Lines Matching defs:dest
131 void move32(Imm32 imm, Register dest) { in move32()
137 void move32(Imm32 imm, const Operand& dest) { movl(imm, dest); } in move32()
138 void move32(Register src, Register dest) { movl(src, dest); } in move32()
139 void move32(Register src, const Operand& dest) { movl(src, dest); } in move32()
186 void convertInt32ToDouble(Register src, FloatRegister dest) { in convertInt32ToDouble()
196 void convertInt32ToDouble(const Address& src, FloatRegister dest) { in convertInt32ToDouble()
199 void convertInt32ToDouble(const BaseIndex& src, FloatRegister dest) { in convertInt32ToDouble()
202 void convertInt32ToDouble(const Operand& src, FloatRegister dest) { in convertInt32ToDouble()
207 void convertInt32ToFloat32(Register src, FloatRegister dest) { in convertInt32ToFloat32()
212 void convertInt32ToFloat32(const Address& src, FloatRegister dest) { in convertInt32ToFloat32()
215 void convertInt32ToFloat32(const Operand& src, FloatRegister dest) { in convertInt32ToFloat32()
267 void load8ZeroExtend(const Operand& src, Register dest) { movzbl(src, dest); } in load8ZeroExtend()
268 void load8ZeroExtend(const Address& src, Register dest) { in load8ZeroExtend()
271 void load8ZeroExtend(const BaseIndex& src, Register dest) { in load8ZeroExtend()
274 void load8SignExtend(const Operand& src, Register dest) { movsbl(src, dest); } in load8SignExtend()
275 void load8SignExtend(const Address& src, Register dest) { in load8SignExtend()
278 void load8SignExtend(const BaseIndex& src, Register dest) { in load8SignExtend()
282 void store8(Imm32 src, const T& dest) { in store8()
286 void store8(Register src, const T& dest) { in store8()
290 void load16ZeroExtend(const Operand& src, Register dest) { in load16ZeroExtend()
293 void load16ZeroExtend(const Address& src, Register dest) { in load16ZeroExtend()
296 void load16ZeroExtend(const BaseIndex& src, Register dest) { in load16ZeroExtend()
300 void load16UnalignedZeroExtend(const S& src, Register dest) { in load16UnalignedZeroExtend()
304 void store16(const S& src, const T& dest) { in store16()
308 void store16Unaligned(const S& src, const T& dest) { in store16Unaligned()
311 void load16SignExtend(const Operand& src, Register dest) { in load16SignExtend()
314 void load16SignExtend(const Address& src, Register dest) { in load16SignExtend()
317 void load16SignExtend(const BaseIndex& src, Register dest) { in load16SignExtend()
321 void load16UnalignedSignExtend(const S& src, Register dest) { in load16UnalignedSignExtend()
324 void load32(const Address& address, Register dest) { in load32()
327 void load32(const BaseIndex& src, Register dest) { movl(Operand(src), dest); } in load32()
328 void load32(const Operand& src, Register dest) { movl(src, dest); } in load32()
330 void load32Unaligned(const S& src, Register dest) { in load32Unaligned()
334 void store32(const S& src, const T& dest) { in store32()
338 void store32_NoSecondScratch(const S& src, const T& dest) { in store32_NoSecondScratch()
342 void store32Unaligned(const S& src, const T& dest) { in store32Unaligned()
345 void loadDouble(const Address& src, FloatRegister dest) { vmovsd(src, dest); } in loadDouble()
346 void loadDouble(const BaseIndex& src, FloatRegister dest) { in loadDouble()
349 void loadDouble(const Operand& src, FloatRegister dest) { in loadDouble()
361 void moveDouble(FloatRegister src, FloatRegister dest) { in moveDouble()
367 void convertFloat32ToDouble(FloatRegister src, FloatRegister dest) { in convertFloat32ToDouble()
370 void convertDoubleToFloat32(FloatRegister src, FloatRegister dest) { in convertDoubleToFloat32()
374 void loadInt32x4(const Address& addr, FloatRegister dest) { in loadInt32x4()
377 void loadFloat32x4(const Address& addr, FloatRegister dest) { in loadFloat32x4()
387 void convertFloat32x4ToInt32x4(FloatRegister src, FloatRegister dest) { in convertFloat32x4ToInt32x4()
394 void convertInt32x4ToFloat32x4(FloatRegister src, FloatRegister dest) { in convertInt32x4ToFloat32x4()
562 void zeroSimd128Float(FloatRegister dest) { vxorps(dest, dest, dest); } in zeroSimd128Float()
563 void zeroSimd128Int(FloatRegister dest) { vpxor(dest, dest, dest); } in zeroSimd128Int()
574 void loadAlignedSimd128Int(const Address& src, FloatRegister dest) { in loadAlignedSimd128Int()
577 void loadAlignedSimd128Int(const Operand& src, FloatRegister dest) { in loadAlignedSimd128Int()
580 void storeAlignedSimd128Int(FloatRegister src, const Address& dest) { in storeAlignedSimd128Int()
583 void moveSimd128Int(FloatRegister src, FloatRegister dest) { in moveSimd128Int()
588 FloatRegister moveSimd128IntIfNotAVX(FloatRegister src, FloatRegister dest) { in moveSimd128IntIfNotAVX()
596 FloatRegister selectDestIfAVX(FloatRegister src, FloatRegister dest) { in selectDestIfAVX()
600 void loadUnalignedSimd128Int(const Address& src, FloatRegister dest) { in loadUnalignedSimd128Int()
603 void loadUnalignedSimd128Int(const BaseIndex& src, FloatRegister dest) { in loadUnalignedSimd128Int()
606 void loadUnalignedSimd128Int(const Operand& src, FloatRegister dest) { in loadUnalignedSimd128Int()
609 void storeUnalignedSimd128Int(FloatRegister src, const Address& dest) { in storeUnalignedSimd128Int()
612 void storeUnalignedSimd128Int(FloatRegister src, const BaseIndex& dest) { in storeUnalignedSimd128Int()
615 void storeUnalignedSimd128Int(FloatRegister src, const Operand& dest) { in storeUnalignedSimd128Int()
618 void packedLeftShiftByScalarInt16x8(Imm32 count, FloatRegister dest) { in packedLeftShiftByScalarInt16x8()
622 void packedRightShiftByScalarInt16x8(Imm32 count, FloatRegister dest) { in packedRightShiftByScalarInt16x8()
627 FloatRegister dest) { in packedUnsignedRightShiftByScalarInt16x8()
631 void packedLeftShiftByScalarInt32x4(Imm32 count, FloatRegister dest) { in packedLeftShiftByScalarInt32x4()
635 void packedRightShiftByScalarInt32x4(Imm32 count, FloatRegister dest) { in packedRightShiftByScalarInt32x4()
640 FloatRegister dest) { in packedUnsignedRightShiftByScalarInt32x4()
644 void loadAlignedSimd128Float(const Address& src, FloatRegister dest) { in loadAlignedSimd128Float()
647 void loadAlignedSimd128Float(const Operand& src, FloatRegister dest) { in loadAlignedSimd128Float()
650 void storeAlignedSimd128Float(FloatRegister src, const Address& dest) { in storeAlignedSimd128Float()
653 void moveSimd128Float(FloatRegister src, FloatRegister dest) { in moveSimd128Float()
659 FloatRegister dest) { in moveSimd128FloatIfNotAVX()
667 FloatRegister moveSimd128FloatIfEqual(FloatRegister src, FloatRegister dest, in moveSimd128FloatIfEqual()
677 FloatRegister dest, in moveSimd128FloatIfNotAVXOrOther()
687 void loadUnalignedSimd128(const Operand& src, FloatRegister dest) { in loadUnalignedSimd128()
690 void storeUnalignedSimd128(FloatRegister src, const Operand& dest) { in storeUnalignedSimd128()
702 void shuffleInt32(uint32_t mask, FloatRegister src, FloatRegister dest) { in shuffleInt32()
705 void moveLowInt32(FloatRegister src, Register dest) { vmovd(src, dest); } in moveLowInt32()
707 void moveHighPairToLowPairFloat32(FloatRegister src, FloatRegister dest) { in moveHighPairToLowPairFloat32()
710 void moveFloatAsDouble(Register src, FloatRegister dest) { in moveFloatAsDouble()
714 void loadFloatAsDouble(const Address& src, FloatRegister dest) { in loadFloatAsDouble()
718 void loadFloatAsDouble(const BaseIndex& src, FloatRegister dest) { in loadFloatAsDouble()
722 void loadFloatAsDouble(const Operand& src, FloatRegister dest) { in loadFloatAsDouble()
726 void loadFloat32(const Address& src, FloatRegister dest) { in loadFloat32()
729 void loadFloat32(const BaseIndex& src, FloatRegister dest) { in loadFloat32()
732 void loadFloat32(const Operand& src, FloatRegister dest) { in loadFloat32()
744 void moveFloat32(FloatRegister src, FloatRegister dest) { in moveFloat32()
785 void truncateDoubleToInt32(FloatRegister src, Register dest, Label* fail) { in truncateDoubleToInt32()
794 void truncateFloat32ToInt32(FloatRegister src, Register dest, Label* fail) { in truncateFloat32ToInt32()
803 bool maybeInlineDouble(double d, FloatRegister dest) { in maybeInlineDouble()
821 bool maybeInlineFloat(float f, FloatRegister dest) { in maybeInlineFloat()
830 bool maybeInlineSimd128Int(const SimdConstant& v, const FloatRegister& dest) { in maybeInlineSimd128Int()
842 const FloatRegister& dest) { in maybeInlineSimd128Float()
850 void convertBoolToInt32(Register source, Register dest) { in convertBoolToInt32()
893 void emitSetRegisterIfZero(Register dest) { in emitSetRegisterIfZero()
916 void computeEffectiveAddress(const T& address, Register dest) { in computeEffectiveAddress()
939 FloatRegister dest) { in loadAlignedVector()
952 const Address& dest) { in storeAlignedVector()