198 		outb(DMA1_MODE, DMA37MD_CASCADE | chan);  in isa_dmacascade()
199 		outb(DMA1_SMSK, chan);  in isa_dmacascade()
201 		outb(DMA2_MODE, DMA37MD_CASCADE | (chan & 3));  in isa_dmacascade()
202 		outb(DMA2_SMSK, chan & 3);  in isa_dmacascade()
273 			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_WRITE|chan);  in isa_dmastart()
275 			outb(DMA1_MODE, DMA37MD_AUTO|DMA37MD_READ|chan);  in isa_dmastart()
279 			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|chan);  in isa_dmastart()
281 			outb(DMA1_MODE, DMA37MD_SINGLE|DMA37MD_READ|chan);  in isa_dmastart()
282 		outb(DMA1_FFC, 0);  in isa_dmastart()
286 		outb(waport, phys);  in isa_dmastart()
287 		outb(waport, phys>>8);  in isa_dmastart()
288 		outb(dmapageport[chan], phys>>16);  in isa_dmastart()
291 		outb(waport + 1, --nbytes);  in isa_dmastart()
292 		outb(waport + 1, nbytes>>8);  in isa_dmastart()
295 		outb(DMA1_SMSK, chan);  in isa_dmastart()
306 			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_WRITE|(chan&3));  in isa_dmastart()
308 			outb(DMA2_MODE, DMA37MD_AUTO|DMA37MD_READ|(chan&3));  in isa_dmastart()
312 			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_WRITE|(chan&3));  in isa_dmastart()
314 			outb(DMA2_MODE, DMA37MD_SINGLE|DMA37MD_READ|(chan&3));  in isa_dmastart()
315 		outb(DMA2_FFC, 0);  in isa_dmastart()
319 		outb(waport, phys>>1);  in isa_dmastart()
320 		outb(waport, phys>>9);  in isa_dmastart()
321 		outb(dmapageport[chan], phys>>16);  in isa_dmastart()
325 		outb(waport + 2, --nbytes);  in isa_dmastart()
326 		outb(waport + 2, nbytes>>8);  in isa_dmastart()
329 		outb(DMA2_SMSK, chan & 3);  in isa_dmastart()
349 		outb(chan & 4 ? DMA2_SMSK : DMA1_SMSK, (chan & 3) | 4);  in isa_dmadone()
455 	outb(ffport, 0);		/* clear register LSB flipflop */  in isa_dmastatus()
458 	outb(ffport, 0);		/* clear again */  in isa_dmastatus()
495 		outb(DMA1_SMSK, (chan & 3) | 4 /* disable mask */);  in isa_dmastop()
497 		outb(DMA2_SMSK, (chan & 3) | 4 /* disable mask */);  in isa_dmastop()