53 	int		*regs;  member
165 	sc->regs = via_v2_regs;  in agp_via_attach()
172 			sc->regs = via_v3_regs;  in agp_via_attach()
201 	if (sc->regs == via_v2_regs) {  in agp_via_attach()
203 		pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical | 3, 4);  in agp_via_attach()
206 		pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);  in agp_via_attach()
211 		pci_write_config(dev, sc->regs[REG_ATTBASE], gatt->ag_physical, 4);  in agp_via_attach()
214 		gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);  in agp_via_attach()
215 		pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl | (3 << 7), 4);  in agp_via_attach()
228 	pci_write_config(dev, sc->regs[REG_GARTCTRL], 0, 4);  in agp_via_detach()
229 	pci_write_config(dev, sc->regs[REG_ATTBASE], 0, 4);  in agp_via_detach()
243 	if (sc->regs == via_v2_regs) {  in agp_via_get_aperture()
244 		apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 1);  in agp_via_get_aperture()
255 		apsize = pci_read_config(dev, sc->regs[REG_APSIZE], 2) & 0xfff;  in agp_via_get_aperture()
279 			    pci_read_config(dev, sc->regs[REG_APSIZE], 2));  in agp_via_get_aperture()
291 	if (sc->regs == via_v2_regs) {  in agp_via_set_aperture()
303 		pci_write_config(dev, sc->regs[REG_APSIZE], apsize, 1);  in agp_via_set_aperture()
341 		val = pci_read_config(dev, sc->regs[REG_APSIZE], 2);  in agp_via_set_aperture()
342 		pci_write_config(dev, sc->regs[REG_APSIZE],  in agp_via_set_aperture()
378 	if (sc->regs == via_v2_regs) {  in agp_via_flush_tlb()
379 		pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x8f, 4);  in agp_via_flush_tlb()
380 		pci_write_config(dev, sc->regs[REG_GARTCTRL], 0x0f, 4);  in agp_via_flush_tlb()
382 		gartctrl = pci_read_config(dev, sc->regs[REG_GARTCTRL], 4);  in agp_via_flush_tlb()
383 		pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl &  in agp_via_flush_tlb()
385 		pci_write_config(dev, sc->regs[REG_GARTCTRL], gartctrl, 4);  in agp_via_flush_tlb()