Lines Matching refs:dc
57 dc->ctx->logger
787 const struct dc *dc, in build_mapped_resource() argument
797 dc->res_pool->underlay_pipe_index)) in build_mapped_resource()
810 struct dc *dc, in dce110_validate_bandwidth() argument
820 dc->ctx, in dce110_validate_bandwidth()
821 dc->bw_dceip, in dce110_validate_bandwidth()
822 dc->bw_vbios, in dce110_validate_bandwidth()
824 dc->res_pool->pipe_count, in dce110_validate_bandwidth()
835 if (memcmp(&dc->current_state->bw.dce, in dce110_validate_bandwidth()
940 struct dc *dc, in dce110_validate_global() argument
950 struct dc *dc, in dce110_add_stream_to_ctx() argument
956 result = resource_map_pool_resources(dc, new_ctx, dc_stream); in dce110_add_stream_to_ctx()
959 result = resource_map_clock_resources(dc, new_ctx, dc_stream); in dce110_add_stream_to_ctx()
963 result = build_mapped_resource(dc, new_ctx, dc_stream); in dce110_add_stream_to_ctx()
973 struct dc *dc = stream->ctx->dc; in dce110_acquire_underlay() local
990 if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { in dce110_acquire_underlay()
992 struct dc_bios *dcb = dc->ctx->dc_bios; in dce110_acquire_underlay()
994 dc->hwss.enable_display_power_gating( in dce110_acquire_underlay()
995 dc, in dce110_acquire_underlay()
1019 color_space_to_black_color(dc, in dce110_acquire_underlay()
1081 ctx->dc->caps.max_slave_planes = 1; in underlay_create()
1082 ctx->dc->caps.max_slave_planes = 1; in underlay_create()
1087 static void bw_calcs_data_update_from_pplib(struct dc *dc) in bw_calcs_data_update_from_pplib() argument
1093 dc->ctx, in bw_calcs_data_update_from_pplib()
1097 dc->bw_vbios->high_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1099 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1101 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1103 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1105 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1107 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1109 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1111 dc->bw_vbios->low_sclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1113 dc->sclk_lvls = clks; in bw_calcs_data_update_from_pplib()
1117 dc->ctx, in bw_calcs_data_update_from_pplib()
1120 dc->bw_vbios->high_voltage_max_dispclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1122 dc->bw_vbios->mid_voltage_max_dispclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1124 dc->bw_vbios->low_voltage_max_dispclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1129 dc->ctx, in bw_calcs_data_update_from_pplib()
1133 dc->bw_vbios->low_yclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1135 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1138 dc->bw_vbios->high_yclk = bw_frc_to_fixed( in bw_calcs_data_update_from_pplib()
1155 struct dc *dc, in construct() argument
1160 struct dc_context *ctx = dc->ctx; in construct()
1177 dc->caps.max_downscale_ratio = 150; in construct()
1178 dc->caps.i2c_speed_in_khz = 100; in construct()
1179 dc->caps.max_cursor_size = 128; in construct()
1180 dc->caps.is_apu = true; in construct()
1258 init_data.ctx = dc->ctx; in construct()
1314 dc->fbc_compressor = dce110_compressor_create(ctx); in construct()
1319 if (!resource_construct(num_virtual_links, dc, &pool->base, in construct()
1324 dce110_hw_sequencer_construct(dc); in construct()
1326 dc->caps.max_planes = pool->base.pipe_count; in construct()
1328 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); in construct()
1330 bw_calcs_data_update_from_pplib(dc); in construct()
1341 struct dc *dc, in dce110_create_resource_pool() argument
1350 if (construct(num_virtual_links, dc, pool, asic_id)) in dce110_create_resource_pool()