42 	dpp->tf_regs->reg
45 	dpp->base.ctx
49 	dpp->tf_shift->field_name, dpp->tf_mask->field_name
101 void dpp_read_state(struct dpp *dpp_base,  in dpp_read_state()
104 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp_read_state()  local
127 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
138 		struct dpp *dpp,  in dpp_get_optimal_number_of_taps()  argument
151 		dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&  in dpp_get_optimal_number_of_taps()
157 		dpp->ctx->dc->debug.max_downscale_src_width != 0 &&  in dpp_get_optimal_number_of_taps()
158 		scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)  in dpp_get_optimal_number_of_taps()
194 	if (!dpp->ctx->dc->debug.always_scale) {  in dpp_get_optimal_number_of_taps()
208 void dpp_reset(struct dpp *dpp_base)  in dpp_reset()
210 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp_reset()  local
212 	dpp->filter_h_c = NULL;  in dpp_reset()
213 	dpp->filter_v_c = NULL;  in dpp_reset()
214 	dpp->filter_h = NULL;  in dpp_reset()
215 	dpp->filter_v = NULL;  in dpp_reset()
217 	memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));  in dpp_reset()
218 	memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));  in dpp_reset()
224 	struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)  in dpp1_cm_set_regamma_pwl()
226 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_cm_set_regamma_pwl()  local
240 		re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;  in dpp1_cm_set_regamma_pwl()
241 		if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)  in dpp1_cm_set_regamma_pwl()
245 		dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);  in dpp1_cm_set_regamma_pwl()
247 		if (dpp->is_write_to_ram_a_safe)  in dpp1_cm_set_regamma_pwl()
254 		dpp->pwl_data = *params;  in dpp1_cm_set_regamma_pwl()
256 		re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;  in dpp1_cm_set_regamma_pwl()
257 		dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;  in dpp1_cm_set_regamma_pwl()
279 		struct dpp *dpp_base,  in dpp1_set_degamma_format_float()
282 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_set_degamma_format_float()  local
294 		struct dpp *dpp_base,  in dpp1_cnv_setup()
306 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_cnv_setup()  local
428 		struct dpp *dpp_base,  in dpp1_set_cursor_attributes()
431 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_set_cursor_attributes()  local
448 		struct dpp *dpp_base,  in dpp1_set_cursor_position()
453 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_set_cursor_position()  local
469 		struct dpp *dpp_base,  in dpp1_cnv_set_optional_cursor_attributes()
472 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_cnv_set_optional_cursor_attributes()  local
481 		struct dpp *dpp_base,  in dpp1_dppclk_control()
485 	struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);  in dpp1_dppclk_control()  local
488 		if (dpp->tf_mask->DPPCLK_RATE_CONTROL)  in dpp1_dppclk_control()
535 	struct dcn10_dpp *dpp,  in dpp1_construct()  argument
542 	dpp->base.ctx = ctx;  in dpp1_construct()
544 	dpp->base.inst = inst;  in dpp1_construct()
545 	dpp->base.funcs = &dcn10_dpp_funcs;  in dpp1_construct()
546 	dpp->base.caps = &dcn10_dpp_cap;  in dpp1_construct()
548 	dpp->tf_regs = tf_regs;  in dpp1_construct()
549 	dpp->tf_shift = tf_shift;  in dpp1_construct()
550 	dpp->tf_mask = tf_mask;  in dpp1_construct()
552 	dpp->lb_pixel_depth_supported =  in dpp1_construct()
557 	dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;  in dpp1_construct()
558 	dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/  in dpp1_construct()