Lines Matching refs:rps
6000 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_rps_limits() local
6010 limits = (rps->max_freq_softlimit) << 23; in intel_rps_limits()
6011 if (val <= rps->min_freq_softlimit) in intel_rps_limits()
6012 limits |= (rps->min_freq_softlimit) << 14; in intel_rps_limits()
6014 limits = rps->max_freq_softlimit << 24; in intel_rps_limits()
6015 if (val <= rps->min_freq_softlimit) in intel_rps_limits()
6016 limits |= rps->min_freq_softlimit << 16; in intel_rps_limits()
6024 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_set_rps_thresholds() local
6029 new_power = rps->power; in gen6_set_rps_thresholds()
6030 switch (rps->power) { in gen6_set_rps_thresholds()
6032 if (val > rps->efficient_freq + 1 && in gen6_set_rps_thresholds()
6033 val > rps->cur_freq) in gen6_set_rps_thresholds()
6038 if (val <= rps->efficient_freq && in gen6_set_rps_thresholds()
6039 val < rps->cur_freq) in gen6_set_rps_thresholds()
6041 else if (val >= rps->rp0_freq && in gen6_set_rps_thresholds()
6042 val > rps->cur_freq) in gen6_set_rps_thresholds()
6047 if (val < (rps->rp1_freq + rps->rp0_freq) >> 1 && in gen6_set_rps_thresholds()
6048 val < rps->cur_freq) in gen6_set_rps_thresholds()
6053 if (val <= rps->min_freq_softlimit) in gen6_set_rps_thresholds()
6055 if (val >= rps->max_freq_softlimit) in gen6_set_rps_thresholds()
6057 if (new_power == rps->power) in gen6_set_rps_thresholds()
6120 rps->power = new_power; in gen6_set_rps_thresholds()
6121 rps->up_threshold = threshold_up; in gen6_set_rps_thresholds()
6122 rps->down_threshold = threshold_down; in gen6_set_rps_thresholds()
6123 rps->last_adj = 0; in gen6_set_rps_thresholds()
6128 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_pm_mask() local
6132 if (val > rps->min_freq_softlimit) in gen6_rps_pm_mask()
6134 if (val < rps->max_freq_softlimit) in gen6_rps_pm_mask()
6147 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_set_rps() local
6152 if (val != rps->cur_freq) { in gen6_set_rps()
6174 rps->cur_freq = val; in gen6_set_rps()
6190 if (val != dev_priv->gt_pm.rps.cur_freq) { in valleyview_set_rps()
6198 dev_priv->gt_pm.rps.cur_freq = val; in valleyview_set_rps()
6213 struct intel_rps *rps = &dev_priv->gt_pm.rps; in vlv_set_rps_idle() local
6214 u32 val = rps->idle_freq; in vlv_set_rps_idle()
6217 if (rps->cur_freq <= val) in vlv_set_rps_idle()
6242 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_busy() local
6245 if (rps->enabled) { in gen6_rps_busy()
6251 gen6_rps_pm_mask(dev_priv, rps->cur_freq)); in gen6_rps_busy()
6258 freq = max(rps->cur_freq, in gen6_rps_busy()
6259 rps->efficient_freq); in gen6_rps_busy()
6263 rps->min_freq_softlimit, in gen6_rps_busy()
6264 rps->max_freq_softlimit))) in gen6_rps_busy()
6272 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_rps_idle() local
6282 if (rps->enabled) { in gen6_rps_idle()
6286 gen6_set_rps(dev_priv, rps->idle_freq); in gen6_rps_idle()
6287 rps->last_adj = 0; in gen6_rps_idle()
6297 struct intel_rps *rps = &rq->i915->gt_pm.rps; in gen6_rps_boost() local
6304 if (!rps->enabled) in gen6_rps_boost()
6310 atomic_inc(&rps->num_waiters); in gen6_rps_boost()
6318 if (READ_ONCE(rps->cur_freq) < rps->boost_freq) in gen6_rps_boost()
6319 schedule_work(&rps->work); in gen6_rps_boost()
6321 atomic_inc(rps_client ? &rps_client->boosts : &rps->boosts); in gen6_rps_boost()
6326 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_set_rps() local
6330 GEM_BUG_ON(val > rps->max_freq); in intel_set_rps()
6331 GEM_BUG_ON(val < rps->min_freq); in intel_set_rps()
6333 if (!rps->enabled) { in intel_set_rps()
6334 rps->cur_freq = val; in intel_set_rps()
6516 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_init_rps_frequencies() local
6523 rps->rp0_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
6524 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
6525 rps->min_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
6528 rps->rp0_freq = (rp_state_cap >> 0) & 0xff; in gen6_init_rps_frequencies()
6529 rps->rp1_freq = (rp_state_cap >> 8) & 0xff; in gen6_init_rps_frequencies()
6530 rps->min_freq = (rp_state_cap >> 16) & 0xff; in gen6_init_rps_frequencies()
6533 rps->max_freq = rps->rp0_freq; in gen6_init_rps_frequencies()
6535 rps->efficient_freq = rps->rp1_freq; in gen6_init_rps_frequencies()
6543 rps->efficient_freq = in gen6_init_rps_frequencies()
6546 rps->min_freq, in gen6_init_rps_frequencies()
6547 rps->max_freq); in gen6_init_rps_frequencies()
6554 rps->rp0_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
6555 rps->rp1_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
6556 rps->min_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
6557 rps->max_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
6558 rps->efficient_freq *= GEN9_FREQ_SCALER; in gen6_init_rps_frequencies()
6565 struct intel_rps *rps = &dev_priv->gt_pm.rps; in reset_rps() local
6566 u8 freq = rps->cur_freq; in reset_rps()
6569 rps->power = -1; in reset_rps()
6570 rps->cur_freq = -1; in reset_rps()
6583 GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); in gen9_enable_rps()
6703 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen8_enable_rps() local
6709 HSW_FREQUENCY(rps->rp1_freq)); in gen8_enable_rps()
6711 HSW_FREQUENCY(rps->rp1_freq)); in gen8_enable_rps()
6717 rps->max_freq_softlimit << 24 | in gen8_enable_rps()
6718 rps->min_freq_softlimit << 16); in gen8_enable_rps()
6841 struct intel_rps *rps = &dev_priv->gt_pm.rps; in gen6_update_ring_freq() local
6875 min_gpu_freq = rps->min_freq / GEN9_FREQ_SCALER; in gen6_update_ring_freq()
6876 max_gpu_freq = rps->max_freq / GEN9_FREQ_SCALER; in gen6_update_ring_freq()
6878 min_gpu_freq = rps->min_freq; in gen6_update_ring_freq()
6879 max_gpu_freq = rps->max_freq; in gen6_update_ring_freq()
7130 dev_priv->gt_pm.rps.gpll_ref_freq = in vlv_init_gpll_ref_freq()
7136 dev_priv->gt_pm.rps.gpll_ref_freq); in vlv_init_gpll_ref_freq()
7141 struct intel_rps *rps = &dev_priv->gt_pm.rps; in valleyview_init_gt_powersave() local
7163 rps->max_freq = valleyview_rps_max_freq(dev_priv); in valleyview_init_gt_powersave()
7164 rps->rp0_freq = rps->max_freq; in valleyview_init_gt_powersave()
7166 intel_gpu_freq(dev_priv, rps->max_freq), in valleyview_init_gt_powersave()
7167 rps->max_freq); in valleyview_init_gt_powersave()
7169 rps->efficient_freq = valleyview_rps_rpe_freq(dev_priv); in valleyview_init_gt_powersave()
7171 intel_gpu_freq(dev_priv, rps->efficient_freq), in valleyview_init_gt_powersave()
7172 rps->efficient_freq); in valleyview_init_gt_powersave()
7174 rps->rp1_freq = valleyview_rps_guar_freq(dev_priv); in valleyview_init_gt_powersave()
7176 intel_gpu_freq(dev_priv, rps->rp1_freq), in valleyview_init_gt_powersave()
7177 rps->rp1_freq); in valleyview_init_gt_powersave()
7179 rps->min_freq = valleyview_rps_min_freq(dev_priv); in valleyview_init_gt_powersave()
7181 intel_gpu_freq(dev_priv, rps->min_freq), in valleyview_init_gt_powersave()
7182 rps->min_freq); in valleyview_init_gt_powersave()
7187 struct intel_rps *rps = &dev_priv->gt_pm.rps; in cherryview_init_gt_powersave() local
7208 rps->max_freq = cherryview_rps_max_freq(dev_priv); in cherryview_init_gt_powersave()
7209 rps->rp0_freq = rps->max_freq; in cherryview_init_gt_powersave()
7211 intel_gpu_freq(dev_priv, rps->max_freq), in cherryview_init_gt_powersave()
7212 rps->max_freq); in cherryview_init_gt_powersave()
7214 rps->efficient_freq = cherryview_rps_rpe_freq(dev_priv); in cherryview_init_gt_powersave()
7216 intel_gpu_freq(dev_priv, rps->efficient_freq), in cherryview_init_gt_powersave()
7217 rps->efficient_freq); in cherryview_init_gt_powersave()
7219 rps->rp1_freq = cherryview_rps_guar_freq(dev_priv); in cherryview_init_gt_powersave()
7221 intel_gpu_freq(dev_priv, rps->rp1_freq), in cherryview_init_gt_powersave()
7222 rps->rp1_freq); in cherryview_init_gt_powersave()
7224 rps->min_freq = cherryview_rps_min_freq(dev_priv); in cherryview_init_gt_powersave()
7226 intel_gpu_freq(dev_priv, rps->min_freq), in cherryview_init_gt_powersave()
7227 rps->min_freq); in cherryview_init_gt_powersave()
7229 WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq | in cherryview_init_gt_powersave()
7230 rps->min_freq) & 1, in cherryview_init_gt_powersave()
7611 pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq)); in __i915_gfx_val()
7900 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_init_gt_powersave() local
7923 rps->idle_freq = rps->min_freq; in intel_init_gt_powersave()
7924 rps->cur_freq = rps->idle_freq; in intel_init_gt_powersave()
7926 rps->max_freq_softlimit = rps->max_freq; in intel_init_gt_powersave()
7927 rps->min_freq_softlimit = rps->min_freq; in intel_init_gt_powersave()
7930 rps->min_freq_softlimit = in intel_init_gt_powersave()
7932 rps->efficient_freq, in intel_init_gt_powersave()
7943 (rps->max_freq & 0xff) * 50, in intel_init_gt_powersave()
7945 rps->max_freq = params & 0xff; in intel_init_gt_powersave()
7950 rps->boost_freq = rps->max_freq; in intel_init_gt_powersave()
7988 dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */ in intel_sanitize_gt_powersave()
8030 if (!dev_priv->gt_pm.rps.enabled) in intel_disable_rps()
8044 dev_priv->gt_pm.rps.enabled = false; in intel_disable_rps()
8094 struct intel_rps *rps = &dev_priv->gt_pm.rps; in intel_enable_rps() local
8098 if (rps->enabled) in intel_enable_rps()
8116 WARN_ON(rps->max_freq < rps->min_freq); in intel_enable_rps()
8117 WARN_ON(rps->idle_freq > rps->max_freq); in intel_enable_rps()
8119 WARN_ON(rps->efficient_freq < rps->min_freq); in intel_enable_rps()
8120 WARN_ON(rps->efficient_freq > rps->max_freq); in intel_enable_rps()
8122 rps->enabled = true; in intel_enable_rps()
9358 struct intel_rps *rps = &dev_priv->gt_pm.rps; in byt_gpu_freq() local
9364 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * (val - 0xb7), 1000); in byt_gpu_freq()
9369 struct intel_rps *rps = &dev_priv->gt_pm.rps; in byt_freq_opcode() local
9371 return DIV_ROUND_CLOSEST(1000 * val, rps->gpll_ref_freq) + 0xb7; in byt_freq_opcode()
9376 struct intel_rps *rps = &dev_priv->gt_pm.rps; in chv_gpu_freq() local
9382 return DIV_ROUND_CLOSEST(rps->gpll_ref_freq * val, 2 * 2 * 1000); in chv_gpu_freq()
9387 struct intel_rps *rps = &dev_priv->gt_pm.rps; in chv_freq_opcode() local
9390 return DIV_ROUND_CLOSEST(2 * 1000 * val, rps->gpll_ref_freq) * 2; in chv_freq_opcode()
9425 atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0); in intel_pm_setup()