3809 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()  local
3819 		reset_mask |= RADEON_RESET_GFX;  in evergreen_gpu_check_soft_reset()
3823 		reset_mask |= RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3826 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3831 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3836 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3841 		reset_mask |= RADEON_RESET_RLC;  in evergreen_gpu_check_soft_reset()
3844 		reset_mask |= RADEON_RESET_IH;  in evergreen_gpu_check_soft_reset()
3847 		reset_mask |= RADEON_RESET_SEM;  in evergreen_gpu_check_soft_reset()
3850 		reset_mask |= RADEON_RESET_GRBM;  in evergreen_gpu_check_soft_reset()
3853 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3857 		reset_mask |= RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3860 		reset_mask |= RADEON_RESET_DISPLAY;  in evergreen_gpu_check_soft_reset()
3865 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3868 	if (reset_mask & RADEON_RESET_MC) {  in evergreen_gpu_check_soft_reset()
3869 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3870 		reset_mask &= ~RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3873 	return reset_mask;  in evergreen_gpu_check_soft_reset()
3876 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in evergreen_gpu_soft_reset()  argument
3882 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3885 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3892 	if (reset_mask & RADEON_RESET_DMA) {  in evergreen_gpu_soft_reset()
3906 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in evergreen_gpu_soft_reset()
3920 	if (reset_mask & RADEON_RESET_CP) {  in evergreen_gpu_soft_reset()
3927 	if (reset_mask & RADEON_RESET_DMA)  in evergreen_gpu_soft_reset()
3930 	if (reset_mask & RADEON_RESET_DISPLAY)  in evergreen_gpu_soft_reset()
3933 	if (reset_mask & RADEON_RESET_RLC)  in evergreen_gpu_soft_reset()
3936 	if (reset_mask & RADEON_RESET_SEM)  in evergreen_gpu_soft_reset()
3939 	if (reset_mask & RADEON_RESET_IH)  in evergreen_gpu_soft_reset()
3942 	if (reset_mask & RADEON_RESET_GRBM)  in evergreen_gpu_soft_reset()
3945 	if (reset_mask & RADEON_RESET_VMC)  in evergreen_gpu_soft_reset()
3949 		if (reset_mask & RADEON_RESET_MC)  in evergreen_gpu_soft_reset()
4034 	u32 reset_mask;  in evergreen_asic_reset()  local
4041 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4043 	if (reset_mask)  in evergreen_asic_reset()
4047 	evergreen_gpu_soft_reset(rdev, reset_mask);  in evergreen_asic_reset()
4049 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4052 	if (reset_mask && radeon_hard_reset)  in evergreen_asic_reset()
4055 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4057 	if (!reset_mask)  in evergreen_asic_reset()
4074 	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_gfx_is_lockup()  local
4076 	if (!(reset_mask & (RADEON_RESET_GFX |  in evergreen_gfx_is_lockup()