724 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
733 struct ni_ps *ni_get_ps(struct radeon_ps *rps)  in ni_get_ps()  argument
735 	struct ni_ps *ps = rps->ps_priv;  in ni_get_ps()
786 					struct radeon_ps *rps)  in ni_apply_state_adjust_rules()  argument
788 	struct ni_ps *ps = ni_get_ps(rps);  in ni_apply_state_adjust_rules()
3560 			  struct radeon_ps *rps)  in ni_update_current_ps()  argument
3562 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_current_ps()
3566 	eg_pi->current_rps = *rps;  in ni_update_current_ps()
3572 			    struct radeon_ps *rps)  in ni_update_requested_ps()  argument
3574 	struct ni_ps *new_ps = ni_get_ps(rps);  in ni_update_requested_ps()
3578 	eg_pi->requested_rps = *rps;  in ni_update_requested_ps()
3893 					  struct radeon_ps *rps,  in ni_parse_pplib_non_clock_info()  argument
3897 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in ni_parse_pplib_non_clock_info()
3898 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in ni_parse_pplib_non_clock_info()
3899 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in ni_parse_pplib_non_clock_info()
3902 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in ni_parse_pplib_non_clock_info()
3903 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in ni_parse_pplib_non_clock_info()
3904 	} else if (r600_is_uvd_state(rps->class, rps->class2)) {  in ni_parse_pplib_non_clock_info()
3905 		rps->vclk = RV770_DEFAULT_VCLK_FREQ;  in ni_parse_pplib_non_clock_info()
3906 		rps->dclk = RV770_DEFAULT_DCLK_FREQ;  in ni_parse_pplib_non_clock_info()
3908 		rps->vclk = 0;  in ni_parse_pplib_non_clock_info()
3909 		rps->dclk = 0;  in ni_parse_pplib_non_clock_info()
3912 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in ni_parse_pplib_non_clock_info()
3913 		rdev->pm.dpm.boot_ps = rps;  in ni_parse_pplib_non_clock_info()
3914 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in ni_parse_pplib_non_clock_info()
3915 		rdev->pm.dpm.uvd_ps = rps;  in ni_parse_pplib_non_clock_info()
3919 				      struct radeon_ps *rps, int index,  in ni_parse_pplib_clock_info()  argument
3924 	struct ni_ps *ps = ni_get_ps(rps);  in ni_parse_pplib_clock_info()
3944 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in ni_parse_pplib_clock_info()
3953 	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {  in ni_parse_pplib_clock_info()
3965 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in ni_parse_pplib_clock_info()
3974 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==  in ni_parse_pplib_clock_info()
4278 			      struct radeon_ps *rps)  in ni_dpm_print_power_state()  argument
4280 	struct ni_ps *ps = ni_get_ps(rps);  in ni_dpm_print_power_state()
4284 	r600_dpm_print_class_info(rps->class, rps->class2);  in ni_dpm_print_power_state()
4285 	r600_dpm_print_cap_info(rps->caps);  in ni_dpm_print_power_state()
4286 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ni_dpm_print_power_state()
4296 	r600_dpm_print_ps_status(rdev, rps);  in ni_dpm_print_power_state()
4303 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_debugfs_print_current_performance_level()  local
4304 	struct ni_ps *ps = ni_get_ps(rps);  in ni_dpm_debugfs_print_current_performance_level()
4314 		seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ni_dpm_debugfs_print_current_performance_level()
4323 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_get_current_sclk()  local
4324 	struct ni_ps *ps = ni_get_ps(rps);  in ni_dpm_get_current_sclk()
4341 	struct radeon_ps *rps = &eg_pi->current_rps;  in ni_dpm_get_current_mclk()  local
4342 	struct ni_ps *ps = ni_get_ps(rps);  in ni_dpm_get_current_mclk()