1608 	u32 reset_mask = 0;  in r600_gpu_check_soft_reset()  local
1619 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1626 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1631 		reset_mask |= RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1634 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1639 		reset_mask |= RADEON_RESET_DMA;  in r600_gpu_check_soft_reset()
1644 		reset_mask |= RADEON_RESET_RLC;  in r600_gpu_check_soft_reset()
1647 		reset_mask |= RADEON_RESET_IH;  in r600_gpu_check_soft_reset()
1650 		reset_mask |= RADEON_RESET_SEM;  in r600_gpu_check_soft_reset()
1653 		reset_mask |= RADEON_RESET_GRBM;  in r600_gpu_check_soft_reset()
1656 		reset_mask |= RADEON_RESET_VMC;  in r600_gpu_check_soft_reset()
1661 		reset_mask |= RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1664 		reset_mask |= RADEON_RESET_DISPLAY;  in r600_gpu_check_soft_reset()
1667 	if (reset_mask & RADEON_RESET_MC) {  in r600_gpu_check_soft_reset()
1668 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in r600_gpu_check_soft_reset()
1669 		reset_mask &= ~RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1672 	return reset_mask;  in r600_gpu_check_soft_reset()
1675 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in r600_gpu_soft_reset()  argument
1681 	if (reset_mask == 0)  in r600_gpu_soft_reset()
1684 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in r600_gpu_soft_reset()
1697 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1711 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in r600_gpu_soft_reset()
1740 	if (reset_mask & RADEON_RESET_CP) {  in r600_gpu_soft_reset()
1747 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1754 	if (reset_mask & RADEON_RESET_RLC)  in r600_gpu_soft_reset()
1757 	if (reset_mask & RADEON_RESET_SEM)  in r600_gpu_soft_reset()
1760 	if (reset_mask & RADEON_RESET_IH)  in r600_gpu_soft_reset()
1763 	if (reset_mask & RADEON_RESET_GRBM)  in r600_gpu_soft_reset()
1767 		if (reset_mask & RADEON_RESET_MC)  in r600_gpu_soft_reset()
1771 	if (reset_mask & RADEON_RESET_VMC)  in r600_gpu_soft_reset()
1874 	u32 reset_mask;  in r600_asic_reset()  local
1881 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1883 	if (reset_mask)  in r600_asic_reset()
1887 	r600_gpu_soft_reset(rdev, reset_mask);  in r600_asic_reset()
1889 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1892 	if (reset_mask && radeon_hard_reset)  in r600_asic_reset()
1895 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1897 	if (!reset_mask)  in r600_asic_reset()
1914 	u32 reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_gfx_is_lockup()  local
1916 	if (!(reset_mask & (RADEON_RESET_GFX |  in r600_gfx_is_lockup()