3762 	u32 reset_mask = 0;  in si_gpu_check_soft_reset()  local
3773 		reset_mask |= RADEON_RESET_GFX;  in si_gpu_check_soft_reset()
3777 		reset_mask |= RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3780 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3785 		reset_mask |= RADEON_RESET_RLC;  in si_gpu_check_soft_reset()
3790 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3795 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3800 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3803 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3809 		reset_mask |= RADEON_RESET_IH;  in si_gpu_check_soft_reset()
3812 		reset_mask |= RADEON_RESET_SEM;  in si_gpu_check_soft_reset()
3815 		reset_mask |= RADEON_RESET_GRBM;  in si_gpu_check_soft_reset()
3818 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3822 		reset_mask |= RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3825 		reset_mask |= RADEON_RESET_DISPLAY;  in si_gpu_check_soft_reset()
3830 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3833 	if (reset_mask & RADEON_RESET_MC) {  in si_gpu_check_soft_reset()
3834 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in si_gpu_check_soft_reset()
3835 		reset_mask &= ~RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3838 	return reset_mask;  in si_gpu_check_soft_reset()
3841 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in si_gpu_soft_reset()  argument
3847 	if (reset_mask == 0)  in si_gpu_soft_reset()
3850 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in si_gpu_soft_reset()
3868 	if (reset_mask & RADEON_RESET_DMA) {  in si_gpu_soft_reset()
3874 	if (reset_mask & RADEON_RESET_DMA1) {  in si_gpu_soft_reset()
3888 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {  in si_gpu_soft_reset()
3903 	if (reset_mask & RADEON_RESET_CP) {  in si_gpu_soft_reset()
3909 	if (reset_mask & RADEON_RESET_DMA)  in si_gpu_soft_reset()
3912 	if (reset_mask & RADEON_RESET_DMA1)  in si_gpu_soft_reset()
3915 	if (reset_mask & RADEON_RESET_DISPLAY)  in si_gpu_soft_reset()
3918 	if (reset_mask & RADEON_RESET_RLC)  in si_gpu_soft_reset()
3921 	if (reset_mask & RADEON_RESET_SEM)  in si_gpu_soft_reset()
3924 	if (reset_mask & RADEON_RESET_IH)  in si_gpu_soft_reset()
3927 	if (reset_mask & RADEON_RESET_GRBM)  in si_gpu_soft_reset()
3930 	if (reset_mask & RADEON_RESET_VMC)  in si_gpu_soft_reset()
3933 	if (reset_mask & RADEON_RESET_MC)  in si_gpu_soft_reset()
4075 	u32 reset_mask;  in si_asic_reset()  local
4082 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4084 	if (reset_mask)  in si_asic_reset()
4088 	si_gpu_soft_reset(rdev, reset_mask);  in si_asic_reset()
4090 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4093 	if (reset_mask && radeon_hard_reset)  in si_asic_reset()
4096 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4098 	if (!reset_mask)  in si_asic_reset()
4115 	u32 reset_mask = si_gpu_check_soft_reset(rdev);  in si_gfx_is_lockup()  local
4117 	if (!(reset_mask & (RADEON_RESET_GFX |  in si_gfx_is_lockup()