76 	outb(IO_ICU1, 0x11);		/* reset; program device, four bytes */  in icu_init()
77 	outb(IO_ICU1 + ICU_IMR_OFFSET, IDT_OFFSET);  in icu_init()
79 	outb(IO_ICU1 + ICU_IMR_OFFSET, 1 << ICU_IRQ_SLAVE);  in icu_init()
81 	outb(IO_ICU1 + ICU_IMR_OFFSET, auto_eoi | 1); /* 8086 mode */  in icu_init()
83 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */  in icu_init()
84 	outb(IO_ICU1, 0x0a);		/* default to IRR on read */  in icu_init()
85 	outb(IO_ICU1, 0xc0 | (3 - 1));	/* pri order 3-7, 0-2 (com2 first) */  in icu_init()
90 	outb(IO_ICU2, 0x11);		/* reset; program device, four bytes */  in icu_init()
91 	outb(IO_ICU2 + ICU_IMR_OFFSET, IDT_OFFSET + 8);  in icu_init()
93 	outb(IO_ICU2 + ICU_IMR_OFFSET, ICU_IRQ_SLAVE);  in icu_init()
95 	outb(IO_ICU2 + ICU_IMR_OFFSET, 2 | 1); /* auto EOI, 8086 mode */  in icu_init()
97 	outb(IO_ICU2 + ICU_IMR_OFFSET, 1); /* 8086 mode */  in icu_init()
100 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff); /* leave interrupts masked */  in icu_init()
101 	outb(IO_ICU2, 0x0a);		/* default to IRR on read */  in icu_init()
115 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);  in icu_definit()
116 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);  in icu_definit()
176 	outb(IO_ICU1, 0x13);  in icu_ioapic_extint()
177 	outb(IO_ICU1 + 1, vec);		/* start vector (unused) */  in icu_ioapic_extint()
178 	outb(IO_ICU1 + 1, 0x00);	/* ignore slave */  in icu_ioapic_extint()
179 	outb(IO_ICU1 + 1, 0x03);	/* auto EOI, 8086 */  in icu_ioapic_extint()
180 	outb(IO_ICU1 + 1, mask);  in icu_ioapic_extint()
198 	outb(IO_ICU1 + ICU_IMR_OFFSET, 0xff);  in icu_reinit_noioapic()
199 	outb(IO_ICU2 + ICU_IMR_OFFSET, 0xff);  in icu_reinit_noioapic()