Lines Matching refs:VirtReg
205 Register VirtReg; ///< Virtual register number. member
211 explicit LiveReg(Register VirtReg) : VirtReg(VirtReg) {} in LiveReg()
214 return Register::virtReg2Index(VirtReg); in getSparseSetIndex()
368 LiveRegMap::iterator findLiveVirtReg(Register VirtReg) { in findLiveVirtReg() argument
369 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
372 LiveRegMap::const_iterator findLiveVirtReg(Register VirtReg) const { in findLiveVirtReg()
373 return LiveVirtRegs.find(Register::virtReg2Index(VirtReg)); in findLiveVirtReg()
380 void assignDanglingDebugValues(MachineInstr &Def, Register VirtReg,
383 Register VirtReg);
384 bool defineVirtReg(MachineInstr &MI, unsigned OpNum, Register VirtReg,
386 bool useVirtReg(MachineInstr &MI, MachineOperand &MO, Register VirtReg);
395 Register traceCopies(Register VirtReg) const;
399 int getStackSpaceFor(Register VirtReg);
400 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
402 void reload(MachineBasicBlock::iterator Before, Register VirtReg,
405 bool mayLiveOut(Register VirtReg);
406 bool mayLiveIn(Register VirtReg);
439 int RegAllocFast::getStackSpaceFor(Register VirtReg) { in getStackSpaceFor() argument
441 int SS = StackSlotForVirtReg[VirtReg]; in getStackSpaceFor()
447 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in getStackSpaceFor()
453 StackSlotForVirtReg[VirtReg] = FrameIdx; in getStackSpaceFor()
467 bool RegAllocFast::mayLiveOut(Register VirtReg) { in mayLiveOut() argument
468 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) { in mayLiveOut()
479 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveOut()
481 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
489 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
498 for (const MachineInstr &UseInst : MRI->use_nodbg_instructions(VirtReg)) { in mayLiveOut()
500 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
510 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveOut()
520 bool RegAllocFast::mayLiveIn(Register VirtReg) { in mayLiveIn() argument
521 if (MayLiveAcrossBlocks.test(Register::virtReg2Index(VirtReg))) in mayLiveIn()
527 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn()
529 MayLiveAcrossBlocks.set(Register::virtReg2Index(VirtReg)); in mayLiveIn()
539 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill() argument
541 LLVM_DEBUG(dbgs() << "Spilling " << printReg(VirtReg, TRI) << " in " in spill()
543 int FI = getStackSpaceFor(VirtReg); in spill()
546 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in spill()
548 VirtReg); in spill()
556 SmallVectorImpl<MachineOperand *> &LRIDbgOperands = LiveDbgValueMap[VirtReg]; in spill()
599 void RegAllocFast::reload(MachineBasicBlock::iterator Before, Register VirtReg, in reload() argument
601 LLVM_DEBUG(dbgs() << "Reloading " << printReg(VirtReg, TRI) << " into " in reload()
603 int FI = getStackSpaceFor(VirtReg); in reload()
604 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in reload()
605 TII->loadRegFromStackSlot(*MBB, Before, PhysReg, FI, &RC, TRI, VirtReg); in reload()
673 reload(MBB.begin(), LR.VirtReg, PhysReg); in reloadAtBegin()
675 reload(InsertBefore, LR.VirtReg, PhysReg); in reloadAtBegin()
704 switch (unsigned VirtReg = RegUnitStates[Unit]) { in displacePhysReg() local
706 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in displacePhysReg()
710 reload(ReloadBefore, VirtReg, LRI->PhysReg); in displacePhysReg()
733 switch (unsigned VirtReg = RegUnitStates[FirstUnit]) { in freePhysReg() local
742 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in freePhysReg()
744 LLVM_DEBUG(dbgs() << ' ' << printReg(LRI->VirtReg, TRI) << '\n'); in freePhysReg()
758 switch (unsigned VirtReg = RegUnitStates[Unit]) { in calcSpillCost() local
766 bool SureSpill = StackSlotForVirtReg[VirtReg] != -1 || in calcSpillCost()
767 findLiveVirtReg(VirtReg)->LiveOut; in calcSpillCost()
776 Register VirtReg, MCPhysReg Reg) { in assignDanglingDebugValues() argument
777 auto UDBGValIter = DanglingDbgValues.find(VirtReg); in assignDanglingDebugValues()
784 if (!DbgValue->hasDebugOperandForReg(VirtReg)) in assignDanglingDebugValues()
800 for (MachineOperand &MO : DbgValue->getDebugOperandsForReg(VirtReg)) { in assignDanglingDebugValues()
814 Register VirtReg = LR.VirtReg; in assignVirtToPhysReg() local
815 LLVM_DEBUG(dbgs() << "Assigning " << printReg(VirtReg, TRI) << " to " in assignVirtToPhysReg()
820 setPhysRegState(PhysReg, VirtReg); in assignVirtToPhysReg()
822 assignDanglingDebugValues(AtMI, VirtReg, PhysReg); in assignVirtToPhysReg()
846 Register RegAllocFast::traceCopies(Register VirtReg) const { in traceCopies()
849 for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) { in traceCopies()
866 const Register VirtReg = LR.VirtReg; in allocVirtReg() local
869 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtReg()
870 LLVM_DEBUG(dbgs() << "Search register for " << printReg(VirtReg) in allocVirtReg()
892 Register Hint1 = traceCopies(VirtReg); in allocVirtReg()
955 Register VirtReg = MO.getReg(); in allocVirtRegUndef() local
956 assert(VirtReg.isVirtual() && "Expected virtreg"); in allocVirtRegUndef()
957 if (!shouldAllocateRegister(VirtReg)) in allocVirtRegUndef()
960 LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg); in allocVirtRegUndef()
965 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in allocVirtRegUndef()
984 Register VirtReg) { in defineLiveThroughVirtReg() argument
985 if (!shouldAllocateRegister(VirtReg)) in defineLiveThroughVirtReg()
987 LiveRegMap::iterator LRI = findLiveVirtReg(VirtReg); in defineLiveThroughVirtReg()
1009 return defineVirtReg(MI, OpNum, VirtReg, true); in defineLiveThroughVirtReg()
1020 Register VirtReg, bool LookAtPhysRegUses) { in defineVirtReg() argument
1021 assert(VirtReg.isVirtual() && "Not a virtual register"); in defineVirtReg()
1022 if (!shouldAllocateRegister(VirtReg)) in defineVirtReg()
1027 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in defineVirtReg()
1030 if (mayLiveOut(VirtReg)) { in defineVirtReg()
1043 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1052 LLVM_DEBUG(dbgs() << "In def of " << printReg(VirtReg, TRI) in defineVirtReg()
1065 spill(SpillBefore, VirtReg, PhysReg, Kill, LRI->LiveOut); in defineVirtReg()
1070 int FI = StackSlotForVirtReg[VirtReg]; in defineVirtReg()
1071 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in defineVirtReg()
1076 &RC, TRI, VirtReg); in defineVirtReg()
1089 BundleVirtRegsMap[VirtReg] = PhysReg; in defineVirtReg()
1098 Register VirtReg) { in useVirtReg() argument
1099 assert(VirtReg.isVirtual() && "Not a virtual register"); in useVirtReg()
1100 if (!shouldAllocateRegister(VirtReg)) in useVirtReg()
1104 std::tie(LRI, New) = LiveVirtRegs.insert(LiveReg(VirtReg)); in useVirtReg()
1107 if (mayLiveOut(VirtReg)) { in useVirtReg()
1134 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg); in useVirtReg()
1145 BundleVirtRegsMap[VirtReg] = LRI->PhysReg; in useVirtReg()
1196 switch (unsigned VirtReg = RegUnitStates[Unit]) { in dumpState() local
1205 dbgs() << ' ' << printRegUnit(Unit, TRI) << '=' << printReg(VirtReg); in dumpState()
1206 LiveRegMap::const_iterator I = findLiveVirtReg(VirtReg); in dumpState()
1224 Register VirtReg = LR.VirtReg; in dumpState() local
1225 assert(VirtReg.isVirtual() && "Bad map key"); in dumpState()
1230 assert(RegUnitStates[Unit] == VirtReg && "inverse map valid"); in dumpState()