Lines Matching refs:SU
211 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
212 return Topo.IsReachable(SU, TargetSU); in IsReachable()
217 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
218 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
224 void AddPredQueued(SUnit *SU, const SDep &D) { in AddPredQueued() argument
225 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
226 SU->addPred(D); in AddPredQueued()
232 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
233 Topo.AddPred(SU, D.getSUnit()); in AddPred()
234 SU->addPred(D); in AddPred()
240 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
241 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
242 SU->removePred(D); in RemovePred()
246 bool isReady(SUnit *SU) { in isReady() argument
248 AvailableQueue->isReady(SU); in isReady()
251 void ReleasePred(SUnit *SU, const SDep *PredEdge);
252 void ReleasePredecessors(SUnit *SU);
255 void AdvancePastStalls(SUnit *SU);
256 void EmitNode(SUnit *SU);
400 void ScheduleDAGRRList::ReleasePred(SUnit *SU, const SDep *PredEdge) { in ReleasePred() argument
416 PredSU->setHeightToAtLeast(SU->getHeight() + PredEdge->getLatency()); in ReleasePred()
556 void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { in ReleasePredecessors() argument
558 for (SDep &Pred : SU->Preds) { in ReleasePredecessors()
559 ReleasePred(SU, &Pred); in ReleasePredecessors()
566 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
571 LiveRegGens[Pred.getReg()] = SU; in ReleasePredecessors()
581 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) in ReleasePredecessors()
590 CallSeqEndForStart[Def] = SU; in ReleasePredecessors()
594 LiveRegGens[CallResource] = SU; in ReleasePredecessors()
653 void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) { in AdvancePastStalls() argument
664 unsigned ReadyCycle = SU->getHeight(); in AdvancePastStalls()
675 if (SU->isCall) in AdvancePastStalls()
683 HazardRec->getHazardType(SU, -Stalls); in AdvancePastStalls()
695 void ScheduleDAGRRList::EmitNode(SUnit *SU) { in EmitNode() argument
700 if (!SU->getNode()) in EmitNode()
703 switch (SU->getNode()->getOpcode()) { in EmitNode()
705 assert(SU->getNode()->isMachineOpcode() && in EmitNode()
724 if (SU->isCall) { in EmitNode()
730 HazardRec->EmitInstruction(SU); in EmitNode()
733 static void resetVRegCycle(SUnit *SU);
738 void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) { in ScheduleNodeBottomUp() argument
740 LLVM_DEBUG(dumpNode(*SU)); in ScheduleNodeBottomUp()
743 if (CurCycle < SU->getHeight()) in ScheduleNodeBottomUp()
744 LLVM_DEBUG(dbgs() << " Height [" << SU->getHeight() in ScheduleNodeBottomUp()
752 SU->setHeightToAtLeast(CurCycle); in ScheduleNodeBottomUp()
755 EmitNode(SU); in ScheduleNodeBottomUp()
757 Sequence.push_back(SU); in ScheduleNodeBottomUp()
759 AvailableQueue->scheduledNode(SU); in ScheduleNodeBottomUp()
769 ReleasePredecessors(SU); in ScheduleNodeBottomUp()
772 for (SDep &Succ : SU->Succs) { in ScheduleNodeBottomUp()
774 if (Succ.isAssignedRegDep() && LiveRegDefs[Succ.getReg()] == SU) { in ScheduleNodeBottomUp()
785 if (LiveRegDefs[CallResource] == SU) in ScheduleNodeBottomUp()
786 for (const SDNode *SUNode = SU->getNode(); SUNode; in ScheduleNodeBottomUp()
798 resetVRegCycle(SU); in ScheduleNodeBottomUp()
800 SU->isScheduled = true; in ScheduleNodeBottomUp()
811 if (SU->getNode() && SU->getNode()->isMachineOpcode()) in ScheduleNodeBottomUp()
837 void ScheduleDAGRRList::UnscheduleNodeBottomUp(SUnit *SU) { in UnscheduleNodeBottomUp() argument
838 LLVM_DEBUG(dbgs() << "*** Unscheduling [" << SU->getHeight() << "]: "); in UnscheduleNodeBottomUp()
839 LLVM_DEBUG(dumpNode(*SU)); in UnscheduleNodeBottomUp()
841 for (SDep &Pred : SU->Preds) { in UnscheduleNodeBottomUp()
843 if (Pred.isAssignedRegDep() && SU == LiveRegGens[Pred.getReg()]){ in UnscheduleNodeBottomUp()
857 for (const SDNode *SUNode = SU->getNode(); SUNode; in UnscheduleNodeBottomUp()
861 SUnit *SeqEnd = CallSeqEndForStart[SU]; in UnscheduleNodeBottomUp()
866 LiveRegDefs[CallResource] = SU; in UnscheduleNodeBottomUp()
873 if (LiveRegGens[CallResource] == SU) in UnscheduleNodeBottomUp()
874 for (const SDNode *SUNode = SU->getNode(); SUNode; in UnscheduleNodeBottomUp()
888 for (auto &Succ : SU->Succs) { in UnscheduleNodeBottomUp()
895 LiveRegDefs[Reg] = SU; in UnscheduleNodeBottomUp()
902 for (auto &Succ2 : SU->Succs) { in UnscheduleNodeBottomUp()
910 if (SU->getHeight() < MinAvailableCycle) in UnscheduleNodeBottomUp()
911 MinAvailableCycle = SU->getHeight(); in UnscheduleNodeBottomUp()
913 SU->setHeightDirty(); in UnscheduleNodeBottomUp()
914 SU->isScheduled = false; in UnscheduleNodeBottomUp()
915 SU->isAvailable = true; in UnscheduleNodeBottomUp()
918 SU->isPending = true; in UnscheduleNodeBottomUp()
919 PendingQueue.push_back(SU); in UnscheduleNodeBottomUp()
922 AvailableQueue->push(SU); in UnscheduleNodeBottomUp()
924 AvailableQueue->unscheduledNode(SU); in UnscheduleNodeBottomUp()
940 SUnit *SU = *I; in RestoreHazardCheckerBottomUp() local
941 for (; SU->getHeight() > HazardCycle; ++HazardCycle) { in RestoreHazardCheckerBottomUp()
944 EmitNode(SU); in RestoreHazardCheckerBottomUp()
950 void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { in BacktrackBottomUp() argument
963 assert(!SU->isSucc(OldSU) && "Something is wrong!"); in BacktrackBottomUp()
972 static bool isOperandOf(const SUnit *SU, SDNode *N) { in isOperandOf() argument
973 for (const SDNode *SUNode = SU->getNode(); SUNode; in isOperandOf()
982 SUnit *ScheduleDAGRRList::TryUnfoldSU(SUnit *SU) { in TryUnfoldSU() argument
983 SDNode *N = SU->getNode(); in TryUnfoldSU()
994 unsigned OldNumVals = SU->getNode()->getNumValues(); in TryUnfoldSU()
1006 return SU; in TryUnfoldSU()
1024 return SU; in TryUnfoldSU()
1045 LLVM_DEBUG(dbgs() << "Unfolding SU #" << SU->NodeNum << "\n"); in TryUnfoldSU()
1049 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), i), SDValue(N, i)); in TryUnfoldSU()
1050 DAG->ReplaceAllUsesOfValueWith(SDValue(SU->getNode(), OldNumVals - 1), in TryUnfoldSU()
1059 for (SDep &Pred : SU->Preds) { in TryUnfoldSU()
1067 for (SDep &Succ : SU->Succs) { in TryUnfoldSU()
1076 RemovePred(SU, Pred); in TryUnfoldSU()
1081 RemovePred(SU, Pred); in TryUnfoldSU()
1086 RemovePred(SU, Pred); in TryUnfoldSU()
1091 D.setSUnit(SU); in TryUnfoldSU()
1102 D.setSUnit(SU); in TryUnfoldSU()
1131 SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { in CopyAndMoveSuccessors() argument
1132 SDNode *N = SU->getNode(); in CopyAndMoveSuccessors()
1137 LLVM_DEBUG(dumpNode(*SU)); in CopyAndMoveSuccessors()
1170 SUnit *UnfoldSU = TryUnfoldSU(SU); in CopyAndMoveSuccessors()
1173 SU = UnfoldSU; in CopyAndMoveSuccessors()
1174 N = SU->getNode(); in CopyAndMoveSuccessors()
1176 if (SU->NumSuccsLeft == 0) in CopyAndMoveSuccessors()
1177 return SU; in CopyAndMoveSuccessors()
1180 LLVM_DEBUG(dbgs() << " Duplicating SU #" << SU->NodeNum << "\n"); in CopyAndMoveSuccessors()
1181 NewSU = CreateClone(SU); in CopyAndMoveSuccessors()
1184 for (SDep &Pred : SU->Preds) in CopyAndMoveSuccessors()
1190 AddPredQueued(NewSU, SDep(SU, SDep::Artificial)); in CopyAndMoveSuccessors()
1195 for (SDep &Succ : SU->Succs) { in CopyAndMoveSuccessors()
1203 D.setSUnit(SU); in CopyAndMoveSuccessors()
1210 AvailableQueue->updateNode(SU); in CopyAndMoveSuccessors()
1219 void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, in InsertCopiesAndMoveSuccs() argument
1234 for (SDep &Succ : SU->Succs) { in InsertCopiesAndMoveSuccs()
1254 SDep FromDep(SU, SDep::Data, Reg); in InsertCopiesAndMoveSuccs()
1255 FromDep.setLatency(SU->Latency); in InsertCopiesAndMoveSuccs()
1261 AvailableQueue->updateNode(SU); in InsertCopiesAndMoveSuccs()
1295 static void CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, in CheckForLiveRegDef() argument
1306 if (LiveRegDefs[*AliasI] == SU) continue; in CheckForLiveRegDef()
1321 static void CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, in CheckForLiveRegDefMasked() argument
1328 if (LiveRegDefs[i] == SU) continue; in CheckForLiveRegDefMasked()
1348 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) { in DelayForLiveRegsBottomUp() argument
1357 for (SDep &Pred : SU->Preds) { in DelayForLiveRegsBottomUp()
1358 if (Pred.isAssignedRegDep() && LiveRegDefs[Pred.getReg()] != SU) in DelayForLiveRegsBottomUp()
1363 for (SDNode *Node = SU->getNode(); Node; Node = Node->getGluedNode()) { in DelayForLiveRegsBottomUp()
1383 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); in DelayForLiveRegsBottomUp()
1395 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI, in DelayForLiveRegsBottomUp()
1418 CheckForLiveRegDefMasked(SU, RegMask, in DelayForLiveRegsBottomUp()
1432 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); in DelayForLiveRegsBottomUp()
1436 CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI); in DelayForLiveRegsBottomUp()
1445 SUnit *SU = Interferences[i-1]; in releaseInterferences() local
1446 LRegsMapT::iterator LRegsPos = LRegsMap.find(SU); in releaseInterferences()
1452 SU->isPending = false; in releaseInterferences()
1456 if (SU->isAvailable && !SU->NodeQueueId) { in releaseInterferences()
1457 LLVM_DEBUG(dbgs() << " Repushing SU #" << SU->NodeNum << '\n'); in releaseInterferences()
1458 AvailableQueue->push(SU); in releaseInterferences()
1625 SUnit *SU = PickNodeToScheduleBottomUp(); in ListScheduleBottomUp() local
1627 AdvancePastStalls(SU); in ListScheduleBottomUp()
1629 ScheduleNodeBottomUp(SU); in ListScheduleBottomUp()
1652 bool isReady(SUnit* SU, unsigned CurCycle) const { return true; } in isReady()
1710 bool isReady(SUnit *SU, unsigned CurCycle) const;
1727 bool isReady(SUnit *SU, unsigned CurCycle) const;
1789 void addNode(const SUnit *SU) override;
1791 void updateNode(const SUnit *SU) override;
1799 unsigned getNodePriority(const SUnit *SU) const;
1801 unsigned getNodeOrdering(const SUnit *SU) const { in getNodeOrdering()
1802 if (!SU->getNode()) return 0; in getNodeOrdering()
1804 return SU->getNode()->getIROrder(); in getNodeOrdering()
1815 void remove(SUnit *SU) override { in remove() argument
1817 assert(SU->NodeQueueId != 0 && "Not in queue!"); in remove()
1818 std::vector<SUnit *>::iterator I = llvm::find(Queue, SU); in remove()
1822 SU->NodeQueueId = 0; in remove()
1829 bool HighRegPressure(const SUnit *SU) const;
1831 bool MayReduceRegPressure(SUnit *SU) const;
1833 int RegPressureDiff(SUnit *SU, unsigned &LiveUses) const;
1835 void scheduledNode(SUnit *SU) override;
1837 void unscheduledNode(SUnit *SU) override;
1840 bool canClobber(const SUnit *SU, const SUnit *Op);
1916 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); in dump() local
1917 dbgs() << "Height " << SU->getHeight() << ": "; in dump()
1918 DAG->dumpNode(*SU); in dump()
1952 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) { in CalcNodeSethiUllmanNumber() argument
1953 if (SUNumbers[SU->NodeNum] != 0) in CalcNodeSethiUllmanNumber()
1954 return SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
1958 WorkState(const SUnit *SU) : SU(SU) {} in CalcNodeSethiUllmanNumber()
1959 const SUnit *SU; in CalcNodeSethiUllmanNumber() member
1964 WorkList.push_back(SU); in CalcNodeSethiUllmanNumber()
1967 auto *TempSU = Temp.SU; in CalcNodeSethiUllmanNumber()
1978 assert(It.SU != PredSU && "Trying to push an element twice?"); in CalcNodeSethiUllmanNumber()
2013 assert(SUNumbers[SU->NodeNum] > 0 && "SethiUllman should never be zero!"); in CalcNodeSethiUllmanNumber()
2014 return SUNumbers[SU->NodeNum]; in CalcNodeSethiUllmanNumber()
2022 for (const SUnit &SU : *SUnits) in CalculateSethiUllmanNumbers()
2023 CalcNodeSethiUllmanNumber(&SU, SethiUllmanNumbers); in CalculateSethiUllmanNumbers()
2026 void RegReductionPQBase::addNode(const SUnit *SU) { in addNode() argument
2030 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); in addNode()
2033 void RegReductionPQBase::updateNode(const SUnit *SU) { in updateNode() argument
2034 SethiUllmanNumbers[SU->NodeNum] = 0; in updateNode()
2035 CalcNodeSethiUllmanNumber(SU, SethiUllmanNumbers); in updateNode()
2040 unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const { in getNodePriority()
2041 assert(SU->NodeNum < SethiUllmanNumbers.size()); in getNodePriority()
2042 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; in getNodePriority()
2053 if (SU->NumSuccs == 0 && SU->NumPreds != 0) in getNodePriority()
2060 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in getNodePriority()
2065 return SethiUllmanNumbers[SU->NodeNum]; in getNodePriority()
2067 unsigned Priority = SethiUllmanNumbers[SU->NodeNum]; in getNodePriority()
2068 if (SU->isCallOp) { in getNodePriority()
2070 int NP = (int)Priority - SU->getNode()->getNumValues(); in getNodePriority()
2093 bool RegReductionPQBase::HighRegPressure(const SUnit *SU) const { in HighRegPressure()
2097 for (const SDep &Pred : SU->Preds) { in HighRegPressure()
2118 bool RegReductionPQBase::MayReduceRegPressure(SUnit *SU) const { in MayReduceRegPressure()
2119 const SDNode *N = SU->getNode(); in MayReduceRegPressure()
2121 if (!N->isMachineOpcode() || !SU->NumSuccs) in MayReduceRegPressure()
2143 int RegReductionPQBase::RegPressureDiff(SUnit *SU, unsigned &LiveUses) const { in RegPressureDiff() argument
2146 for (const SDep &Pred : SU->Preds) { in RegPressureDiff()
2165 const SDNode *N = SU->getNode(); in RegPressureDiff()
2167 if (!N || !N->isMachineOpcode() || !SU->NumSuccs) in RegPressureDiff()
2182 void RegReductionPQBase::scheduledNode(SUnit *SU) { in scheduledNode() argument
2186 if (!SU->getNode()) in scheduledNode()
2189 for (const SDep &Pred : SU->Preds) { in scheduledNode()
2230 int SkipRegDefs = (int)SU->NumRegDefsLeft; in scheduledNode()
2231 for (ScheduleDAGSDNodes::RegDefIter RegDefPos(SU, scheduleDAG); in scheduledNode()
2240 LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum in scheduledNode()
2251 void RegReductionPQBase::unscheduledNode(SUnit *SU) { in unscheduledNode() argument
2255 const SDNode *N = SU->getNode(); in unscheduledNode()
2271 for (const SDep &Pred : SU->Preds) { in unscheduledNode()
2324 if (SU->NumSuccs && N->isMachineOpcode()) { in unscheduledNode()
2346 static unsigned closestSucc(const SUnit *SU) { in closestSucc() argument
2348 for (const SDep &Succ : SU->Succs) { in closestSucc()
2364 static unsigned calcMaxScratches(const SUnit *SU) { in calcMaxScratches() argument
2366 for (const SDep &Pred : SU->Preds) { in calcMaxScratches()
2375 static bool hasOnlyLiveInOpers(const SUnit *SU) { in hasOnlyLiveInOpers() argument
2377 for (const SDep &Pred : SU->Preds) { in hasOnlyLiveInOpers()
2397 static bool hasOnlyLiveOutUses(const SUnit *SU) { in hasOnlyLiveOutUses() argument
2399 for (const SDep &Succ : SU->Succs) { in hasOnlyLiveOutUses()
2425 static void initVRegCycle(SUnit *SU) { in initVRegCycle() argument
2429 if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU)) in initVRegCycle()
2432 LLVM_DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n"); in initVRegCycle()
2434 SU->isVRegCycle = true; in initVRegCycle()
2436 for (const SDep &Pred : SU->Preds) { in initVRegCycle()
2444 static void resetVRegCycle(SUnit *SU) { in resetVRegCycle() argument
2445 if (!SU->isVRegCycle) in resetVRegCycle()
2448 for (const SDep &Pred : SU->Preds) { in resetVRegCycle()
2461 static bool hasVRegCycleUse(const SUnit *SU) { in hasVRegCycleUse() argument
2463 if (SU->isVRegCycle) in hasVRegCycleUse()
2466 for (const SDep &Pred : SU->Preds) { in hasVRegCycleUse()
2470 LLVM_DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n"); in hasVRegCycleUse()
2480 static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) { in BUHasStall() argument
2482 if (SPQ->getHazardRec()->getHazardType(SU, 0) in BUHasStall()
2672 bool hybrid_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady() argument
2675 if (SPQ->MayReduceRegPressure(SU)) return true; in isReady()
2677 if (SU->getHeight() > (CurCycle + ReadyDelay)) return false; in isReady()
2679 if (SPQ->getHazardRec()->getHazardType(SU, -ReadyDelay) in isReady()
2719 bool ilp_ls_rr_sort::isReady(SUnit *SU, unsigned CurCycle) const { in isReady() argument
2720 if (SU->getHeight() > CurCycle) return false; in isReady()
2722 if (SPQ->getHazardRec()->getHazardType(SU, 0) in isReady()
2729 static bool canEnableCoalescing(SUnit *SU) { in canEnableCoalescing() argument
2730 unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0; in canEnableCoalescing()
2743 if (SU->NumPreds == 0 && SU->NumSuccs != 0) in canEnableCoalescing()
2827 for (SUnit &SU : sunits) in initNodes()
2828 initVRegCycle(&SU); in initNodes()
2835 bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { in canClobber() argument
2836 if (SU->isTwoAddress) { in canClobber()
2837 unsigned Opc = SU->getNode()->getMachineOpcode(); in canClobber()
2843 SDNode *DU = SU->getNode()->getOperand(i).getNode(); in canClobber()
2856 static bool canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, in canClobberReachingPhysRegUse() argument
2861 TII->get(SU->getNode()->getMachineOpcode()).implicit_defs(); in canClobberReachingPhysRegUse()
2862 const uint32_t *RegMask = getNodeRegMask(SU->getNode()); in canClobberReachingPhysRegUse()
2866 for (const SDep &Succ : SU->Succs) { in canClobberReachingPhysRegUse()
2892 static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, in canClobberPhysRegDefs() argument
2899 for (const SDNode *SUNode = SU->getNode(); SUNode; in canClobberPhysRegDefs()
2958 for (SUnit &SU : *SUnits) { in PrescheduleNodesWithMultipleUses()
2962 if (SU.NumSuccs != 0) in PrescheduleNodesWithMultipleUses()
2965 if (SU.NumPreds != 1) in PrescheduleNodesWithMultipleUses()
2969 if (SDNode *N = SU.getNode()) in PrescheduleNodesWithMultipleUses()
2975 for (const SDep &Pred : SU.Preds) in PrescheduleNodesWithMultipleUses()
2999 for (const SDep &Pred : SU.Preds) in PrescheduleNodesWithMultipleUses()
3015 if (SDNode *N = SU.getNode()) in PrescheduleNodesWithMultipleUses()
3023 if (PredSuccSU == &SU) continue; in PrescheduleNodesWithMultipleUses()
3029 if (SU.hasPhysRegClobbers && PredSuccSU->hasPhysRegDefs) in PrescheduleNodesWithMultipleUses()
3030 if (canClobberPhysRegDefs(PredSuccSU, &SU, TII, TRI)) in PrescheduleNodesWithMultipleUses()
3033 if (scheduleDAG->IsReachable(&SU, PredSuccSU)) in PrescheduleNodesWithMultipleUses()
3040 dbgs() << " Prescheduling SU #" << SU.NodeNum << " next to PredSU #" in PrescheduleNodesWithMultipleUses()
3047 if (SuccSU != &SU) { in PrescheduleNodesWithMultipleUses()
3050 scheduleDAG->AddPredQueued(&SU, Edge); in PrescheduleNodesWithMultipleUses()
3051 Edge.setSUnit(&SU); in PrescheduleNodesWithMultipleUses()
3068 for (SUnit &SU : *SUnits) { in AddPseudoTwoAddrDeps()
3069 if (!SU.isTwoAddress) in AddPseudoTwoAddrDeps()
3072 SDNode *Node = SU.getNode(); in AddPseudoTwoAddrDeps()
3073 if (!Node || !Node->isMachineOpcode() || SU.getNode()->getGluedNode()) in AddPseudoTwoAddrDeps()
3076 bool isLiveOut = hasOnlyLiveOutUses(&SU); in AddPseudoTwoAddrDeps()
3084 SDNode *DU = SU.getNode()->getOperand(j).getNode(); in AddPseudoTwoAddrDeps()
3094 if (SuccSU == &SU) in AddPseudoTwoAddrDeps()
3098 if (SuccSU->getHeight() < SU.getHeight() && in AddPseudoTwoAddrDeps()
3099 (SU.getHeight() - SuccSU->getHeight()) > 1) in AddPseudoTwoAddrDeps()
3115 if (SuccSU->hasPhysRegDefs && SU.hasPhysRegClobbers) { in AddPseudoTwoAddrDeps()
3116 if (canClobberPhysRegDefs(SuccSU, &SU, TII, TRI)) in AddPseudoTwoAddrDeps()
3126 if (!canClobberReachingPhysRegUse(SuccSU, &SU, scheduleDAG, TII, TRI) && in AddPseudoTwoAddrDeps()
3129 (!SU.isCommutable && SuccSU->isCommutable)) && in AddPseudoTwoAddrDeps()
3130 !scheduleDAG->IsReachable(SuccSU, &SU)) { in AddPseudoTwoAddrDeps()
3133 << SU.NodeNum << " to SU #" << SuccSU->NodeNum << "\n"); in AddPseudoTwoAddrDeps()
3134 scheduleDAG->AddPredQueued(&SU, SDep(SuccSU, SDep::Artificial)); in AddPseudoTwoAddrDeps()