158 ArrayRef<MCPhysReg> llvm::AArch64::getGPRArgRegs() { return GPRArgRegs; }  in getGPRArgRegs()
160 ArrayRef<MCPhysReg> llvm::AArch64::getFPRArgRegs() { return FPRArgRegs; }  in getFPRArgRegs()
11322 static bool isSingletonEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {  in isSingletonEXTMask()
11405 static bool isWideDUPMask(ArrayRef<int> M, EVT VT, unsigned BlockSize,  in isWideDUPMask()
11478 static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,  in isEXTMask()
11520 static bool isREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {  in isREVMask()
11545 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIPMask()
11561 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZPMask()
11574 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRNMask()
11590 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIP_v_undef_Mask()
11609 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZP_v_undef_Mask()
11628 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRN_v_undef_Mask()
11641 static bool isINSMask(ArrayRef<int> M, int NumInputElements,  in isINSMask()
11680 static bool isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) {  in isConcatMask()
11705   ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();  in tryFormConcatFromShuffle()
11894 static SDValue GenerateTBL(SDValue Op, ArrayRef<int> ShuffleMask,  in GenerateTBL()
11943         DAG.getBuildVector(IndexVT, DL, ArrayRef(TBLMask.data(), IndexLen)));  in GenerateTBL()
11950           DAG.getBuildVector(IndexVT, DL, ArrayRef(TBLMask.data(), IndexLen)));  in GenerateTBL()
11962           DAG.getBuildVector(IndexVT, DL, ArrayRef(TBLMask.data(), IndexLen)));  in GenerateTBL()
12043 static bool isWideTypeMask(ArrayRef<int> M, EVT VT,  in isWideTypeMask()
12095   ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask();  in tryWidenMaskForShuffle()
12122                                                ArrayRef<int> ShuffleMask,  in tryToConvertShuffleOfTbl2ToTbl4()
12200   ArrayRef<int> ShuffleMask = SVN->getMask();  in LowerVECTOR_SHUFFLE()
13746 bool AArch64TargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {  in isShuffleMaskLegal()
13775 bool AArch64TargetLowering::isVectorClearMaskLegal(ArrayRef<int> M,  in isVectorClearMaskLegal()
14866   ArrayRef<int> M1, M2;  in areExtractShuffleVectors()
15651     LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,  in lowerInterleavedLoad()
15652     ArrayRef<unsigned> Indices, unsigned Factor) const {  in lowerInterleavedLoad()
16356 ArrayRef<MCPhysReg> AArch64TargetLowering::getRoundingControlRegisters() const {  in getRoundingControlRegisters()
21866     SDVTList SDTys = DAG.getVTList(ArrayRef(Tys, NumResultVecs + 2));  in performNEONPostLDSTCombine()
22795         is_contained(ArrayRef({MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16,  in performVSelectCombine()
24449   ArrayRef<int> Mask = Shuf->getMask();  in ReplaceAddWithADDP()
26548                                          ArrayRef<int> ShuffleMask, EVT VT,  in GenerateFixedLengthSVETBL()
26601       DAG.getBuildVector(MaskType, DL, ArrayRef(TBLMask.data(), IndexLen));  in GenerateFixedLengthSVETBL()