Lines Matching refs:bits

16   field bits<16> Inst;
21   field bits<16> SoftFail = 0;
25 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
28   bits<5> rs1;
29   bits<5> rs2;
38 // is responsible for setting the appropriate bits in the Inst field.
39 // The bits Inst{6-2} must be set for each instruction.
40 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
43   bits<10> imm;
44   bits<5> rd;
53 // is responsible for setting the appropriate bits in the Inst field.
54 // The bits Inst{12-7} must be set for each instruction.
55 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
58   bits<10> imm;
59   bits<5> rs2;
60   bits<5> rs1;
67 class RVInst16CIW<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
70   bits<10> imm;
71   bits<3> rd;
79 // is responsible for setting the appropriate bits in the Inst field.
80 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
81 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
84   bits<3> rd;
85   bits<3> rs1;
94 // is responsible for setting the appropriate bits in the Inst field.
95 // The bits Inst{12-10} and Inst{6-5} must be set for each instruction.
96 class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
99   bits<3> rs2;
100   bits<3> rs1;
108 class RVInst16CA<bits<6> funct6, bits<2> funct2, bits<2> opcode, dag outs,
111   bits<3> rs2;
112   bits<3> rs1;
121 class RVInst16CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
124   bits<9> imm;
125   bits<3> rs1;
132 class RVInst16CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
135   bits<11> offset;
149 class RVInst16CU<bits<6> funct6, bits<5> funct5, bits<2> opcode, dag outs,
152   bits<3> rd;
161 // is responsible for setting the appropriate bits in the Inst field.
162 // The bits Inst{6-5} must be set for each instruction.
163 class RVInst16CLB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
166   bits<3> rd;
167   bits<3> rs1;
176 // is responsible for setting the appropriate bits in the Inst field.
177 // The bits Inst{5} must be set for each instruction.
178 class RVInst16CLH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
181   bits<3> rd;
182   bits<3> rs1;
192 // is responsible for setting the appropriate bits in the Inst field.
193 // The bits Inst{6-5} must be set for each instruction.
194 class RVInst16CSB<bits<6> funct6, bits<2> opcode, dag outs, dag ins,
197   bits<3> rs2;
198   bits<3> rs1;
207 // is responsible for setting the appropriate bits in the Inst field.
208 // The bits Inst{5} must be set for each instruction.
209 class RVInst16CSH<bits<6> funct6, bit funct1, bits<2> opcode, dag outs,
212   bits<3> rs2;
213   bits<3> rs1;
228   bits<2> opcode;
229   bits<4> funct4;
231   bits<5> rs2;
232   bits<5> rd;
244   bits<2> opcode;
245   bits<3> funct3;
247   bits<6> imm6;
248   bits<5> rd;
261   bits<2> opcode;
262   bits<3> funct3;
264   bits<8> imm8;
265   bits<3> rd;
277   bits<2> opcode;
278   bits<3> funct3;
280   bits<6> imm6;
281   bits<5> rs2;
293   bits<2> opcode;
294   bits<3> funct3;
296   bits<5> imm5;
297   bits<3> rd;
298   bits<3> rs1;
312   bits<2> opcode;
313   bits<3> funct3;
315   bits<5> imm5;
316   bits<3> rs2;
317   bits<3> rs1;
331   bits<2> opcode;
332   bits<6> funct6;
333   bits<2> funct2;
335   bits<3> rd;
336   bits<3> rs2;
349   bits<2> opcode;
350   bits<3> funct3;
352   bits<8> imm8;
353   bits<3> rs1;
369   bits<2> opcode;
370   bits<3> funct3;
372   bits<11> imm11;