Lines Matching refs:RC
148 for (const auto &RC : RegisterClasses) in runEnums() local
149 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; in runEnums()
218 for (const auto &RC : RegBank.getRegClasses()) { in EmitRegUnitPressure() local
219 const CodeGenRegister::Vec &Regs = RC.getMembers(); in EmitRegUnitPressure()
220 OS << " {" << RC.getWeight(RegBank) << ", "; in EmitRegUnitPressure()
221 if (Regs.empty() || RC.Artificial) in EmitRegUnitPressure()
225 RC.buildRegUnitSet(RegBank, RegUnits); in EmitRegUnitPressure()
228 OS << "}, \t// " << RC.getName() << "\n"; in EmitRegUnitPressure()
1023 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1024 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1027 const std::string &Name = RC.getName(); in runMCDesc()
1059 for (const auto &RC : RegisterClasses) { in runMCDesc() local
1060 ArrayRef<Record *> Order = RC.getOrder(); in runMCDesc()
1061 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); in runMCDesc()
1062 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; in runMCDesc()
1064 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); in runMCDesc()
1066 if (RC.RSI.isSimple()) in runMCDesc()
1067 RegSize = RC.RSI.getSimple().RegSize; in runMCDesc()
1069 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1070 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", " in runMCDesc()
1071 << RegSize << ", " << RC.CopyCost << ", " in runMCDesc()
1072 << (RC.Allocatable ? "true" : "false") << " },\n"; in runMCDesc()
1177 if (llvm::any_of(RegisterClasses, [](const auto &RC) { return RC.getBaseClassOrder(); })) { in runTargetHeader() argument
1187 for (const auto &RC : RegisterClasses) { in runTargetHeader() local
1188 const std::string &Name = RC.getName(); in runTargetHeader()
1224 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1225 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1227 if (RC.Allocatable) in runTargetDesc()
1237 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1239 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1282 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1283 assert(RC.EnumValue == EV && "Unexpected order of register classes"); in runTargetDesc()
1286 const RegSizeInfo &RI = RC.RSI.get(M); in runTargetDesc()
1290 for (const ValueTypeByHwMode &VVT : RC.VTs) in runTargetDesc()
1294 << RC.getName() << '\n'; in runTargetDesc()
1327 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1328 OS << "static const uint32_t " << RC.getName() in runTargetDesc()
1330 printBitVectorAsHex(OS, RC.getSubClasses(), 32); in runTargetDesc()
1334 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; in runTargetDesc()
1337 RC.getSuperRegClasses(&Idx, MaskBV); in runTargetDesc()
1355 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1356 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); in runTargetDesc()
1363 << RC.getName() << "Superclasses[] = {\n"; in runTargetDesc()
1370 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1371 if (!RC.AltOrderSelect.empty()) { in runTargetDesc()
1372 OS << "\nstatic inline unsigned " << RC.getName() in runTargetDesc()
1374 << RC.AltOrderSelect << "}\n\n" in runTargetDesc()
1375 << "static ArrayRef<MCPhysReg> " << RC.getName() in runTargetDesc()
1377 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { in runTargetDesc()
1378 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1387 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" in runTargetDesc()
1390 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) in runTargetDesc()
1391 if (RC.getOrder(oi).empty()) in runTargetDesc()
1395 OS << ")\n };\n const unsigned Select = " << RC.getName() in runTargetDesc()
1396 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() in runTargetDesc()
1405 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1406 OS << " extern const TargetRegisterClass " << RC.getName() in runTargetDesc()
1408 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " in runTargetDesc()
1409 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " in runTargetDesc()
1410 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; in runTargetDesc()
1411 printMask(OS, RC.LaneMask); in runTargetDesc()
1412 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " in runTargetDesc()
1413 << (RC.GlobalPriority ? "true" : "false") << ",\n " in runTargetDesc()
1414 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " in runTargetDesc()
1415 << (RC.HasDisjunctSubRegs ? "true" : "false") in runTargetDesc()
1417 << (RC.CoveredBySubRegs ? "true" : "false") in runTargetDesc()
1419 if (RC.getSuperClasses().empty()) in runTargetDesc()
1422 OS << RC.getName() << "Superclasses,\n "; in runTargetDesc()
1423 if (RC.AltOrderSelect.empty()) in runTargetDesc()
1426 OS << RC.getName() << "GetRawAllocationOrder\n"; in runTargetDesc()
1435 for (const auto &RC : RegisterClasses) in runTargetDesc() local
1436 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; in runTargetDesc()
1513 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1514 OS << " {\t// " << RC.getName() << "\n"; in runTargetDesc()
1516 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) in runTargetDesc()
1546 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1547 OS << " {\t// " << RC.getName() << '\n'; in runTargetDesc()
1550 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx); in runTargetDesc()
1559 << RC.getName() << ':' << Idx.getName(); in runTargetDesc()
1584 for (const auto &RC : RegisterClasses) { in runTargetDesc() local
1585 if (RC.getBaseClassOrder()) in runTargetDesc()
1586 BaseClasses.push_back(&RC); in runTargetDesc()
1611 for (const CodeGenRegisterClass *RC : BaseClasses) { in runTargetDesc() local
1612 if (is_contained(RC->getMembers(), &Reg)) { in runTargetDesc()
1613 BaseRC = RC; in runTargetDesc()
1739 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1740 OS << " " << RC->getQualifiedName() in runTargetDesc()
1753 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1754 OS << " " << RC->getQualifiedName() in runTargetDesc()
1767 for (const CodeGenRegisterClass *RC : Category.getClasses()) in runTargetDesc() local
1768 OS << " " << RC->getQualifiedName() in runTargetDesc()
1835 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { in debugDump() local
1836 OS << "RegisterClass " << RC.getName() << ":\n"; in debugDump()
1839 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; in debugDump()
1842 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; in debugDump()
1843 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; in debugDump()
1844 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; in debugDump()
1845 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1846 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; in debugDump()
1847 OS << "\tAllocatable: " << RC.Allocatable << '\n'; in debugDump()
1848 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; in debugDump()
1850 for (const CodeGenRegister *R : RC.getMembers()) { in debugDump()
1855 const BitVector &SubClasses = RC.getSubClasses(); in debugDump()
1863 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { in debugDump()