162 	int reg;  in fpgamgr_state_get()  local
164 	reg = READ4(sc, FPGAMGR_STAT);  in fpgamgr_state_get()
165 	reg >>= STAT_MODE_SHIFT;  in fpgamgr_state_get()
166 	reg &= STAT_MODE_MASK;  in fpgamgr_state_get()
168 	return reg;  in fpgamgr_state_get()
197 	int reg;  in fpga_open()  local
218 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_open()
219 	reg &= ~(CTRL_CDRATIO_MASK << CTRL_CDRATIO_SHIFT);  in fpga_open()
220 	reg |= (mode->cdratio << CTRL_CDRATIO_SHIFT);  in fpga_open()
221 	reg &= ~(CTRL_CFGWDTH_MASK << CTRL_CFGWDTH_SHIFT);  in fpga_open()
222 	reg |= (mode->cfgwdth << CTRL_CFGWDTH_SHIFT);  in fpga_open()
223 	reg &= ~(CTRL_NCE);  in fpga_open()
224 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_open()
227 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_open()
228 	reg |= (CTRL_EN);  in fpga_open()
229 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_open()
232 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_open()
233 	reg |= (CTRL_NCONFIGPULL);  in fpga_open()
234 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_open()
243 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_open()
244 	reg &= ~(CTRL_NCONFIGPULL);  in fpga_open()
245 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_open()
256 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_open()
257 	reg |= (CTRL_AXICFGEN);  in fpga_open()
258 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_open()
297 	int reg;  in fpga_close()  local
301 	reg = READ4(sc, GPIO_EXT_PORTA);  in fpga_close()
302 	if ((reg & EXT_PORTA_CDP) == 0) {  in fpga_close()
308 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_close()
309 	reg &= ~(CTRL_AXICFGEN);  in fpga_close()
310 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_close()
324 	reg = READ4(sc, FPGAMGR_CTRL);  in fpga_close()
325 	reg &= ~(CTRL_EN);  in fpga_close()
326 	WRITE4(sc, FPGAMGR_CTRL, reg);  in fpga_close()