180 	u_int irq;  in gpio_pic_map_fdt()  local
200 	irq = daf->cells[0];  in gpio_pic_map_fdt()
201 	if (irq >= sc->gpio_npins) {  in gpio_pic_map_fdt()
202 		device_printf(sc->dev, "Invalid interrupt number %u\n", irq);  in gpio_pic_map_fdt()
226 	*irqp = irq;  in gpio_pic_map_fdt()
236 	u_int irq;  in gpio_pic_map_gpio()  local
238 	irq = dag->gpio_pin_num;  in gpio_pic_map_gpio()
239 	if (irq >= sc->gpio_npins) {  in gpio_pic_map_gpio()
240 		device_printf(sc->dev, "Invalid interrupt number %u\n", irq);  in gpio_pic_map_gpio()
257 	*irqp = irq;  in gpio_pic_map_gpio()
285 	u_int irq;  in gpio_pic_map_intr()  local
289 	error = gpio_pic_map(sc, data, &irq, NULL);  in gpio_pic_map_intr()
291 		*isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc;  in gpio_pic_map_intr()
323 	u_int icfg, irq, reg, shift, wrk;  in gpio_pic_setup_intr()  local
333 	error = gpio_pic_map(sc, data, &irq, &mode);  in gpio_pic_setup_intr()
336 	if (gi->gi_irq != irq)  in gpio_pic_setup_intr()
352 		SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq));  in gpio_pic_setup_intr()
354 		CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq));  in gpio_pic_setup_intr()
372 		if (irq < 16) {  in gpio_pic_setup_intr()
374 			shift = 2 * irq;  in gpio_pic_setup_intr()
377 			shift = 2 * (irq - 16);  in gpio_pic_setup_intr()
384 	WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq));  in gpio_pic_setup_intr()
385 	SET4(sc, IMX_GPIO_IMR_REG, (1u << irq));  in gpio_pic_setup_intr()
398 	u_int irq;  in gpio_pic_disable_intr()  local
401 	irq = ((struct gpio_irqsrc *)isrc)->gi_irq;  in gpio_pic_disable_intr()
404 	CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq));  in gpio_pic_disable_intr()
415 	u_int irq;  in gpio_pic_enable_intr()  local
418 	irq = ((struct gpio_irqsrc *)isrc)->gi_irq;  in gpio_pic_enable_intr()
421 	SET4(sc, IMX_GPIO_IMR_REG, (1U << irq));  in gpio_pic_enable_intr()
429 	u_int irq;  in gpio_pic_post_filter()  local
432 	irq = ((struct gpio_irqsrc *)isrc)->gi_irq;  in gpio_pic_post_filter()
436 	WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));  in gpio_pic_post_filter()
443 	u_int irq;  in gpio_pic_post_ithread()  local
446 	irq = ((struct gpio_irqsrc *)isrc)->gi_irq;  in gpio_pic_post_ithread()
450 	WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq));  in gpio_pic_post_ithread()
493 	uint32_t irq;  in gpio_pic_register_isrcs()  local
497 	for (irq = 0; irq < NGPIO; irq++) {  in gpio_pic_register_isrcs()
498 		sc->gpio_pic_irqsrc[irq].gi_irq = irq;  in gpio_pic_register_isrcs()
499 		sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM;  in gpio_pic_register_isrcs()
501 		error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc,  in gpio_pic_register_isrcs()
502 		    sc->dev, 0, "%s,%u", name, irq);  in gpio_pic_register_isrcs()
799 	int i, irq, unit;  in imx51_gpio_attach()  local
836 	for (irq = 0; irq < 2; irq++) {  in imx51_gpio_attach()
838 		if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK,  in imx51_gpio_attach()
839 		    gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) {  in imx51_gpio_attach()
876 	int irq;  in imx51_gpio_detach()  local
893 	for (irq = 0; irq < NUM_IRQRES; irq++) {  in imx51_gpio_detach()
894 		if (sc->gpio_ih[irq])  in imx51_gpio_detach()
895 			bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES],  in imx51_gpio_detach()
896 			    sc->gpio_ih[irq]);  in imx51_gpio_detach()