114 a37x0_spi_wait(struct a37x0_spi_softc *sc, int timeout, uint32_t reg,  in a37x0_spi_wait()  argument
120 		if ((A37X0_SPI_READ(sc, reg) & mask) == 0)  in a37x0_spi_wait()
147 	uint32_t reg;  in a37x0_spi_attach()  local
173 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);  in a37x0_spi_attach()
174 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);  in a37x0_spi_attach()
177 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);  in a37x0_spi_attach()
178 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_FIFO_FLUSH);  in a37x0_spi_attach()
188 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);  in a37x0_spi_attach()
189 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_SRST);  in a37x0_spi_attach()
192 	reg &= ~(A37X0_SPI_FIFO_MODE | A37X0_SPI_BYTE_LEN);  in a37x0_spi_attach()
193 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);  in a37x0_spi_attach()
197 	reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);  in a37x0_spi_attach()
198 	A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);  in a37x0_spi_attach()
284 	uint32_t psc, reg;  in a37x0_spi_set_clock()  local
291 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);  in a37x0_spi_set_clock()
292 	reg &= ~A37X0_SPI_PSC_MASK;  in a37x0_spi_set_clock()
293 	reg |= psc & A37X0_SPI_PSC_MASK;  in a37x0_spi_set_clock()
294 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);  in a37x0_spi_set_clock()
300 	uint32_t reg;  in a37x0_spi_set_pins()  local
303 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);  in a37x0_spi_set_pins()
304 	reg &= ~(A37X0_SPI_DATA_PIN_MASK << A37X0_SPI_DATA_PIN_SHIFT);  in a37x0_spi_set_pins()
305 	reg |= (npins / 2) << A37X0_SPI_DATA_PIN_SHIFT;  in a37x0_spi_set_pins()
306 	reg |= A37X0_SPI_INSTR_PIN | A37X0_SPI_ADDR_PIN;  in a37x0_spi_set_pins()
307 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);  in a37x0_spi_set_pins()
313 	uint32_t reg;  in a37x0_spi_set_mode()  local
315 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF);  in a37x0_spi_set_mode()
318 		reg &= ~(A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);  in a37x0_spi_set_mode()
321 		reg &= ~A37X0_SPI_CLK_POL;  in a37x0_spi_set_mode()
322 		reg |= A37X0_SPI_CLK_PHASE;  in a37x0_spi_set_mode()
325 		reg &= ~A37X0_SPI_CLK_PHASE;  in a37x0_spi_set_mode()
326 		reg |= A37X0_SPI_CLK_POL;  in a37x0_spi_set_mode()
329 		reg |= (A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL);  in a37x0_spi_set_mode()
332 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg);  in a37x0_spi_set_mode()
371 	uint32_t clock, cs, mode, reg;  in a37x0_spi_transfer()  local
427 	reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT);  in a37x0_spi_transfer()
428 	A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg);  in a37x0_spi_transfer()
438 			reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);  in a37x0_spi_transfer()
439 			if (reg & A37X0_SPI_XFER_DONE)  in a37x0_spi_transfer()
449 	reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL);  in a37x0_spi_transfer()
450 	A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK);  in a37x0_spi_transfer()