415 	uint32_t reg;  in pll_enable()  local
417 	RD4(sc, sc->base_reg, &reg);  in pll_enable()
419 		reg &= ~PLL_BASE_BYPASS;  in pll_enable()
420 	reg |= PLL_BASE_ENABLE;  in pll_enable()
421 	WR4(sc, sc->base_reg, reg);  in pll_enable()
428 	uint32_t reg;  in pll_disable()  local
430 	RD4(sc, sc->base_reg, &reg);  in pll_disable()
432 		reg |= PLL_BASE_BYPASS;  in pll_disable()
433 	reg &= ~PLL_BASE_ENABLE;  in pll_disable()
434 	WR4(sc, sc->base_reg, reg);  in pll_disable()
456 reg_to_pdiv(struct pll_sc *sc, uint32_t reg)  in reg_to_pdiv()  argument
462 		return (1 << reg);  in reg_to_pdiv()
465 		if (reg == tbl->value)  in reg_to_pdiv()
517 	uint32_t reg;  in is_locked()  local
521 		RD4(sc, sc->misc_reg, &reg);  in is_locked()
522 		reg &=  PLLRE_MISC_LOCK;  in is_locked()
526 		RD4(sc, sc->misc_reg, &reg);  in is_locked()
527 		reg &= PLLE_MISC_LOCK;  in is_locked()
531 		RD4(sc, sc->base_reg, &reg);  in is_locked()
532 		reg &= PLL_BASE_LOCK;  in is_locked()
535 	return (reg != 0);  in is_locked()
558 	uint32_t reg;  in plle_enable()  local
566 	RD4(sc, sc->base_reg, &reg);  in plle_enable()
567 	reg &= ~PLLE_BASE_LOCK_OVERRIDE;  in plle_enable()
568 	WR4(sc, sc->base_reg, reg);  in plle_enable()
570 	RD4(sc, PLLE_AUX, &reg);  in plle_enable()
571 	reg |= PLLE_AUX_ENABLE_SWCTL;  in plle_enable()
572 	reg &= ~PLLE_AUX_SEQ_ENABLE;  in plle_enable()
573 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
576 	RD4(sc, sc->misc_reg, &reg);  in plle_enable()
577 	reg |= PLLE_MISC_LOCK_ENABLE;  in plle_enable()
578 	reg |= PLLE_MISC_IDDQ_SWCTL;  in plle_enable()
579 	reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE;  in plle_enable()
580 	reg |= PLLE_MISC_PTS;  in plle_enable()
581 	reg |= PLLE_MISC_VREG_BG_CTRL_MASK;  in plle_enable()
582 	reg |= PLLE_MISC_VREG_CTRL_MASK;  in plle_enable()
583 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
586 	RD4(sc, PLLE_SS_CNTL, &reg);  in plle_enable()
587 	reg |= PLLE_SS_CNTL_DISABLE;  in plle_enable()
588 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
590 	RD4(sc, sc->base_reg, &reg);  in plle_enable()
591 	reg = set_divisors(sc, reg, pll_m, pll_n, pll_p);  in plle_enable()
592 	reg &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);  in plle_enable()
593 	reg |= pll_cml << PLLE_BASE_DIVCML_SHIFT;  in plle_enable()
594 	WR4(sc, sc->base_reg, reg);  in plle_enable()
602 	RD4(sc, PLLE_SS_CNTL, &reg);  in plle_enable()
603 	reg &= ~PLLE_SS_CNTL_SSCCENTER;  in plle_enable()
604 	reg &= ~PLLE_SS_CNTL_SSCINVERT;  in plle_enable()
605 	reg &= ~PLLE_SS_CNTL_COEFFICIENTS_MASK;  in plle_enable()
606 	reg |= PLLE_SS_CNTL_COEFFICIENTS_VAL;  in plle_enable()
607 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
608 	reg &= ~PLLE_SS_CNTL_SSCBYP;  in plle_enable()
609 	reg &= ~PLLE_SS_CNTL_BYPASS_SS;  in plle_enable()
610 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
613 	reg &= ~PLLE_SS_CNTL_INTERP_RESET;  in plle_enable()
614 	WR4(sc, PLLE_SS_CNTL, reg);  in plle_enable()
618 	RD4(sc, sc->misc_reg, &reg);  in plle_enable()
619 	reg &= ~PLLE_MISC_IDDQ_SWCTL;  in plle_enable()
620 	WR4(sc, sc->misc_reg, reg);  in plle_enable()
622 	RD4(sc, PLLE_AUX, &reg);  in plle_enable()
623 	reg |= PLLE_AUX_USE_LOCKDET;  in plle_enable()
624 	reg |= PLLE_AUX_SEQ_START_STATE;  in plle_enable()
625 	reg &= ~PLLE_AUX_ENABLE_SWCTL;  in plle_enable()
626 	reg &= ~PLLE_AUX_SS_SWCTL;  in plle_enable()
627 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
628 	reg |= PLLE_AUX_SEQ_START_STATE;  in plle_enable()
630 	reg |= PLLE_AUX_SEQ_ENABLE;  in plle_enable()
631 	WR4(sc, PLLE_AUX, reg);  in plle_enable()
633 	RD4(sc, XUSBIO_PLL_CFG0, &reg);  in plle_enable()
634 	reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;  in plle_enable()
635 	reg |= XUSBIO_PLL_CFG0_SEQ_START_STATE;  in plle_enable()
636 	reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;  in plle_enable()
637 	reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;  in plle_enable()
638 	WR4(sc, XUSBIO_PLL_CFG0, reg);  in plle_enable()
641 	reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE;  in plle_enable()
642 	WR4(sc, XUSBIO_PLL_CFG0, reg);  in plle_enable()
645 	RD4(sc, SATA_PLL_CFG0, &reg);  in plle_enable()
646 	reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;  in plle_enable()
647 	reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE;  in plle_enable()
648 	reg |=  SATA_PLL_CFG0_PADPLL_USE_LOCKDET;  in plle_enable()
649 	reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL;  in plle_enable()
650 	reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE;  in plle_enable()
651 	reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE;  in plle_enable()
652 	reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE;  in plle_enable()
653 	reg &= ~SATA_PLL_CFG0_SEQ_ENABLE;  in plle_enable()
654 	reg |=  SATA_PLL_CFG0_SEQ_START_STATE;  in plle_enable()
655 	WR4(sc, SATA_PLL_CFG0, reg);  in plle_enable()
657 	reg |= SATA_PLL_CFG0_SEQ_ENABLE;  in plle_enable()
658 	WR4(sc, SATA_PLL_CFG0, reg);  in plle_enable()
661 	RD4(sc, PCIE_PLL_CFG0, &reg);  in plle_enable()
662 	reg |= PCIE_PLL_CFG0_SEQ_ENABLE;  in plle_enable()
663 	WR4(sc, PCIE_PLL_CFG0, reg);  in plle_enable()
690 	uint32_t reg;  in tegra124_pll_get_gate()  local
694 	RD4(sc, sc->base_reg, &reg);  in tegra124_pll_get_gate()
695 	*enabled = reg & PLL_BASE_ENABLE ? true: false;  in tegra124_pll_get_gate()
696 	WR4(sc, sc->base_reg, reg);  in tegra124_pll_get_gate()
704 	uint32_t reg;  in pll_set_std()  local
732 	RD4(sc, sc->base_reg, &reg);  in pll_set_std()
733 	reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);  in pll_set_std()
734 	reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);  in pll_set_std()
735 	reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,  in pll_set_std()
737 	WR4(sc, sc->base_reg, reg);  in pll_set_std()
740 	RD4(sc, sc->base_reg, &reg);  in pll_set_std()
741 	reg |= PLL_BASE_ENABLE;  in pll_set_std()
742 	WR4(sc, sc->base_reg, reg);  in pll_set_std()
745 	RD4(sc, sc->misc_reg, &reg);  in pll_set_std()
746 	reg |= sc->lock_enable;  in pll_set_std()
747 	WR4(sc, sc->misc_reg, reg);  in pll_set_std()
752 		RD4(sc, sc->base_reg, &reg);  in pll_set_std()
753 		reg &= ~PLL_BASE_ENABLE;  in pll_set_std()
754 		WR4(sc, sc->base_reg, reg);  in pll_set_std()
757 	RD4(sc, sc->misc_reg, &reg);  in pll_set_std()
886 	uint32_t reg;  in pllx_set_freq()  local
914 	RD4(sc, sc->base_reg, &reg);  in pllx_set_freq()
915 	reg &= ~PLL_BASE_ENABLE;  in pllx_set_freq()
916 	WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
919 	RD4(sc, sc->base_reg, &reg);  in pllx_set_freq()
920 	reg = set_masked(reg, m, PLL_BASE_DIVM_SHIFT, mnp_bits->m_width);  in pllx_set_freq()
921 	reg = set_masked(reg, n, PLL_BASE_DIVN_SHIFT, mnp_bits->n_width);  in pllx_set_freq()
922 	reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift,  in pllx_set_freq()
924 	WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
925 	RD4(sc, sc->base_reg, &reg);  in pllx_set_freq()
929 	RD4(sc, sc->misc_reg, &reg);  in pllx_set_freq()
930 	reg |= sc->lock_enable;  in pllx_set_freq()
931 	WR4(sc, sc->misc_reg, reg);  in pllx_set_freq()
934 	RD4(sc, sc->base_reg, &reg);  in pllx_set_freq()
935 	reg |= PLL_BASE_ENABLE;  in pllx_set_freq()
936 	WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
941 		RD4(sc, sc->base_reg, &reg);  in pllx_set_freq()
942 		reg &= ~PLL_BASE_ENABLE;  in pllx_set_freq()
943 		WR4(sc, sc->base_reg, reg);  in pllx_set_freq()
946 	RD4(sc, sc->misc_reg, &reg);  in pllx_set_freq()
1000 	uint32_t reg;  in tegra124_pll_init()  local
1005 	RD4(sc, sc->base_reg, &reg);  in tegra124_pll_init()
1006 	if (reg & PLL_BASE_ENABLE) {  in tegra124_pll_init()
1007 		RD4(sc, sc->misc_reg, &reg);  in tegra124_pll_init()
1008 		reg |= sc->lock_enable;  in tegra124_pll_init()
1009 		WR4(sc, sc->misc_reg, reg);  in tegra124_pll_init()
1012 		RD4(sc, sc->misc_reg, &reg);  in tegra124_pll_init()
1013 		reg &= ~(1 << 29);	/* Diasble lock override */  in tegra124_pll_init()
1014 		WR4(sc, sc->misc_reg, reg);  in tegra124_pll_init()
1026 	uint32_t reg, misc_reg;  in tegra124_pll_recalc()  local
1030 	RD4(sc, sc->base_reg, &reg);  in tegra124_pll_recalc()
1041 	    clknode_get_name(clk), reg, misc_reg, m, n, p, pr,  in tegra124_pll_recalc()
1042 	    (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1,  in tegra124_pll_recalc()
1081 	uint32_t reg;  in config_utmi_pll()  local
1090 	CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, &reg);  in config_utmi_pll()
1091 	reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);  in config_utmi_pll()
1092 	reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT);  in config_utmi_pll()
1093 	reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);  in config_utmi_pll()
1094 	reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT);  in config_utmi_pll()
1095 	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;  in config_utmi_pll()
1096 	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;  in config_utmi_pll()
1097 	reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;  in config_utmi_pll()
1098 	CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg);  in config_utmi_pll()
1100 	CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);  in config_utmi_pll()
1101 	reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);  in config_utmi_pll()
1102 	reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT);  in config_utmi_pll()
1103 	reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);  in config_utmi_pll()
1104 	reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT);  in config_utmi_pll()
1105 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;  in config_utmi_pll()
1106 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;  in config_utmi_pll()
1107 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP;  in config_utmi_pll()
1108 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;  in config_utmi_pll()
1109 	CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);  in config_utmi_pll()
1112 	CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);  in config_utmi_pll()
1113 	reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET;  in config_utmi_pll()
1114 	reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL;  in config_utmi_pll()
1115 	reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_START_STATE;  in config_utmi_pll()
1116 	CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);  in config_utmi_pll()
1119 	CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, &reg);  in config_utmi_pll()
1120 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP;  in config_utmi_pll()
1121 	reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;  in config_utmi_pll()
1122 	CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg);  in config_utmi_pll()
1126 	CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);  in config_utmi_pll()
1127 	reg |= UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL;  in config_utmi_pll()
1128 	reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE;  in config_utmi_pll()
1129 	CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);  in config_utmi_pll()
1133 	CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, &reg);  in config_utmi_pll()
1134 	reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE;  in config_utmi_pll()
1135 	CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg);  in config_utmi_pll()