Lines Matching refs:RD4
192 #define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r)) macro
242 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
248 reg = RD4(sc, I2C_FIFO_CONTROL); in tegra_i2c_flush_fifo()
290 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_bus_clear()
296 reg = RD4(sc, I2C_BUS_CLEAR_CONFIG); in tegra_i2c_bus_clear()
301 if ((RD4(sc, I2C_BUS_CLEAR_CONFIG) & in tegra_i2c_bus_clear()
309 status = RD4(sc, I2C_BUS_CLEAR_STATUS); in tegra_i2c_bus_clear()
344 if (RD4(sc, I2C_CONFIG_LOAD) == 0) in tegra_i2c_hw_init()
365 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_tx()
391 reg = RD4(sc, I2C_FIFO_STATUS); in tegra_i2c_rx()
395 reg = RD4(sc, I2C_RX_FIFO); in tegra_i2c_rx()
417 status = RD4(sc, I2C_INTERRUPT_SOURCE_REGISTER); in tegra_i2c_intr()
420 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); in tegra_i2c_intr()
442 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); in tegra_i2c_intr()
450 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); in tegra_i2c_intr()
458 reg = RD4(sc, I2C_INTERRUPT_MASK_REGISTER); in tegra_i2c_intr()