Lines Matching refs:RD4
73 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) macro
137 RD4(sc, ZY7_SLCR_REBOOT_STAT) & 0xf0ffffff); in zy7_slcr_cpu_reset()
271 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_source()
297 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_source()
361 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_set_freq()
410 reg = RD4(sc, ZY7_SLCR_FPGA_CLK_CTRL(unit)); in zy7_pl_fclk_get_freq()
490 reg = RD4(sc, ZY7_SLCR_FPGA_THR_CNT(unit)); in zy7_pl_fclk_enabled()
507 reg = RD4(sc, ZY7_SLCR_LVL_SHFTR_EN); in zy7_pl_level_shifters_enabled()
596 bootmode = RD4(sc, ZY7_SLCR_BOOT_MODE); in zy7_slcr_attach()
601 pss_idcode = RD4(sc, ZY7_SLCR_PSS_IDCODE); in zy7_slcr_attach()
617 zynq_reboot_status = RD4(sc, ZY7_SLCR_REBOOT_STAT); in zy7_slcr_attach()
626 arm_pll_ctrl = RD4(sc, ZY7_SLCR_ARM_PLL_CTRL); in zy7_slcr_attach()
627 ddr_pll_ctrl = RD4(sc, ZY7_SLCR_DDR_PLL_CTRL); in zy7_slcr_attach()
628 io_pll_ctrl = RD4(sc, ZY7_SLCR_IO_PLL_CTRL); in zy7_slcr_attach()