72 	uint32_t reg;  in etm_prepare()  local
83 	reg = TRCCONFIGR_RS | TRCCONFIGR_TS;  in etm_prepare()
84 	reg |= TRCCONFIGR_CID | TRCCONFIGR_VMID;  in etm_prepare()
85 	reg |= TRCCONFIGR_INSTP0_LDRSTR;  in etm_prepare()
86 	reg |= TRCCONFIGR_COND_ALL;  in etm_prepare()
87 	bus_write_4(sc->res, TRCCONFIGR, reg);  in etm_prepare()
112 	reg = TRCVICTLR_SSSTATUS;  in etm_prepare()
115 	reg |= (1 << EVENT_SEL_S);  in etm_prepare()
120 	reg |= TRCVICTLR_EXLEVEL_NS_M;  in etm_prepare()
121 	reg &= ~TRCVICTLR_EXLEVEL_NS(event->excp_level);  in etm_prepare()
122 	reg |= TRCVICTLR_EXLEVEL_S_M;  in etm_prepare()
123 	reg &= ~TRCVICTLR_EXLEVEL_S(event->excp_level);  in etm_prepare()
124 	bus_write_4(sc->res, TRCVICTLR, reg);  in etm_prepare()
131 		reg = 0;  in etm_prepare()
133 		reg |= TRCACATR_EXLEVEL_S_M;  in etm_prepare()
134 		reg &= ~TRCACATR_EXLEVEL_S(event->excp_level);  in etm_prepare()
136 		reg |= TRCACATR_EXLEVEL_NS_M;  in etm_prepare()
137 		reg &= ~TRCACATR_EXLEVEL_NS(event->excp_level);  in etm_prepare()
138 		bus_write_4(sc->res, TRCACATR(i), reg);  in etm_prepare()
141 		reg = bus_read_4(sc->res, TRCVIIECTLR);  in etm_prepare()
142 		reg |= (1 << (TRCVIIECTLR_INCLUDE_S + i / 2));  in etm_prepare()
143 		bus_write_4(sc->res, TRCVIIECTLR, reg);  in etm_prepare()
173 	uint32_t reg __unused;  in etm_init()
183 	reg = bus_read_4(sc->res, TRCIDR(1));  in etm_init()
185 	    (reg & TRCIDR1_TRCARCHMAJ_M) >> TRCIDR1_TRCARCHMAJ_S,  in etm_init()
186 	    (reg & TRCIDR1_TRCARCHMIN_M) >> TRCIDR1_TRCARCHMIN_S);  in etm_init()
196 	uint32_t reg;  in etm_enable()  local
207 		reg = bus_read_4(sc->res, TRCSTATR);  in etm_enable()
208 	} while ((reg & TRCSTATR_IDLE) == 1);  in etm_enable()
221 	uint32_t reg;  in etm_disable()  local
230 		reg = bus_read_4(sc->res, TRCSTATR);  in etm_disable()
231 	} while ((reg & TRCSTATR_IDLE) == 0);  in etm_disable()