Lines Matching refs:reg
600 uint32_t reg; in pll_enable() local
603 RD4(sc, sc->base_reg, ®); in pll_enable()
605 reg &= ~PLL_BASE_BYPASS; in pll_enable()
606 reg |= PLL_BASE_ENABLE; in pll_enable()
607 WR4(sc, sc->base_reg, reg); in pll_enable()
614 uint32_t reg; in pll_disable() local
616 RD4(sc, sc->base_reg, ®); in pll_disable()
618 reg |= PLL_BASE_BYPASS; in pll_disable()
619 reg &= ~PLL_BASE_ENABLE; in pll_disable()
620 WR4(sc, sc->base_reg, reg); in pll_disable()
646 reg_to_pdiv(struct pll_sc *sc, uint32_t reg) in reg_to_pdiv() argument
653 return (1 << reg); in reg_to_pdiv()
655 return (reg == 0 ? 1: reg); in reg_to_pdiv()
658 if (reg == tbl->value) in reg_to_pdiv()
710 uint32_t reg; in is_locked() local
714 RD4(sc, sc->misc_reg, ®); in is_locked()
715 reg &= PLLREFE_MISC_LOCK; in is_locked()
719 RD4(sc, sc->misc_reg, ®); in is_locked()
720 reg &= PLLE_MISC_LOCK; in is_locked()
724 RD4(sc, sc->base_reg, ®); in is_locked()
725 reg &= PLL_BASE_LOCK; in is_locked()
728 return (reg != 0); in is_locked()
751 uint32_t reg; in plle_enable() local
758 RD4(sc, sc->base_reg, ®); in plle_enable()
759 reg &= ~PLLE_BASE_LOCK_OVERRIDE; in plle_enable()
760 WR4(sc, sc->base_reg, reg); in plle_enable()
763 RD4(sc, PLLE_AUX, ®); in plle_enable()
764 reg |= PLLE_AUX_ENABLE_SWCTL; in plle_enable()
765 reg &= ~PLLE_AUX_SEQ_ENABLE; in plle_enable()
766 WR4(sc, PLLE_AUX, reg); in plle_enable()
769 RD4(sc, sc->misc_reg, ®); in plle_enable()
770 reg |= PLLE_MISC_LOCK_ENABLE; in plle_enable()
771 reg |= PLLE_MISC_IDDQ_SWCTL; in plle_enable()
772 reg &= ~PLLE_MISC_IDDQ_OVERRIDE_VALUE; in plle_enable()
773 reg |= PLLE_MISC_PTS; in plle_enable()
774 reg &= ~PLLE_MISC_VREG_BG_CTRL(~0); in plle_enable()
775 reg &= ~PLLE_MISC_VREG_CTRL(~0); in plle_enable()
776 WR4(sc, sc->misc_reg, reg); in plle_enable()
779 RD4(sc, PLLE_SS_CNTL, ®); in plle_enable()
780 reg |= PLLE_SS_CNTL_DISABLE; in plle_enable()
781 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
783 RD4(sc, sc->base_reg, ®); in plle_enable()
784 reg = set_divisors(sc, reg, pll_m, pll_n, pll_cml); in plle_enable()
785 WR4(sc, sc->base_reg, reg); in plle_enable()
793 RD4(sc, PLLE_SS_CNTL, ®); in plle_enable()
794 reg &= ~PLLE_SS_CNTL_SSCINCINTRV(~0); in plle_enable()
795 reg &= ~PLLE_SS_CNTL_SSCINC(~0); in plle_enable()
796 reg &= ~PLLE_SS_CNTL_SSCINVERT; in plle_enable()
797 reg &= ~PLLE_SS_CNTL_SSCCENTER; in plle_enable()
798 reg &= ~PLLE_SS_CNTL_SSCMAX(~0); in plle_enable()
799 reg |= PLLE_SS_CNTL_SSCINCINTRV(0x23); in plle_enable()
800 reg |= PLLE_SS_CNTL_SSCINC(0x1); in plle_enable()
801 reg |= PLLE_SS_CNTL_SSCMAX(0x21); in plle_enable()
802 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
803 reg &= ~PLLE_SS_CNTL_SSCBYP; in plle_enable()
804 reg &= ~PLLE_SS_CNTL_BYPASS_SS; in plle_enable()
805 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
808 reg &= ~PLLE_SS_CNTL_INTERP_RESET; in plle_enable()
809 WR4(sc, PLLE_SS_CNTL, reg); in plle_enable()
813 RD4(sc, sc->misc_reg, ®); in plle_enable()
814 reg &= ~PLLE_MISC_IDDQ_SWCTL; in plle_enable()
815 WR4(sc, sc->misc_reg, reg); in plle_enable()
817 RD4(sc, PLLE_AUX, ®); in plle_enable()
818 reg |= PLLE_AUX_USE_LOCKDET; in plle_enable()
819 reg |= PLLE_AUX_SS_SEQ_INCLUDE; in plle_enable()
820 reg &= ~PLLE_AUX_ENABLE_SWCTL; in plle_enable()
821 reg &= ~PLLE_AUX_SS_SWCTL; in plle_enable()
822 WR4(sc, PLLE_AUX, reg); in plle_enable()
823 reg |= PLLE_AUX_SEQ_START_STATE; in plle_enable()
825 reg |= PLLE_AUX_SEQ_ENABLE; in plle_enable()
826 WR4(sc, PLLE_AUX, reg); in plle_enable()
829 RD4(sc, XUSBIO_PLL_CFG0, ®); in plle_enable()
830 reg &= ~XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; in plle_enable()
831 reg &= ~XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL; in plle_enable()
832 reg |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET; in plle_enable()
833 reg |= XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ; in plle_enable()
834 reg &= ~XUSBIO_PLL_CFG0_SEQ_ENABLE; in plle_enable()
835 WR4(sc, XUSBIO_PLL_CFG0, reg); in plle_enable()
838 reg |= XUSBIO_PLL_CFG0_SEQ_ENABLE; in plle_enable()
839 WR4(sc, XUSBIO_PLL_CFG0, reg); in plle_enable()
843 RD4(sc, SATA_PLL_CFG0, ®); in plle_enable()
844 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL; in plle_enable()
845 reg &= ~SATA_PLL_CFG0_PADPLL_RESET_OVERRIDE_VALUE; in plle_enable()
846 reg |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET; in plle_enable()
847 reg |= SATA_PLL_CFG0_PADPLL_SLEEP_IDDQ; in plle_enable()
848 reg &= ~SATA_PLL_CFG0_SEQ_IN_SWCTL; in plle_enable()
849 reg &= ~SATA_PLL_CFG0_SEQ_RESET_INPUT_VALUE; in plle_enable()
850 reg &= ~SATA_PLL_CFG0_SEQ_LANE_PD_INPUT_VALUE; in plle_enable()
851 reg &= ~SATA_PLL_CFG0_SEQ_PADPLL_PD_INPUT_VALUE; in plle_enable()
852 reg &= ~SATA_PLL_CFG0_SEQ_ENABLE; in plle_enable()
853 WR4(sc, SATA_PLL_CFG0, reg); in plle_enable()
855 reg |= SATA_PLL_CFG0_SEQ_ENABLE; in plle_enable()
856 WR4(sc, SATA_PLL_CFG0, reg); in plle_enable()
859 RD4(sc, PCIE_PLL_CFG, ®); in plle_enable()
860 reg |= PCIE_PLL_CFG_SEQ_ENABLE; in plle_enable()
861 WR4(sc, PCIE_PLL_CFG, reg); in plle_enable()
888 uint32_t reg; in tegra210_pll_get_gate() local
892 RD4(sc, sc->base_reg, ®); in tegra210_pll_get_gate()
893 *enabled = reg & PLL_BASE_ENABLE ? true: false; in tegra210_pll_get_gate()
894 WR4(sc, sc->base_reg, reg); in tegra210_pll_get_gate()
902 uint32_t reg; in pll_set_std() local
930 RD4(sc, sc->base_reg, ®); in pll_set_std()
931 reg = set_masked(reg, m, mnp_bits->m_shift, mnp_bits->m_width); in pll_set_std()
932 reg = set_masked(reg, n, mnp_bits->n_shift, mnp_bits->n_width); in pll_set_std()
933 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pll_set_std()
935 WR4(sc, sc->base_reg, reg); in pll_set_std()
938 RD4(sc, sc->base_reg, ®); in pll_set_std()
939 reg |= PLL_BASE_ENABLE; in pll_set_std()
940 WR4(sc, sc->base_reg, reg); in pll_set_std()
943 RD4(sc, sc->misc_reg, ®); in pll_set_std()
944 reg |= sc->lock_enable; in pll_set_std()
945 WR4(sc, sc->misc_reg, reg); in pll_set_std()
950 RD4(sc, sc->base_reg, ®); in pll_set_std()
951 reg &= ~PLL_BASE_ENABLE; in pll_set_std()
952 WR4(sc, sc->base_reg, reg); in pll_set_std()
955 RD4(sc, sc->misc_reg, ®); in pll_set_std()
1117 uint32_t reg; in pllx_set_freq() local
1153 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1154 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1156 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1162 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq()
1163 reg &= ~PLLX_MISC_2_EN_DYNRAMP; in pllx_set_freq()
1164 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1167 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq()
1168 reg &= ~PLLX_MISC_2_NDIV_NEW(~0); in pllx_set_freq()
1169 reg |= PLLX_MISC_2_NDIV_NEW(n); in pllx_set_freq()
1170 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1173 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq()
1174 reg |= PLLX_MISC_2_EN_DYNRAMP; in pllx_set_freq()
1175 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1179 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq()
1180 if (reg & PLLX_MISC_2_DYNRAMP_DONE) in pllx_set_freq()
1190 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1191 reg = set_masked(reg, n, mnp_bits->n_shift, in pllx_set_freq()
1193 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1196 RD4(sc, PLLX_MISC_2, ®); in pllx_set_freq()
1197 reg &= ~PLLX_MISC_2_EN_DYNRAMP; in pllx_set_freq()
1198 WR4(sc, PLLX_MISC_2, reg); in pllx_set_freq()
1208 RD4(sc, sc->base_reg, ®); in pllx_set_freq()
1209 reg = set_masked(reg, pdiv_to_reg(sc, p), mnp_bits->p_shift, in pllx_set_freq()
1211 WR4(sc, sc->base_reg, reg); in pllx_set_freq()
1224 uint32_t reg; in pllx_init() local
1226 RD4(sc, PLLX_MISC, ®); in pllx_init()
1227 reg = PLLX_MISC_LOCK_ENABLE; in pllx_init()
1228 WR4(sc, PLLX_MISC, reg); in pllx_init()
1231 reg = 0; in pllx_init()
1232 reg |= PLLX_MISC_2_DYNRAMP_STEPA(PLLX_STEP_A); in pllx_init()
1233 reg |= PLLX_MISC_2_DYNRAMP_STEPB(PLLX_STEP_B); in pllx_init()
1234 WR4(sc, PLLX_MISC_2, reg); in pllx_init()
1237 reg = 0; in pllx_init()
1238 WR4(sc, PLLX_MISC_4, reg); in pllx_init()
1239 WR4(sc, PLLX_MISC_5, reg); in pllx_init()
1305 uint32_t reg, rv; in tegra210_pll_init() local
1316 RD4(sc, sc->base_reg, ®); in tegra210_pll_init()
1317 if (reg & PLL_BASE_ENABLE) { in tegra210_pll_init()
1318 RD4(sc, sc->misc_reg, ®); in tegra210_pll_init()
1319 reg |= sc->lock_enable; in tegra210_pll_init()
1320 WR4(sc, sc->misc_reg, reg); in tegra210_pll_init()
1323 RD4(sc, sc->misc_reg, ®); in tegra210_pll_init()
1324 reg &= ~(1 << 29); /* Disable lock override */ in tegra210_pll_init()
1325 WR4(sc, sc->misc_reg, reg); in tegra210_pll_init()
1336 uint32_t reg, misc_reg; in tegra210_pll_recalc() local
1341 RD4(sc, sc->base_reg, ®); in tegra210_pll_recalc()
1356 clknode_get_name(clk), reg, misc_reg, m, n, p, pr, in tegra210_pll_recalc()
1357 (reg >> 30) & 1, (reg >> 29) & 1, (reg >> 28) & 1, in tegra210_pll_recalc()
1399 uint32_t reg; in config_utmi_pll() local
1408 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1409 reg &= ~UTMIPLL_HW_PWRDN_CFG0_IDDQ_OVERRIDE; in config_utmi_pll()
1410 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1412 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); in config_utmi_pll()
1413 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); in config_utmi_pll()
1414 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(STABLE_COUNT); in config_utmi_pll()
1415 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); in config_utmi_pll()
1416 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(ACTIVE_DELAY_COUNT); in config_utmi_pll()
1417 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); in config_utmi_pll()
1419 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1420 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); in config_utmi_pll()
1421 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(ENABLE_DELAY_COUNT); in config_utmi_pll()
1422 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); in config_utmi_pll()
1423 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(XTAL_FREQ_COUNT); in config_utmi_pll()
1424 reg |= UTMIP_PLL_CFG1_FORCE_PLLU_POWERUP; in config_utmi_pll()
1425 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1427 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; in config_utmi_pll()
1428 reg |= UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; in config_utmi_pll()
1429 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1433 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG2, ®); in config_utmi_pll()
1434 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERUP; in config_utmi_pll()
1435 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERUP; in config_utmi_pll()
1436 reg |= UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERUP; in config_utmi_pll()
1437 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; in config_utmi_pll()
1438 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; in config_utmi_pll()
1439 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_D_POWERDOWN; in config_utmi_pll()
1440 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG2, reg); in config_utmi_pll()
1443 CLKDEV_READ_4(sc->dev, UTMIP_PLL_CFG1, ®); in config_utmi_pll()
1444 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERUP; in config_utmi_pll()
1445 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; in config_utmi_pll()
1446 CLKDEV_WRITE_4(sc->dev, UTMIP_PLL_CFG1, reg); in config_utmi_pll()
1450 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1451 reg |= UTMIPLL_HW_PWRDN_CFG0_USE_LOCKDET; in config_utmi_pll()
1452 reg &= ~UTMIPLL_HW_PWRDN_CFG0_CLK_ENABLE_SWCTL; in config_utmi_pll()
1453 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()
1456 CLKDEV_READ_4(sc->dev, XUSB_PLL_CFG0, ®); in config_utmi_pll()
1457 reg &= ~XUSB_PLL_CFG0_UTMIPLL_LOCK_DLY; in config_utmi_pll()
1458 CLKDEV_WRITE_4(sc->dev, XUSB_PLL_CFG0, reg); in config_utmi_pll()
1462 CLKDEV_READ_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, ®); in config_utmi_pll()
1463 reg |= UTMIPLL_HW_PWRDN_CFG0_SEQ_ENABLE; in config_utmi_pll()
1464 CLKDEV_WRITE_4(sc->dev, UTMIPLL_HW_PWRDN_CFG0, reg); in config_utmi_pll()