Lines Matching refs:reg
459 bus_size_t reg; member
476 .reg = r, \
545 uint32_t reg; in uphy_pex_enable() local
570 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
571 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); in uphy_pex_enable()
572 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); in uphy_pex_enable()
573 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
575 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_pex_enable()
576 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_pex_enable()
577 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_pex_enable()
578 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); in uphy_pex_enable()
580 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
581 reg |= UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD; in uphy_pex_enable()
582 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
584 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
585 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD; in uphy_pex_enable()
586 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
588 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
589 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD; in uphy_pex_enable()
590 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
596 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in uphy_pex_enable()
597 reg &= ~UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(~0); in uphy_pex_enable()
598 reg &= ~UPHY_PLL_P0_CTL4_PLL0_REFCLK_SEL(~0); in uphy_pex_enable()
599 reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_SEL(0x2); in uphy_pex_enable()
600 reg |= UPHY_PLL_P0_CTL4_PLL0_TXCLKREF_EN; in uphy_pex_enable()
601 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); in uphy_pex_enable()
603 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
604 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_MDIV(~0); in uphy_pex_enable()
605 reg &= ~UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(~0); in uphy_pex_enable()
606 reg |= UPHY_PLL_P0_CTL1_PLL0_FREQ_NDIV(0x19); in uphy_pex_enable()
607 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
609 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
610 reg &= ~UPHY_PLL_P0_CTL1_PLL0_IDDQ; in uphy_pex_enable()
611 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
613 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
614 reg &= ~UPHY_PLL_P0_CTL1_PLL0_SLEEP(~0); in uphy_pex_enable()
615 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
621 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4); in uphy_pex_enable()
622 reg |= UPHY_PLL_P0_CTL4_PLL0_REFCLKBUF_EN; in uphy_pex_enable()
623 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL4, reg); in uphy_pex_enable()
626 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
627 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_EN; in uphy_pex_enable()
628 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
630 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
631 if (reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) in uphy_pex_enable()
637 "for pad '%s' (0x%08X).\n", pad->name, reg); in uphy_pex_enable()
642 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
643 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_EN; in uphy_pex_enable()
644 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
646 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
647 if ((reg & UPHY_PLL_P0_CTL2_PLL0_CAL_DONE) == 0) in uphy_pex_enable()
659 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
660 reg |= UPHY_PLL_P0_CTL1_PLL0_ENABLE; in uphy_pex_enable()
661 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
663 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
664 if (reg & UPHY_PLL_P0_CTL1_PLL0_LOCKDET_STATUS) in uphy_pex_enable()
676 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
677 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_EN; in uphy_pex_enable()
678 reg |= UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN; in uphy_pex_enable()
679 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
682 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
683 if (reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE) in uphy_pex_enable()
694 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
695 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_EN; in uphy_pex_enable()
696 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
699 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
700 if (!(reg & UPHY_PLL_P0_CTL8_PLL0_RCAL_DONE)) in uphy_pex_enable()
712 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
713 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_CLK_EN; in uphy_pex_enable()
714 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
719 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in uphy_pex_enable()
720 reg &= ~UPHY_PLL_P0_CTL1_PLL0_PWR_OVRD; in uphy_pex_enable()
721 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL1, reg); in uphy_pex_enable()
723 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_pex_enable()
724 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_OVRD; in uphy_pex_enable()
725 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_pex_enable()
727 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8); in uphy_pex_enable()
728 reg &= ~UPHY_PLL_P0_CTL8_PLL0_RCAL_OVRD; in uphy_pex_enable()
729 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL8, reg); in uphy_pex_enable()
769 uint32_t reg; in uphy_sata_enable() local
793 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in uphy_sata_enable()
794 reg &= ~UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(~0); in uphy_sata_enable()
795 reg |= UPHY_PLL_P0_CTL2_PLL0_CAL_CTRL(0x136); in uphy_sata_enable()
796 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL2, reg); in uphy_sata_enable()
798 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in uphy_sata_enable()
799 reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0); in uphy_sata_enable()
800 reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a); in uphy_sata_enable()
801 WR4(sc, XUSB_PADCTL_UPHY_PLL_P0_CTL5, reg); in uphy_sata_enable()
803 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
804 reg |= UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD; in uphy_sata_enable()
805 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
807 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
808 reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD; in uphy_sata_enable()
809 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); in uphy_sata_enable()
811 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
812 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD; in uphy_sata_enable()
813 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); in uphy_sata_enable()
819 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in uphy_sata_enable()
820 reg &= ~UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(~0); in uphy_sata_enable()
821 reg &= ~UPHY_PLL_S0_CTL4_PLL0_REFCLK_SEL(~0); in uphy_sata_enable()
822 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_EN; in uphy_sata_enable()
825 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x2); in uphy_sata_enable()
827 reg |= UPHY_PLL_S0_CTL4_PLL0_TXCLKREF_SEL(0x0); in uphy_sata_enable()
835 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
836 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_MDIV(~0); in uphy_sata_enable()
837 reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0); in uphy_sata_enable()
839 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19); in uphy_sata_enable()
841 reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e); in uphy_sata_enable()
842 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
844 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
845 reg &= ~UPHY_PLL_S0_CTL1_PLL0_IDDQ; in uphy_sata_enable()
846 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
848 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
849 reg &= ~UPHY_PLL_S0_CTL1_PLL0_SLEEP(~0); in uphy_sata_enable()
850 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
856 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4); in uphy_sata_enable()
857 reg |= UPHY_PLL_S0_CTL4_PLL0_REFCLKBUF_EN; in uphy_sata_enable()
858 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL4, reg); in uphy_sata_enable()
861 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
862 reg |= UPHY_PLL_S0_CTL2_PLL0_CAL_EN; in uphy_sata_enable()
863 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); in uphy_sata_enable()
865 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
866 if (reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) in uphy_sata_enable()
877 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
878 reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_EN; in uphy_sata_enable()
879 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); in uphy_sata_enable()
881 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
882 if ((reg & UPHY_PLL_S0_CTL2_PLL0_CAL_DONE) == 0) in uphy_sata_enable()
894 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
895 reg |= UPHY_PLL_S0_CTL1_PLL0_ENABLE; in uphy_sata_enable()
896 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
898 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
899 if (reg & UPHY_PLL_S0_CTL1_PLL0_LOCKDET_STATUS) in uphy_sata_enable()
911 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
912 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_EN; in uphy_sata_enable()
913 reg |= UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN; in uphy_sata_enable()
914 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); in uphy_sata_enable()
916 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
917 if (reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE) in uphy_sata_enable()
928 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
929 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_EN; in uphy_sata_enable()
930 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); in uphy_sata_enable()
932 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
933 if (!(reg & UPHY_PLL_S0_CTL8_PLL0_RCAL_DONE)) in uphy_sata_enable()
944 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
945 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_CLK_EN; in uphy_sata_enable()
946 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); in uphy_sata_enable()
951 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1); in uphy_sata_enable()
952 reg &= ~UPHY_PLL_S0_CTL1_PLL0_PWR_OVRD; in uphy_sata_enable()
953 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL1, reg); in uphy_sata_enable()
955 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2); in uphy_sata_enable()
956 reg &= ~UPHY_PLL_S0_CTL2_PLL0_CAL_OVRD; in uphy_sata_enable()
957 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL2, reg); in uphy_sata_enable()
959 reg = RD4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8); in uphy_sata_enable()
960 reg &= ~UPHY_PLL_S0_CTL8_PLL0_RCAL_OVRD; in uphy_sata_enable()
961 WR4(sc, XUSB_PADCTL_UPHY_PLL_S0_CTL8, reg); in uphy_sata_enable()
1002 uint32_t reg; in usb3_port_init() local
1007 reg = RD4(sc, XUSB_PADCTL_SS_PORT_MAP); in usb3_port_init()
1009 reg &= ~SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
1011 reg |= SS_PORT_MAP_PORT_INTERNAL(port->idx); in usb3_port_init()
1012 reg &= ~SS_PORT_MAP_PORT_MAP(port->idx, ~0); in usb3_port_init()
1013 reg |= SS_PORT_MAP_PORT_MAP(port->idx, port->companion); in usb3_port_init()
1014 WR4(sc, XUSB_PADCTL_SS_PORT_MAP, reg); in usb3_port_init()
1025 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx)); in usb3_port_init()
1026 reg &= ~UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(~0); in usb3_port_init()
1027 reg |= UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL(2); in usb3_port_init()
1028 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL1(port->idx), reg); in usb3_port_init()
1030 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx)); in usb3_port_init()
1031 reg &= ~UPHY_USB3_PAD_ECTL2_RX_CTLE(~0); in usb3_port_init()
1032 reg |= UPHY_USB3_PAD_ECTL2_RX_CTLE(0x00fc); in usb3_port_init()
1033 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL2(port->idx), reg); in usb3_port_init()
1037 reg = RD4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx)); in usb3_port_init()
1038 reg &= ~UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(~0); in usb3_port_init()
1039 reg |= UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL(0x01c7); in usb3_port_init()
1040 WR4(sc, XUSB_PADCTL_UPHY_USB3_PAD_ECTL4(port->idx), reg); in usb3_port_init()
1051 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1052 reg &= ~ELPG_PROGRAM1_SSP_ELPG_VCORE_DOWN(port->idx); in usb3_port_init()
1053 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1056 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1057 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN_EARLY(port->idx); in usb3_port_init()
1058 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1061 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in usb3_port_init()
1062 reg &= ~ELPG_PROGRAM1_SSP_ELPG_CLAMP_EN(port->idx); in usb3_port_init()
1063 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in usb3_port_init()
1072 uint32_t reg; in pcie_enable() local
1079 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_enable()
1080 reg |= USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); in pcie_enable()
1081 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_enable()
1089 uint32_t reg; in pcie_disable() local
1091 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in pcie_disable()
1092 reg &= ~USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->idx); in pcie_disable()
1093 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in pcie_disable()
1104 uint32_t reg; in sata_enable() local
1111 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_enable()
1112 reg |= USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); in sata_enable()
1113 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_enable()
1121 uint32_t reg; in sata_disable() local
1123 reg = RD4(sc, XUSB_PADCTL_USB3_PAD_MUX); in sata_disable()
1124 reg &= ~USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->idx); in sata_disable()
1125 WR4(sc, XUSB_PADCTL_USB3_PAD_MUX, reg); in sata_disable()
1135 uint32_t reg; in hsic_enable() local
1158 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx)); in hsic_enable()
1159 reg &= ~HSIC_PAD_CTL1_TX_RTUNEP(~0); in hsic_enable()
1160 reg |= HSIC_PAD_CTL1_TX_RTUNEP(sc->tx_rtune_p); in hsic_enable()
1161 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); in hsic_enable()
1163 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx)); in hsic_enable()
1164 reg &= ~HSIC_PAD_CTL2_RX_STROBE_TRIM(~0); in hsic_enable()
1165 reg &= ~HSIC_PAD_CTL2_RX_DATA1_TRIM(~0); in hsic_enable()
1166 reg &= ~HSIC_PAD_CTL2_RX_DATA0_TRIM(~0); in hsic_enable()
1167 reg |= HSIC_PAD_CTL2_RX_STROBE_TRIM(sc->rx_strobe_trim); in hsic_enable()
1168 reg |= HSIC_PAD_CTL2_RX_DATA1_TRIM(sc->rx_data1_trim); in hsic_enable()
1169 reg |= HSIC_PAD_CTL2_RX_DATA0_TRIM(sc->rx_data0_trim); in hsic_enable()
1170 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL2(lane->idx), reg); in hsic_enable()
1172 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); in hsic_enable()
1173 reg &= ~HSIC_PAD_CTL0_RPU_DATA0; in hsic_enable()
1174 reg &= ~HSIC_PAD_CTL0_RPU_DATA1; in hsic_enable()
1175 reg &= ~HSIC_PAD_CTL0_RPU_STROBE; in hsic_enable()
1176 reg &= ~HSIC_PAD_CTL0_PD_RX_DATA0; in hsic_enable()
1177 reg &= ~HSIC_PAD_CTL0_PD_RX_DATA1; in hsic_enable()
1178 reg &= ~HSIC_PAD_CTL0_PD_RX_STROBE; in hsic_enable()
1179 reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA0; in hsic_enable()
1180 reg &= ~HSIC_PAD_CTL0_PD_ZI_DATA1; in hsic_enable()
1181 reg &= ~HSIC_PAD_CTL0_PD_ZI_STROBE; in hsic_enable()
1182 reg &= ~HSIC_PAD_CTL0_PD_TX_DATA0; in hsic_enable()
1183 reg &= ~HSIC_PAD_CTL0_PD_TX_DATA1; in hsic_enable()
1184 reg &= ~HSIC_PAD_CTL0_PD_TX_STROBE; in hsic_enable()
1185 reg |= HSIC_PAD_CTL0_RPD_DATA0; in hsic_enable()
1186 reg |= HSIC_PAD_CTL0_RPD_DATA1; in hsic_enable()
1187 reg |= HSIC_PAD_CTL0_RPD_STROBE; in hsic_enable()
1188 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx), reg); in hsic_enable()
1199 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in hsic_enable()
1200 reg &= ~HSIC_PAD_TRK_CTL_TRK_START_TIMER(~0); in hsic_enable()
1201 reg &= ~HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(~0); in hsic_enable()
1202 reg |= HSIC_PAD_TRK_CTL_TRK_START_TIMER(0x1e); in hsic_enable()
1203 reg |= HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER(0x0a); in hsic_enable()
1204 WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg); in hsic_enable()
1208 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL); in hsic_enable()
1209 reg &= ~HSIC_PAD_TRK_CTL_PD_TRK; in hsic_enable()
1210 WR4(sc, XUSB_PADCTL_HSIC_PAD_TRK_CTL, reg); in hsic_enable()
1220 uint32_t reg; in hsic_disable() local
1230 reg = RD4(sc, XUSB_PADCTL_HSIC_PAD_CTL0(lane->idx)); in hsic_disable()
1231 reg |= HSIC_PAD_CTL0_PD_RX_DATA0; in hsic_disable()
1232 reg |= HSIC_PAD_CTL0_PD_RX_DATA1; in hsic_disable()
1233 reg |= HSIC_PAD_CTL0_PD_RX_STROBE; in hsic_disable()
1234 reg |= HSIC_PAD_CTL0_PD_ZI_DATA0; in hsic_disable()
1235 reg |= HSIC_PAD_CTL0_PD_ZI_DATA1; in hsic_disable()
1236 reg |= HSIC_PAD_CTL0_PD_ZI_STROBE; in hsic_disable()
1237 reg |= HSIC_PAD_CTL0_PD_TX_DATA0; in hsic_disable()
1238 reg |= HSIC_PAD_CTL0_PD_TX_DATA1; in hsic_disable()
1239 reg |= HSIC_PAD_CTL0_PD_TX_STROBE; in hsic_disable()
1240 WR4(sc, XUSB_PADCTL_HSIC_PAD_CTL1(lane->idx), reg); in hsic_disable()
1257 uint32_t reg; in usb2_enable() local
1269 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in usb2_enable()
1270 reg &= ~USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL(~0); in usb2_enable()
1271 reg &= ~USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(~0); in usb2_enable()
1272 reg |= USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL(0x7); in usb2_enable()
1273 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); in usb2_enable()
1275 reg = RD4(sc, XUSB_PADCTL_USB2_PORT_CAP); in usb2_enable()
1276 reg &= ~USB2_PORT_CAP_PORT_CAP(lane->idx, ~0); in usb2_enable()
1277 reg |= USB2_PORT_CAP_PORT_CAP(lane->idx, USB2_PORT_CAP_PORT_CAP_HOST); in usb2_enable()
1278 WR4(sc, XUSB_PADCTL_USB2_PORT_CAP, reg); in usb2_enable()
1280 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx)); in usb2_enable()
1281 reg &= ~USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(~0); in usb2_enable()
1282 reg &= ~USB2_OTG_PAD_CTL0_HS_SLEW(~0); in usb2_enable()
1283 reg &= ~USB2_OTG_PAD_CTL0_PD; in usb2_enable()
1284 reg &= ~USB2_OTG_PAD_CTL0_PD2; in usb2_enable()
1285 reg &= ~USB2_OTG_PAD_CTL0_PD_ZI; in usb2_enable()
1286 reg |= USB2_OTG_PAD_CTL0_HS_SLEW(14); in usb2_enable()
1287 reg |= USB2_OTG_PAD_CTL0_HS_CURR_LEVEL(sc->hs_curr_level[lane->idx] + in usb2_enable()
1289 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL0(lane->idx), reg); in usb2_enable()
1291 reg = RD4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx)); in usb2_enable()
1292 reg &= ~USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(~0); in usb2_enable()
1293 reg &= ~USB2_OTG_PAD_CTL1_RPD_CTRL(~0); in usb2_enable()
1294 reg &= ~USB2_OTG_PAD_CTL1_PD_DR; in usb2_enable()
1295 reg &= ~USB2_OTG_PAD_CTL1_PD_CHRP_OVRD; in usb2_enable()
1296 reg &= ~USB2_OTG_PAD_CTL1_PD_DISC_OVRD; in usb2_enable()
1297 reg |= USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ(sc->hs_term_range_adj); in usb2_enable()
1298 reg |= USB2_OTG_PAD_CTL1_RPD_CTRL(sc->rpd_ctrl); in usb2_enable()
1299 WR4(sc, XUSB_PADCTL_USB2_OTG_PAD_CTL1(lane->idx), reg); in usb2_enable()
1301 reg = RD4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx)); in usb2_enable()
1302 reg &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0); in usb2_enable()
1303 reg |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18; in usb2_enable()
1304 WR4(sc, XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1(lane->idx), reg); in usb2_enable()
1322 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in usb2_enable()
1323 reg &= ~USB2_BIAS_PAD_CTL1_TRK_START_TIMER(~0); in usb2_enable()
1324 reg &= ~USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(~0); in usb2_enable()
1325 reg |= USB2_BIAS_PAD_CTL1_TRK_START_TIMER(0x1e); in usb2_enable()
1326 reg |= USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER(0x0a); in usb2_enable()
1327 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL1, reg); in usb2_enable()
1329 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in usb2_enable()
1330 reg &= ~USB2_BIAS_PAD_CTL0_PD; in usb2_enable()
1331 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); in usb2_enable()
1338 uint32_t reg; in usb2_disable() local
1350 reg = RD4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in usb2_disable()
1351 reg |= USB2_BIAS_PAD_CTL0_PD; in usb2_disable()
1352 WR4(sc, XUSB_PADCTL_USB2_BIAS_PAD_CTL0, reg); in usb2_disable()
1377 uint32_t reg; in pad_common_enable() local
1379 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable()
1380 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in pad_common_enable()
1381 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_enable()
1384 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable()
1385 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in pad_common_enable()
1386 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_enable()
1389 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_enable()
1390 reg &= ~ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in pad_common_enable()
1391 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_enable()
1400 uint32_t reg; in pad_common_disable() local
1402 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_disable()
1403 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN; in pad_common_disable()
1404 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_disable()
1407 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_disable()
1408 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY; in pad_common_disable()
1409 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_disable()
1412 reg = RD4(sc, XUSB_PADCTL_ELPG_PROGRAM1); in pad_common_disable()
1413 reg |= ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN; in pad_common_disable()
1414 WR4(sc, XUSB_PADCTL_ELPG_PROGRAM1, reg); in pad_common_disable()
1584 uint32_t reg; in config_lane() local
1586 reg = RD4(sc, lane->reg); in config_lane()
1587 reg &= ~(lane->mask << lane->shift); in config_lane()
1588 reg |= (lane->mux_idx & lane->mask) << lane->shift; in config_lane()
1589 WR4(sc, lane->reg, reg); in config_lane()
1851 uint32_t reg; in load_calibration() local
1854 reg = tegra_fuse_read_4(FUSE_SKU_CALIB_0); in load_calibration()
1855 sc->hs_curr_level[0] = FUSE_SKU_CALIB_0_HS_CURR_LEVEL_0(reg); in load_calibration()
1858 FUSE_SKU_CALIB_0_HS_CURR_LEVEL_123(reg, i); in load_calibration()
1860 sc->hs_term_range_adj = FUSE_SKU_CALIB_0_HS_TERM_RANGE_ADJ(reg); in load_calibration()
1863 sc->rpd_ctrl = FUSE_USB_CALIB_EXT_0_RPD_CTRL(reg); in load_calibration()