Lines Matching defs:src
83 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
95 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
107 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
108 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
109 #define MAC_DMA_CR__RXD__MODIFY(dst, src) \ argument
113 #define MAC_DMA_CR__RXD__VERIFY(src) \ argument
127 #define MAC_DMA_CR__SWI__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
139 #define MAC_DMA_CR__SPARE__READ(src) (((u_int32_t)(src) & 0x00000780U) >> 7) argument
140 #define MAC_DMA_CR__SPARE__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000780U) argument
141 #define MAC_DMA_CR__SPARE__MODIFY(dst, src) \ argument
145 #define MAC_DMA_CR__SPARE__VERIFY(src) \ argument
166 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \ argument
169 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \ argument
172 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \ argument
176 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \ argument
190 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \ argument
193 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \ argument
196 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \ argument
200 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \ argument
214 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \ argument
217 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \ argument
220 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \ argument
224 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \ argument
238 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \ argument
241 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \ argument
244 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \ argument
248 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \ argument
262 #define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \ argument
265 #define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \ argument
268 #define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \ argument
272 #define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \ argument
286 #define MAC_DMA_CFG__ADHOC__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
287 #define MAC_DMA_CFG__ADHOC__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
288 #define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \ argument
292 #define MAC_DMA_CFG__ADHOC__VERIFY(src) \ argument
306 #define MAC_DMA_CFG__PHY_OK__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
318 #define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \ argument
332 #define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \ argument
335 #define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \ argument
338 #define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \ argument
342 #define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \ argument
356 #define MAC_DMA_CFG__HALT_REQ__READ(src) \ argument
359 #define MAC_DMA_CFG__HALT_REQ__WRITE(src) \ argument
362 #define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \ argument
366 #define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \ argument
380 #define MAC_DMA_CFG__HALT_ACK__READ(src) \ argument
394 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \ argument
397 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \ argument
400 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \ argument
404 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \ argument
412 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \ argument
415 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \ argument
418 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \ argument
422 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \ argument
436 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__READ(src) \ argument
439 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__WRITE(src) \ argument
442 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__MODIFY(dst, src) \ argument
446 #define MAC_DMA_CFG__LEGACY_INT_MIT_MODE_ENABLE__VERIFY(src) \ argument
460 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__READ(src) \ argument
463 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__WRITE(src) \ argument
466 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__MODIFY(dst, src) \ argument
470 #define MAC_DMA_CFG__RESET_INT_MIT_CNTRS__VERIFY(src) \ argument
497 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \ argument
500 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \ argument
503 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \ argument
507 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \ argument
515 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \ argument
518 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \ argument
521 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \ argument
525 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \ argument
546 #define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src) (u_int32_t)(src) & 0x0000000fU argument
547 #define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \ argument
550 #define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \ argument
554 #define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \ argument
575 #define MAC_DMA_MIRT__RATE_THRESH__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
576 #define MAC_DMA_MIRT__RATE_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
577 #define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \ argument
581 #define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \ argument
602 #define MAC_DMA_GLOBAL_IER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
603 #define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
604 #define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \ argument
608 #define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \ argument
635 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__READ(src) \ argument
638 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__WRITE(src) \ argument
641 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
645 #define MAC_DMA_TIMT_ALIAS__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
653 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__READ(src) \ argument
656 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
659 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
663 #define MAC_DMA_TIMT_ALIAS__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
684 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \ argument
687 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \ argument
690 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
694 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \ argument
702 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \ argument
705 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \ argument
708 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
712 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \ argument
733 #define MAC_DMA_TXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U argument
734 #define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
735 #define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \ argument
739 #define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \ argument
747 #define MAC_DMA_TXCFG__TRIGLVL__READ(src) \ argument
750 #define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \ argument
753 #define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \ argument
757 #define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \ argument
765 #define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \ argument
768 #define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \ argument
771 #define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \ argument
775 #define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \ argument
789 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \ argument
792 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \ argument
795 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \ argument
799 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \ argument
813 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \ argument
816 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \ argument
819 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \ argument
823 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \ argument
837 #define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \ argument
840 #define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \ argument
843 #define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \ argument
847 #define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \ argument
861 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \ argument
864 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \ argument
867 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \ argument
871 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \ argument
885 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \ argument
888 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \ argument
891 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \ argument
895 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \ argument
909 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__READ(src) \ argument
912 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__WRITE(src) \ argument
915 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__MODIFY(dst, src) \ argument
919 #define MAC_DMA_TXCFG__RTS_FAIL_EXCESSIVE_RETRIES__VERIFY(src) \ argument
946 #define MAC_DMA_RXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U argument
947 #define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
948 #define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \ argument
952 #define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \ argument
960 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \ argument
963 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \ argument
966 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \ argument
970 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \ argument
978 #define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \ argument
981 #define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \ argument
984 #define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \ argument
988 #define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \ argument
1002 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \ argument
1005 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \ argument
1008 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \ argument
1012 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \ argument
1026 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \ argument
1029 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \ argument
1032 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \ argument
1036 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \ argument
1063 #define MAC_DMA_RXJLA__DATA__READ(src) (((u_int32_t)(src) & 0xfffffffcU) >> 2) argument
1081 #define MAC_DMA_MIBC__WARNING__READ(src) (u_int32_t)(src) & 0x00000001U argument
1093 #define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
1094 #define MAC_DMA_MIBC__FREEZE__WRITE(src) \ argument
1097 #define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \ argument
1101 #define MAC_DMA_MIBC__FREEZE__VERIFY(src) \ argument
1115 #define MAC_DMA_MIBC__CLEAR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
1116 #define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
1117 #define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \ argument
1121 #define MAC_DMA_MIBC__CLEAR__VERIFY(src) \ argument
1135 #define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
1160 #define MAC_DMA_TOPS__TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
1161 #define MAC_DMA_TOPS__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
1162 #define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \ argument
1166 #define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \ argument
1187 #define MAC_DMA_RXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU argument
1188 #define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
1189 #define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \ argument
1193 #define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \ argument
1214 #define MAC_DMA_TXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU argument
1215 #define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
1216 #define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \ argument
1220 #define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \ argument
1228 #define MAC_DMA_TXNPTO__MASK__READ(src) \ argument
1231 #define MAC_DMA_TXNPTO__MASK__WRITE(src) \ argument
1234 #define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \ argument
1238 #define MAC_DMA_TXNPTO__MASK__VERIFY(src) \ argument
1259 #define MAC_DMA_RPGTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU argument
1260 #define MAC_DMA_RPGTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
1261 #define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \ argument
1265 #define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \ argument
1286 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \ argument
1289 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \ argument
1292 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \ argument
1296 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \ argument
1310 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \ argument
1313 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \ argument
1316 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \ argument
1320 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \ argument
1328 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \ argument
1331 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \ argument
1334 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \ argument
1338 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \ argument
1346 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \ argument
1349 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \ argument
1352 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \ argument
1356 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \ argument
1364 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \ argument
1367 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \ argument
1370 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \ argument
1374 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \ argument
1395 #define MAC_DMA_INTER__REQ__READ(src) (u_int32_t)(src) & 0x00000001U argument
1396 #define MAC_DMA_INTER__REQ__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
1397 #define MAC_DMA_INTER__REQ__MODIFY(dst, src) \ argument
1401 #define MAC_DMA_INTER__REQ__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
1413 #define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \ argument
1416 #define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \ argument
1419 #define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \ argument
1423 #define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \ argument
1431 #define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \ argument
1434 #define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \ argument
1437 #define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \ argument
1441 #define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \ argument
1462 #define MAC_DMA_DATABUF__LEN__READ(src) (u_int32_t)(src) & 0x00000fffU argument
1463 #define MAC_DMA_DATABUF__LEN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) argument
1464 #define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \ argument
1468 #define MAC_DMA_DATABUF__LEN__VERIFY(src) \ argument
1489 #define MAC_DMA_GTT__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
1490 #define MAC_DMA_GTT__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
1491 #define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \ argument
1495 #define MAC_DMA_GTT__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) argument
1501 #define MAC_DMA_GTT__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) argument
1502 #define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) argument
1503 #define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \ argument
1507 #define MAC_DMA_GTT__LIMIT__VERIFY(src) \ argument
1528 #define MAC_DMA_GTTM__USEC_STROBE__READ(src) (u_int32_t)(src) & 0x00000001U argument
1529 #define MAC_DMA_GTTM__USEC_STROBE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
1530 #define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \ argument
1534 #define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \ argument
1548 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \ argument
1551 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \ argument
1554 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \ argument
1558 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \ argument
1572 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \ argument
1575 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \ argument
1578 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \ argument
1582 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \ argument
1596 #define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \ argument
1599 #define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \ argument
1602 #define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \ argument
1606 #define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \ argument
1620 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \ argument
1623 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \ argument
1626 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \ argument
1630 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \ argument
1644 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \ argument
1647 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \ argument
1650 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \ argument
1654 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \ argument
1681 #define MAC_DMA_CST__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
1682 #define MAC_DMA_CST__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
1683 #define MAC_DMA_CST__COUNT__MODIFY(dst, src) \ argument
1687 #define MAC_DMA_CST__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) argument
1693 #define MAC_DMA_CST__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16) argument
1694 #define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U) argument
1695 #define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \ argument
1699 #define MAC_DMA_CST__LIMIT__VERIFY(src) \ argument
1720 #define MAC_DMA_RXDP_SIZE__LP__READ(src) (u_int32_t)(src) & 0x000000ffU argument
1726 #define MAC_DMA_RXDP_SIZE__HP__READ(src) \ argument
1746 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \ argument
1749 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \ argument
1752 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \ argument
1756 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \ argument
1777 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \ argument
1780 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \ argument
1783 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \ argument
1787 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \ argument
1808 #define MAC_DMA_ISR_P__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1809 #define MAC_DMA_ISR_P__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1810 #define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \ argument
1814 #define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
1833 #define MAC_DMA_ISR_S0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1834 #define MAC_DMA_ISR_S0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1835 #define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \ argument
1839 #define MAC_DMA_ISR_S0__DATA__VERIFY(src) \ argument
1860 #define MAC_DMA_ISR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1861 #define MAC_DMA_ISR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1862 #define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \ argument
1866 #define MAC_DMA_ISR_S1__DATA__VERIFY(src) \ argument
1887 #define MAC_DMA_ISR_S2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1888 #define MAC_DMA_ISR_S2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1889 #define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \ argument
1893 #define MAC_DMA_ISR_S2__DATA__VERIFY(src) \ argument
1914 #define MAC_DMA_ISR_S3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1915 #define MAC_DMA_ISR_S3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1916 #define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \ argument
1920 #define MAC_DMA_ISR_S3__DATA__VERIFY(src) \ argument
1941 #define MAC_DMA_ISR_S4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1942 #define MAC_DMA_ISR_S4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1943 #define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \ argument
1947 #define MAC_DMA_ISR_S4__DATA__VERIFY(src) \ argument
1968 #define MAC_DMA_ISR_S5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1969 #define MAC_DMA_ISR_S5__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1970 #define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \ argument
1974 #define MAC_DMA_ISR_S5__DATA__VERIFY(src) \ argument
1995 #define MAC_DMA_IMR_P__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
1996 #define MAC_DMA_IMR_P__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
1997 #define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \ argument
2001 #define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
2020 #define MAC_DMA_IMR_S0__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2021 #define MAC_DMA_IMR_S0__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2022 #define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \ argument
2026 #define MAC_DMA_IMR_S0__MASK__VERIFY(src) \ argument
2047 #define MAC_DMA_IMR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2048 #define MAC_DMA_IMR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2049 #define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \ argument
2053 #define MAC_DMA_IMR_S1__DATA__VERIFY(src) \ argument
2074 #define MAC_DMA_IMR_S2__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2075 #define MAC_DMA_IMR_S2__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2076 #define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \ argument
2080 #define MAC_DMA_IMR_S2__MASK__VERIFY(src) \ argument
2101 #define MAC_DMA_IMR_S3__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2102 #define MAC_DMA_IMR_S3__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2103 #define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \ argument
2107 #define MAC_DMA_IMR_S3__MASK__VERIFY(src) \ argument
2128 #define MAC_DMA_IMR_S4__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2129 #define MAC_DMA_IMR_S4__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2130 #define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \ argument
2134 #define MAC_DMA_IMR_S4__MASK__VERIFY(src) \ argument
2155 #define MAC_DMA_IMR_S5__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2156 #define MAC_DMA_IMR_S5__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2157 #define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \ argument
2161 #define MAC_DMA_IMR_S5__MASK__VERIFY(src) \ argument
2182 #define MAC_DMA_ISR_P_RAC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2200 #define MAC_DMA_ISR_S0_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2218 #define MAC_DMA_ISR_S1_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2236 #define MAC_DMA_ISR_S2_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2254 #define MAC_DMA_ISR_S3_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2272 #define MAC_DMA_ISR_S4_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2290 #define MAC_DMA_ISR_S5_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2308 #define MAC_DMA_DMADBG_0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2326 #define MAC_DMA_DMADBG_1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2344 #define MAC_DMA_DMADBG_2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2362 #define MAC_DMA_DMADBG_3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2380 #define MAC_DMA_DMADBG_4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2398 #define MAC_DMA_DMADBG_5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2416 #define MAC_DMA_DMADBG_6__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2434 #define MAC_DMA_DMADBG_7__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2452 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \ argument
2472 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \ argument
2492 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__READ(src) \ argument
2495 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2498 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2502 #define MAC_DMA_TIMT_0__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2510 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__READ(src) \ argument
2513 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2516 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2520 #define MAC_DMA_TIMT_0__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2541 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__READ(src) \ argument
2544 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2547 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2551 #define MAC_DMA_TIMT_1__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2559 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__READ(src) \ argument
2562 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2565 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2569 #define MAC_DMA_TIMT_1__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2590 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__READ(src) \ argument
2593 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2596 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2600 #define MAC_DMA_TIMT_2__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2608 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__READ(src) \ argument
2611 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2614 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2618 #define MAC_DMA_TIMT_2__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2639 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__READ(src) \ argument
2642 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2645 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2649 #define MAC_DMA_TIMT_3__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2657 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__READ(src) \ argument
2660 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2663 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2667 #define MAC_DMA_TIMT_3__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2688 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__READ(src) \ argument
2691 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2694 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2698 #define MAC_DMA_TIMT_4__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2706 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__READ(src) \ argument
2709 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2712 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2716 #define MAC_DMA_TIMT_4__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2737 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__READ(src) \ argument
2740 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2743 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2747 #define MAC_DMA_TIMT_5__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2755 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__READ(src) \ argument
2758 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2761 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2765 #define MAC_DMA_TIMT_5__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2786 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__READ(src) \ argument
2789 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2792 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2796 #define MAC_DMA_TIMT_6__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2804 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__READ(src) \ argument
2807 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2810 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2814 #define MAC_DMA_TIMT_6__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2835 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__READ(src) \ argument
2838 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2841 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2845 #define MAC_DMA_TIMT_7__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2853 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__READ(src) \ argument
2856 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2859 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2863 #define MAC_DMA_TIMT_7__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2884 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__READ(src) \ argument
2887 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2890 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2894 #define MAC_DMA_TIMT_8__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2902 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__READ(src) \ argument
2905 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2908 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2912 #define MAC_DMA_TIMT_8__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2933 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__READ(src) \ argument
2936 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__WRITE(src) \ argument
2939 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__MODIFY(dst, src) \ argument
2943 #define MAC_DMA_TIMT_9__TX_LAST_PKT_THRESH__VERIFY(src) \ argument
2951 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__READ(src) \ argument
2954 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__WRITE(src) \ argument
2957 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \ argument
2961 #define MAC_DMA_TIMT_9__TX_FIRST_PKT_THRESH__VERIFY(src) \ argument
2982 #define MAC_QCU_TXDP__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
2983 #define MAC_QCU_TXDP__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
2984 #define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \ argument
2988 #define MAC_QCU_TXDP__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
3007 #define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \ argument
3010 #define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \ argument
3013 #define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \ argument
3017 #define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \ argument
3038 #define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU argument
3039 #define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \ argument
3042 #define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \ argument
3046 #define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \ argument
3067 #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \ argument
3087 #define MAC_QCU_TXE__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3105 #define MAC_QCU_TXD__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3106 #define MAC_QCU_TXD__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
3107 #define MAC_QCU_TXD__DATA__MODIFY(dst, src) \ argument
3111 #define MAC_QCU_TXD__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) argument
3117 #define MAC_QCU_TXD__SPARE__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10) argument
3118 #define MAC_QCU_TXD__SPARE__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U) argument
3119 #define MAC_QCU_TXD__SPARE__MODIFY(dst, src) \ argument
3123 #define MAC_QCU_TXD__SPARE__VERIFY(src) \ argument
3144 #define MAC_QCU_CBR__INTERVAL__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
3145 #define MAC_QCU_CBR__INTERVAL__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) argument
3146 #define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \ argument
3150 #define MAC_QCU_CBR__INTERVAL__VERIFY(src) \ argument
3158 #define MAC_QCU_CBR__OVF_THRESH__READ(src) \ argument
3161 #define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \ argument
3164 #define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \ argument
3168 #define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \ argument
3189 #define MAC_QCU_RDYTIME__DURATION__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
3190 #define MAC_QCU_RDYTIME__DURATION__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) argument
3191 #define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \ argument
3195 #define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \ argument
3203 #define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
3204 #define MAC_QCU_RDYTIME__EN__WRITE(src) \ argument
3207 #define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \ argument
3211 #define MAC_QCU_RDYTIME__EN__VERIFY(src) \ argument
3238 #define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3239 #define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \ argument
3242 #define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \ argument
3246 #define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \ argument
3267 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3268 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \ argument
3271 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \ argument
3275 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \ argument
3296 #define MAC_QCU_MISC__FSP__READ(src) (u_int32_t)(src) & 0x0000000fU argument
3297 #define MAC_QCU_MISC__FSP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
3298 #define MAC_QCU_MISC__FSP__MODIFY(dst, src) \ argument
3302 #define MAC_QCU_MISC__FSP__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) argument
3308 #define MAC_QCU_MISC__ONESHOT_EN__READ(src) \ argument
3311 #define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \ argument
3314 #define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \ argument
3318 #define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \ argument
3332 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \ argument
3335 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \ argument
3338 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \ argument
3342 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \ argument
3356 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \ argument
3359 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \ argument
3362 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \ argument
3366 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \ argument
3380 #define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
3381 #define MAC_QCU_MISC__IS_BCN__WRITE(src) \ argument
3384 #define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \ argument
3388 #define MAC_QCU_MISC__IS_BCN__VERIFY(src) \ argument
3402 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \ argument
3405 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \ argument
3408 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \ argument
3412 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \ argument
3426 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \ argument
3429 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \ argument
3432 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \ argument
3436 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \ argument
3450 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \ argument
3453 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \ argument
3456 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \ argument
3460 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \ argument
3474 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \ argument
3477 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \ argument
3480 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \ argument
3484 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \ argument
3511 #define MAC_QCU_CNT__FR_PEND__READ(src) (u_int32_t)(src) & 0x00000003U argument
3517 #define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
3535 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \ argument
3538 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \ argument
3541 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \ argument
3545 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \ argument
3567 #define MAC_QCU_DESC_CRC_CHK__EN__READ(src) (u_int32_t)(src) & 0x00000001U argument
3568 #define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
3569 #define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \ argument
3573 #define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \ argument
3600 #define MAC_DCU_QCUMASK__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3601 #define MAC_DCU_QCUMASK__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
3602 #define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \ argument
3606 #define MAC_DCU_QCUMASK__DATA__VERIFY(src) \ argument
3627 #define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \ argument
3630 #define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \ argument
3633 #define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \ argument
3637 #define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \ argument
3658 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \ argument
3661 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \ argument
3664 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \ argument
3668 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \ argument
3689 #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \ argument
3709 #define MAC_DCU_LCL_IFS__CW_MIN__READ(src) (u_int32_t)(src) & 0x000003ffU argument
3710 #define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
3711 #define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \ argument
3715 #define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \ argument
3723 #define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \ argument
3726 #define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \ argument
3729 #define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \ argument
3733 #define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \ argument
3741 #define MAC_DCU_LCL_IFS__AIFS__READ(src) \ argument
3744 #define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \ argument
3747 #define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \ argument
3751 #define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \ argument
3759 #define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \ argument
3762 #define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \ argument
3765 #define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \ argument
3769 #define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \ argument
3796 #define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \ argument
3799 #define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \ argument
3802 #define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \ argument
3806 #define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \ argument
3827 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \ argument
3830 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \ argument
3833 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \ argument
3837 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \ argument
3858 #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \ argument
3878 #define MAC_DCU_RETRY_LIMIT__FRFL__READ(src) (u_int32_t)(src) & 0x0000000fU argument
3879 #define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
3880 #define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \ argument
3884 #define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \ argument
3892 #define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \ argument
3895 #define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \ argument
3898 #define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \ argument
3902 #define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \ argument
3910 #define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \ argument
3913 #define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \ argument
3916 #define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \ argument
3920 #define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \ argument
3941 #define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \ argument
3944 #define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \ argument
3947 #define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \ argument
3951 #define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \ argument
3972 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \ argument
3975 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \ argument
3978 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \ argument
3982 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \ argument
4003 #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \ argument
4023 #define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \ argument
4026 #define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \ argument
4029 #define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \ argument
4033 #define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \ argument
4041 #define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \ argument
4044 #define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \ argument
4047 #define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \ argument
4051 #define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \ argument
4078 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \ argument
4081 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \ argument
4084 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \ argument
4088 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \ argument
4096 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \ argument
4099 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \ argument
4102 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \ argument
4106 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \ argument
4120 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \ argument
4123 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \ argument
4126 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \ argument
4130 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \ argument
4138 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \ argument
4141 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \ argument
4144 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \ argument
4148 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \ argument
4156 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \ argument
4159 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \ argument
4162 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \ argument
4166 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \ argument
4180 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \ argument
4183 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \ argument
4186 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \ argument
4190 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \ argument
4204 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \ argument
4207 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \ argument
4210 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \ argument
4214 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \ argument
4228 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \ argument
4231 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \ argument
4234 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \ argument
4238 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \ argument
4246 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \ argument
4249 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \ argument
4252 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \ argument
4256 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \ argument
4270 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \ argument
4273 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \ argument
4276 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \ argument
4280 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \ argument
4294 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__READ(src) \ argument
4297 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__WRITE(src) \ argument
4300 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__MODIFY(dst, src) \ argument
4304 #define MAC_DCU_GBL_IFS_MISC__SLOT_COUNT_RST_UNCOND__VERIFY(src) \ argument
4331 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \ argument
4334 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \ argument
4337 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \ argument
4341 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \ argument
4362 #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \ argument
4382 #define MAC_DCU_MISC__BKOFF_THRESH__READ(src) (u_int32_t)(src) & 0x0000003fU argument
4383 #define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
4384 #define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \ argument
4388 #define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \ argument
4396 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \ argument
4399 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \ argument
4402 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \ argument
4406 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \ argument
4420 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \ argument
4423 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \ argument
4426 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \ argument
4430 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \ argument
4444 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \ argument
4447 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \ argument
4450 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \ argument
4454 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \ argument
4468 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \ argument
4471 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \ argument
4474 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \ argument
4478 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \ argument
4492 #define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \ argument
4495 #define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \ argument
4498 #define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \ argument
4502 #define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \ argument
4516 #define MAC_DCU_MISC__BKOFF_PF__READ(src) \ argument
4519 #define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \ argument
4522 #define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \ argument
4526 #define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \ argument
4540 #define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \ argument
4543 #define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \ argument
4546 #define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \ argument
4550 #define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \ argument
4558 #define MAC_DCU_MISC__IS_BCN__READ(src) \ argument
4561 #define MAC_DCU_MISC__IS_BCN__WRITE(src) \ argument
4564 #define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \ argument
4568 #define MAC_DCU_MISC__IS_BCN__VERIFY(src) \ argument
4582 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \ argument
4585 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \ argument
4588 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \ argument
4592 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \ argument
4606 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \ argument
4609 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \ argument
4612 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \ argument
4616 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \ argument
4630 #define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \ argument
4633 #define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \ argument
4636 #define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \ argument
4640 #define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \ argument
4654 #define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \ argument
4657 #define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \ argument
4660 #define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \ argument
4664 #define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \ argument
4678 #define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \ argument
4681 #define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \ argument
4684 #define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \ argument
4688 #define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \ argument
4702 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \ argument
4705 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \ argument
4708 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \ argument
4712 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \ argument
4726 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \ argument
4729 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \ argument
4732 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \ argument
4736 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \ argument
4750 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \ argument
4753 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \ argument
4756 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \ argument
4760 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \ argument
4787 #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \ argument
4807 #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \ argument
4827 #define MAC_DCU_SEQ__NUM__READ(src) (u_int32_t)(src) & 0xffffffffU argument
4828 #define MAC_DCU_SEQ__NUM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
4829 #define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \ argument
4833 #define MAC_DCU_SEQ__NUM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
4852 #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \ argument
4872 #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \ argument
4892 #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \ argument
4912 #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \ argument
4932 #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \ argument
4952 #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \ argument
4972 #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \ argument
4992 #define MAC_DCU_PAUSE__REQUEST__READ(src) (u_int32_t)(src) & 0x000003ffU argument
4993 #define MAC_DCU_PAUSE__REQUEST__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
4994 #define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \ argument
4998 #define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \ argument
5006 #define MAC_DCU_PAUSE__STATUS__READ(src) \ argument
5020 #define MAC_DCU_PAUSE__SPARE__READ(src) \ argument
5023 #define MAC_DCU_PAUSE__SPARE__WRITE(src) \ argument
5026 #define MAC_DCU_PAUSE__SPARE__MODIFY(dst, src) \ argument
5030 #define MAC_DCU_PAUSE__SPARE__VERIFY(src) \ argument
5051 #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \ argument
5071 #define MAC_DCU_WOW_KACFG__TX_EN__READ(src) (u_int32_t)(src) & 0x00000001U argument
5072 #define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
5073 #define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \ argument
5077 #define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \ argument
5091 #define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \ argument
5094 #define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \ argument
5097 #define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \ argument
5101 #define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \ argument
5115 #define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \ argument
5118 #define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \ argument
5121 #define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \ argument
5125 #define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \ argument
5133 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \ argument
5136 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \ argument
5139 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \ argument
5143 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \ argument
5164 #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \ argument
5184 #define MAC_DCU_TXSLOT__MASK__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
5185 #define MAC_DCU_TXSLOT__MASK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
5186 #define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \ argument
5190 #define MAC_DCU_TXSLOT__MASK__VERIFY(src) \ argument
5211 #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \ argument
5231 #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \ argument
5251 #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \ argument
5271 #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \ argument
5291 #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \ argument
5311 #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \ argument
5331 #define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
5332 #define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \ argument
5335 #define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \ argument
5339 #define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \ argument
5360 #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \ argument
5380 #define MAC_DCU_TXFILTER_SET__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
5381 #define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
5382 #define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \ argument
5386 #define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \ argument
5407 #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \ argument
5427 #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \ argument
5447 #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \ argument
5467 #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \ argument
5487 #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \ argument
5507 #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \ argument
5527 #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \ argument
5547 #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \ argument
5567 #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \ argument
5587 #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \ argument
5607 #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \ argument
5627 #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \ argument
5647 #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \ argument
5667 #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \ argument
5687 #define MAC_SLEEP_STATUS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
5688 #define MAC_SLEEP_STATUS__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
5689 #define MAC_SLEEP_STATUS__DATA__MODIFY(dst, src) \ argument
5693 #define MAC_SLEEP_STATUS__DATA__VERIFY(src) \ argument
5714 #define MAC_LED_CONFIG__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
5715 #define MAC_LED_CONFIG__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
5716 #define MAC_LED_CONFIG__DATA__MODIFY(dst, src) \ argument
5720 #define MAC_LED_CONFIG__DATA__VERIFY(src) \ argument
5741 #define RESET_CONTROL__MAC_WARM_RST__READ(src) (u_int32_t)(src) & 0x00000001U argument
5742 #define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \ argument
5745 #define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \ argument
5749 #define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \ argument
5763 #define RESET_CONTROL__MAC_COLD_RST__READ(src) \ argument
5766 #define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \ argument
5769 #define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \ argument
5773 #define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \ argument
5787 #define RESET_CONTROL__WARM_RST__READ(src) \ argument
5790 #define RESET_CONTROL__WARM_RST__WRITE(src) \ argument
5793 #define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \ argument
5797 #define RESET_CONTROL__WARM_RST__VERIFY(src) \ argument
5811 #define RESET_CONTROL__COLD_RST__READ(src) \ argument
5814 #define RESET_CONTROL__COLD_RST__WRITE(src) \ argument
5817 #define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \ argument
5821 #define RESET_CONTROL__COLD_RST__VERIFY(src) \ argument
5848 #define XTAL_CONTROL__TCXO__READ(src) (u_int32_t)(src) & 0x00000001U argument
5849 #define XTAL_CONTROL__TCXO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
5850 #define XTAL_CONTROL__TCXO__MODIFY(dst, src) \ argument
5854 #define XTAL_CONTROL__TCXO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
5879 #define REG_CONTROL0__SWREG_BITS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
5880 #define REG_CONTROL0__SWREG_BITS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
5881 #define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \ argument
5885 #define REG_CONTROL0__SWREG_BITS__VERIFY(src) \ argument
5906 #define REG_CONTROL1__SWREG_PROGRAM__READ(src) (u_int32_t)(src) & 0x00000001U argument
5907 #define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \ argument
5910 #define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \ argument
5914 #define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \ argument
5928 #define REG_CONTROL1__OTPREG_LVL__READ(src) \ argument
5931 #define REG_CONTROL1__OTPREG_LVL__WRITE(src) \ argument
5934 #define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \ argument
5938 #define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \ argument
5959 #define QUADRATURE__DAC__READ(src) (u_int32_t)(src) & 0x00000007U argument
5960 #define QUADRATURE__DAC__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
5961 #define QUADRATURE__DAC__MODIFY(dst, src) \ argument
5965 #define QUADRATURE__DAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) argument
5971 #define QUADRATURE__ADC__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) argument
5972 #define QUADRATURE__ADC__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) argument
5973 #define QUADRATURE__ADC__MODIFY(dst, src) \ argument
5977 #define QUADRATURE__ADC__VERIFY(src) \ argument
5998 #define PLL_CONTROL__DIV_INT__READ(src) (u_int32_t)(src) & 0x0000003fU argument
5999 #define PLL_CONTROL__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
6000 #define PLL_CONTROL__DIV_INT__MODIFY(dst, src) \ argument
6004 #define PLL_CONTROL__DIV_INT__VERIFY(src) \ argument
6012 #define PLL_CONTROL__DIV_FRAC__READ(src) \ argument
6015 #define PLL_CONTROL__DIV_FRAC__WRITE(src) \ argument
6018 #define PLL_CONTROL__DIV_FRAC__MODIFY(dst, src) \ argument
6022 #define PLL_CONTROL__DIV_FRAC__VERIFY(src) \ argument
6030 #define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x01f00000U) >> 20) argument
6031 #define PLL_CONTROL__REFDIV__WRITE(src) \ argument
6034 #define PLL_CONTROL__REFDIV__MODIFY(dst, src) \ argument
6038 #define PLL_CONTROL__REFDIV__VERIFY(src) \ argument
6046 #define PLL_CONTROL__CLK_SEL__READ(src) \ argument
6049 #define PLL_CONTROL__CLK_SEL__WRITE(src) \ argument
6052 #define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \ argument
6056 #define PLL_CONTROL__CLK_SEL__VERIFY(src) \ argument
6064 #define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
6065 #define PLL_CONTROL__BYPASS__WRITE(src) \ argument
6068 #define PLL_CONTROL__BYPASS__MODIFY(dst, src) \ argument
6072 #define PLL_CONTROL__BYPASS__VERIFY(src) \ argument
6086 #define PLL_CONTROL__UPDATING__READ(src) \ argument
6100 #define PLL_CONTROL__NOPWD__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
6101 #define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
6102 #define PLL_CONTROL__NOPWD__MODIFY(dst, src) \ argument
6106 #define PLL_CONTROL__NOPWD__VERIFY(src) \ argument
6120 #define PLL_CONTROL__MAC_OVERRIDE__READ(src) \ argument
6123 #define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \ argument
6126 #define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \ argument
6130 #define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \ argument
6157 #define PLL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x000007ffU argument
6158 #define PLL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x000007ffU) argument
6159 #define PLL_SETTLE__TIME__MODIFY(dst, src) \ argument
6163 #define PLL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x000007ffU))) argument
6182 #define XTAL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x0000007fU argument
6183 #define XTAL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) argument
6184 #define XTAL_SETTLE__TIME__MODIFY(dst, src) \ argument
6188 #define XTAL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) argument
6207 #define CLOCK_OUT__SELECT__READ(src) (u_int32_t)(src) & 0x0000000fU argument
6208 #define CLOCK_OUT__SELECT__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
6209 #define CLOCK_OUT__SELECT__MODIFY(dst, src) \ argument
6213 #define CLOCK_OUT__SELECT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) argument
6219 #define CLOCK_OUT__DELAY__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) argument
6220 #define CLOCK_OUT__DELAY__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U) argument
6221 #define CLOCK_OUT__DELAY__MODIFY(dst, src) \ argument
6225 #define CLOCK_OUT__DELAY__VERIFY(src) \ argument
6246 #define BIAS_OVERRIDE__ON__READ(src) (u_int32_t)(src) & 0x00000001U argument
6247 #define BIAS_OVERRIDE__ON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
6248 #define BIAS_OVERRIDE__ON__MODIFY(dst, src) \ argument
6252 #define BIAS_OVERRIDE__ON__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
6277 #define RESET_CAUSE__LAST__READ(src) (u_int32_t)(src) & 0x00000003U argument
6295 #define SYSTEM_SLEEP__DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
6296 #define SYSTEM_SLEEP__DISABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
6297 #define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \ argument
6301 #define SYSTEM_SLEEP__DISABLE__VERIFY(src) \ argument
6315 #define SYSTEM_SLEEP__LIGHT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
6316 #define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
6317 #define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \ argument
6321 #define SYSTEM_SLEEP__LIGHT__VERIFY(src) \ argument
6335 #define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
6360 #define MAC_SLEEP_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000003U argument
6361 #define MAC_SLEEP_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
6362 #define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \ argument
6366 #define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \ argument
6387 #define KEEP_AWAKE__COUNT__READ(src) (u_int32_t)(src) & 0x000000ffU argument
6388 #define KEEP_AWAKE__COUNT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
6389 #define KEEP_AWAKE__COUNT__MODIFY(dst, src) \ argument
6393 #define KEEP_AWAKE__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
6412 #define DERIVED_RTC_CLK__PERIOD__READ(src) \ argument
6415 #define DERIVED_RTC_CLK__PERIOD__WRITE(src) \ argument
6418 #define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \ argument
6422 #define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \ argument
6430 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \ argument
6457 #define PLL_CONTROL2__DIV_INT__READ(src) (u_int32_t)(src) & 0x00000007U argument
6458 #define PLL_CONTROL2__DIV_INT__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
6459 #define PLL_CONTROL2__DIV_INT__MODIFY(dst, src) \ argument
6463 #define PLL_CONTROL2__DIV_INT__VERIFY(src) \ argument
6471 #define PLL_CONTROL2__DIV_FRAC__READ(src) \ argument
6474 #define PLL_CONTROL2__DIV_FRAC__WRITE(src) \ argument
6477 #define PLL_CONTROL2__DIV_FRAC__MODIFY(dst, src) \ argument
6481 #define PLL_CONTROL2__DIV_FRAC__VERIFY(src) \ argument
6502 #define RTC_SYNC_RESET__RESET_L__READ(src) (u_int32_t)(src) & 0x00000001U argument
6503 #define RTC_SYNC_RESET__RESET_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
6504 #define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \ argument
6508 #define RTC_SYNC_RESET__RESET_L__VERIFY(src) \ argument
6535 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \ argument
6549 #define RTC_SYNC_STATUS__ON_STATE__READ(src) \ argument
6563 #define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \ argument
6577 #define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \ argument
6591 #define RTC_SYNC_STATUS__WRESET__READ(src) \ argument
6605 #define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \ argument
6631 #define RTC_SYNC_DERIVED__BYPASS__READ(src) (u_int32_t)(src) & 0x00000001U argument
6632 #define RTC_SYNC_DERIVED__BYPASS__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
6633 #define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \ argument
6637 #define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \ argument
6651 #define RTC_SYNC_DERIVED__FORCE__READ(src) \ argument
6654 #define RTC_SYNC_DERIVED__FORCE__WRITE(src) \ argument
6657 #define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \ argument
6661 #define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \ argument
6688 #define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
6700 #define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \ argument
6703 #define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \ argument
6706 #define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \ argument
6710 #define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \ argument
6737 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \ argument
6740 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \ argument
6743 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \ argument
6747 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \ argument
6761 #define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \ argument
6764 #define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \ argument
6767 #define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \ argument
6771 #define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \ argument
6785 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \ argument
6788 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \ argument
6791 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \ argument
6795 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \ argument
6809 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \ argument
6812 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \ argument
6815 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \ argument
6819 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \ argument
6833 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \ argument
6836 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \ argument
6839 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \ argument
6843 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \ argument
6857 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \ argument
6860 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \ argument
6863 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \ argument
6867 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \ argument
6894 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \ argument
6897 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \ argument
6900 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \ argument
6904 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \ argument
6918 #define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \ argument
6921 #define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \ argument
6924 #define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \ argument
6928 #define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \ argument
6942 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \ argument
6945 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \ argument
6948 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \ argument
6952 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \ argument
6966 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \ argument
6969 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \ argument
6972 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \ argument
6976 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \ argument
6990 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \ argument
6993 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \ argument
6996 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \ argument
7000 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \ argument
7014 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \ argument
7017 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \ argument
7020 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \ argument
7024 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \ argument
7051 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \ argument
7054 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \ argument
7057 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \ argument
7061 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \ argument
7075 #define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \ argument
7078 #define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \ argument
7081 #define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \ argument
7085 #define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \ argument
7099 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \ argument
7102 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \ argument
7105 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \ argument
7109 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \ argument
7123 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \ argument
7126 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \ argument
7129 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \ argument
7133 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \ argument
7147 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \ argument
7150 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \ argument
7153 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \ argument
7157 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \ argument
7171 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \ argument
7174 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \ argument
7177 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \ argument
7181 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \ argument
7208 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \ argument
7211 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \ argument
7214 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \ argument
7218 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \ argument
7239 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \ argument
7242 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \ argument
7245 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \ argument
7249 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \ argument
7257 #define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \ argument
7260 #define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \ argument
7263 #define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \ argument
7267 #define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \ argument
7281 #define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \ argument
7284 #define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \ argument
7287 #define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \ argument
7291 #define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \ argument
7305 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \ argument
7308 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \ argument
7311 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \ argument
7315 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \ argument
7329 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \ argument
7332 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \ argument
7335 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \ argument
7339 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \ argument
7353 #define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \ argument
7356 #define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \ argument
7359 #define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \ argument
7363 #define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \ argument
7377 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \ argument
7380 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \ argument
7383 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \ argument
7387 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \ argument
7401 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \ argument
7404 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \ argument
7407 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \ argument
7411 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \ argument
7425 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \ argument
7428 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \ argument
7431 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \ argument
7435 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \ argument
7449 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \ argument
7452 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \ argument
7455 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \ argument
7459 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \ argument
7473 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \ argument
7476 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \ argument
7479 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \ argument
7483 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \ argument
7497 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \ argument
7500 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \ argument
7503 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \ argument
7507 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \ argument
7521 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \ argument
7524 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \ argument
7527 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \ argument
7531 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \ argument
7545 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \ argument
7548 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \ argument
7551 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \ argument
7555 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \ argument
7569 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \ argument
7572 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \ argument
7575 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \ argument
7579 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \ argument
7593 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \ argument
7596 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \ argument
7599 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \ argument
7603 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \ argument
7617 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \ argument
7620 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \ argument
7623 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \ argument
7627 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \ argument
7654 #define MAC_PCU_BSSID_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU argument
7655 #define MAC_PCU_BSSID_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
7656 #define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \ argument
7660 #define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \ argument
7681 #define MAC_PCU_BSSID_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
7682 #define MAC_PCU_BSSID_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
7683 #define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \ argument
7687 #define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \ argument
7695 #define MAC_PCU_BSSID_U16__AID__READ(src) \ argument
7698 #define MAC_PCU_BSSID_U16__AID__WRITE(src) \ argument
7701 #define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \ argument
7705 #define MAC_PCU_BSSID_U16__AID__VERIFY(src) \ argument
7726 #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \ argument
7734 #define MAC_PCU_BCN_RSSI_AVE__SPARE__READ(src) \ argument
7737 #define MAC_PCU_BCN_RSSI_AVE__SPARE__WRITE(src) \ argument
7740 #define MAC_PCU_BCN_RSSI_AVE__SPARE__MODIFY(dst, src) \ argument
7744 #define MAC_PCU_BCN_RSSI_AVE__SPARE__VERIFY(src) \ argument
7765 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \ argument
7768 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \ argument
7771 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \ argument
7775 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \ argument
7783 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \ argument
7786 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \ argument
7789 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \ argument
7793 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \ argument
7814 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \ argument
7817 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \ argument
7820 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \ argument
7824 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \ argument
7832 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \ argument
7835 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \ argument
7838 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \ argument
7842 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \ argument
7850 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \ argument
7853 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \ argument
7856 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \ argument
7860 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \ argument
7868 #define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \ argument
7871 #define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \ argument
7874 #define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \ argument
7878 #define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \ argument
7905 #define MAC_PCU_USEC_LATENCY__USEC__READ(src) (u_int32_t)(src) & 0x000000ffU argument
7906 #define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
7907 #define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \ argument
7911 #define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \ argument
7919 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \ argument
7922 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \ argument
7925 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \ argument
7929 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \ argument
7937 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \ argument
7940 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \ argument
7943 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \ argument
7947 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \ argument
7968 #define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \ argument
7971 #define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \ argument
7974 #define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \ argument
7978 #define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \ argument
7992 #define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \ argument
7995 #define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \ argument
7998 #define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \ argument
8002 #define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \ argument
8029 #define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
8030 #define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
8031 #define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \ argument
8035 #define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \ argument
8043 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \ argument
8046 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \ argument
8049 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \ argument
8053 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \ argument
8061 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \ argument
8064 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \ argument
8067 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \ argument
8071 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \ argument
8092 #define MAC_PCU_RX_FILTER__UNICAST__READ(src) (u_int32_t)(src) & 0x00000001U argument
8093 #define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
8094 #define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \ argument
8098 #define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \ argument
8112 #define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \ argument
8115 #define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \ argument
8118 #define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \ argument
8122 #define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \ argument
8136 #define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \ argument
8139 #define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \ argument
8142 #define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \ argument
8146 #define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \ argument
8160 #define MAC_PCU_RX_FILTER__CONTROL__READ(src) \ argument
8163 #define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \ argument
8166 #define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \ argument
8170 #define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \ argument
8184 #define MAC_PCU_RX_FILTER__BEACON__READ(src) \ argument
8187 #define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \ argument
8190 #define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \ argument
8194 #define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \ argument
8208 #define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \ argument
8211 #define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \ argument
8214 #define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \ argument
8218 #define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \ argument
8232 #define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \ argument
8235 #define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \ argument
8238 #define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \ argument
8242 #define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \ argument
8256 #define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \ argument
8259 #define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \ argument
8262 #define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \ argument
8266 #define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \ argument
8280 #define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \ argument
8283 #define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \ argument
8286 #define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \ argument
8290 #define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \ argument
8304 #define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \ argument
8307 #define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \ argument
8310 #define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \ argument
8314 #define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \ argument
8328 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \ argument
8331 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \ argument
8334 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \ argument
8338 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \ argument
8352 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \ argument
8355 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \ argument
8358 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \ argument
8362 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \ argument
8376 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \ argument
8379 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \ argument
8382 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \ argument
8386 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \ argument
8400 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \ argument
8403 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \ argument
8406 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \ argument
8410 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \ argument
8424 #define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \ argument
8427 #define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \ argument
8430 #define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \ argument
8434 #define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \ argument
8448 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \ argument
8451 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \ argument
8454 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \ argument
8458 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \ argument
8472 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \ argument
8475 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \ argument
8478 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \ argument
8482 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \ argument
8496 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \ argument
8499 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \ argument
8502 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \ argument
8506 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \ argument
8520 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \ argument
8523 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \ argument
8526 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \ argument
8530 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \ argument
8544 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__READ(src) \ argument
8547 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__WRITE(src) \ argument
8550 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__MODIFY(dst, src) \ argument
8554 #define MAC_PCU_RX_FILTER__CONTROL_WRAPPER__VERIFY(src) \ argument
8568 #define MAC_PCU_RX_FILTER__FROM_TO_DS__READ(src) \ argument
8571 #define MAC_PCU_RX_FILTER__FROM_TO_DS__WRITE(src) \ argument
8574 #define MAC_PCU_RX_FILTER__FROM_TO_DS__MODIFY(dst, src) \ argument
8578 #define MAC_PCU_RX_FILTER__FROM_TO_DS__VERIFY(src) \ argument
8605 #define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \ argument
8608 #define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \ argument
8611 #define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \ argument
8615 #define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \ argument
8636 #define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \ argument
8639 #define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \ argument
8642 #define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \ argument
8646 #define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \ argument
8667 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \ argument
8670 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \ argument
8673 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \ argument
8677 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \ argument
8691 #define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \ argument
8694 #define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \ argument
8697 #define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \ argument
8701 #define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \ argument
8715 #define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \ argument
8718 #define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \ argument
8721 #define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \ argument
8725 #define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \ argument
8739 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \ argument
8742 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \ argument
8745 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \ argument
8749 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \ argument
8763 #define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \ argument
8766 #define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \ argument
8769 #define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \ argument
8773 #define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \ argument
8787 #define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \ argument
8790 #define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \ argument
8793 #define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \ argument
8797 #define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \ argument
8811 #define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \ argument
8814 #define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \ argument
8817 #define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \ argument
8821 #define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \ argument
8835 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \ argument
8838 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \ argument
8841 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \ argument
8845 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \ argument
8859 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \ argument
8862 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \ argument
8865 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \ argument
8869 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \ argument
8883 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \ argument
8886 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \ argument
8889 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \ argument
8893 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \ argument
8907 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \ argument
8910 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \ argument
8913 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \ argument
8917 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \ argument
8925 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \ argument
8928 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \ argument
8931 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \ argument
8935 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \ argument
8949 #define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \ argument
8952 #define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \ argument
8955 #define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \ argument
8959 #define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \ argument
8973 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \ argument
8976 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \ argument
8979 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \ argument
8983 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \ argument
8997 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \ argument
9000 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \ argument
9003 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \ argument
9007 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \ argument
9021 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \ argument
9024 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \ argument
9027 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \ argument
9031 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \ argument
9045 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \ argument
9048 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \ argument
9051 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \ argument
9055 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \ argument
9069 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \ argument
9072 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \ argument
9075 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \ argument
9079 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \ argument
9093 #define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \ argument
9096 #define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \ argument
9099 #define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \ argument
9103 #define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \ argument
9117 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \ argument
9120 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \ argument
9123 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \ argument
9127 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \ argument
9141 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \ argument
9144 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \ argument
9147 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \ argument
9151 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \ argument
9165 #define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \ argument
9168 #define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \ argument
9171 #define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \ argument
9175 #define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \ argument
9196 #define MAC_PCU_TSF_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
9197 #define MAC_PCU_TSF_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
9198 #define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \ argument
9202 #define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \ argument
9223 #define MAC_PCU_TSF_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
9224 #define MAC_PCU_TSF_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
9225 #define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \ argument
9229 #define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \ argument
9250 #define MAC_PCU_TST_ADDAC__CONT_TX__READ(src) (u_int32_t)(src) & 0x00000001U argument
9251 #define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
9252 #define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \ argument
9256 #define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \ argument
9270 #define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \ argument
9273 #define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \ argument
9276 #define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \ argument
9280 #define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \ argument
9294 #define MAC_PCU_TST_ADDAC__LOOP__READ(src) \ argument
9297 #define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \ argument
9300 #define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \ argument
9304 #define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \ argument
9318 #define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \ argument
9321 #define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \ argument
9324 #define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \ argument
9328 #define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \ argument
9336 #define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \ argument
9339 #define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \ argument
9342 #define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \ argument
9346 #define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \ argument
9360 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__READ(src) \ argument
9363 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__WRITE(src) \ argument
9366 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__MODIFY(dst, src) \ argument
9370 #define MAC_PCU_TST_ADDAC__SAMPLE_SIZE_2K__VERIFY(src) \ argument
9384 #define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \ argument
9387 #define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \ argument
9390 #define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \ argument
9394 #define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \ argument
9408 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \ argument
9411 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \ argument
9414 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \ argument
9418 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \ argument
9432 #define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \ argument
9446 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \ argument
9449 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \ argument
9452 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \ argument
9456 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \ argument
9470 #define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \ argument
9473 #define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \ argument
9476 #define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \ argument
9480 #define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \ argument
9507 #define MAC_PCU_DEF_ANTENNA__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
9508 #define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU) argument
9509 #define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \ argument
9513 #define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \ argument
9521 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \ argument
9524 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \ argument
9527 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \ argument
9531 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \ argument
9545 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \ argument
9548 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \ argument
9551 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \ argument
9555 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \ argument
9569 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \ argument
9572 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \ argument
9575 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \ argument
9579 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \ argument
9593 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \ argument
9596 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \ argument
9599 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \ argument
9603 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \ argument
9617 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \ argument
9620 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \ argument
9623 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \ argument
9627 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \ argument
9641 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \ argument
9644 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \ argument
9647 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \ argument
9651 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \ argument
9665 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__READ(src) \ argument
9668 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__WRITE(src) \ argument
9671 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__MODIFY(dst, src) \ argument
9675 #define MAC_PCU_DEF_ANTENNA__RX_ANT_EN__VERIFY(src) \ argument
9689 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__READ(src) \ argument
9692 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__WRITE(src) \ argument
9695 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__MODIFY(dst, src) \ argument
9699 #define MAC_PCU_DEF_ANTENNA__RX_ANT_DIV_ON__VERIFY(src) \ argument
9726 #define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
9727 #define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \ argument
9730 #define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \ argument
9734 #define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \ argument
9742 #define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \ argument
9745 #define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \ argument
9748 #define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \ argument
9752 #define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \ argument
9773 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
9774 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \ argument
9777 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \ argument
9781 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \ argument
9789 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \ argument
9792 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \ argument
9795 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \ argument
9799 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \ argument
9820 #define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \ argument
9823 #define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \ argument
9826 #define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \ argument
9830 #define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \ argument
9844 #define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \ argument
9847 #define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \ argument
9850 #define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \ argument
9854 #define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \ argument
9868 #define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \ argument
9871 #define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \ argument
9874 #define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \ argument
9878 #define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \ argument
9905 #define MAC_PCU_OBS_BUS_2__VALUE__READ(src) (u_int32_t)(src) & 0x0003ffffU argument
9911 #define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \ argument
9919 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \ argument
9933 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \ argument
9947 #define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \ argument
9955 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \ argument
9981 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \ argument
9995 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \ argument
10009 #define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \ argument
10023 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \ argument
10037 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \ argument
10051 #define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \ argument
10065 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \ argument
10079 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \ argument
10093 #define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \ argument
10107 #define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \ argument
10121 #define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \ argument
10135 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \ argument
10149 #define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \ argument
10157 #define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \ argument
10165 #define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \ argument
10185 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \ argument
10188 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \ argument
10191 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \ argument
10195 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \ argument
10209 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \ argument
10212 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \ argument
10215 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \ argument
10219 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \ argument
10233 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \ argument
10236 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \ argument
10239 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \ argument
10243 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \ argument
10257 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \ argument
10260 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \ argument
10263 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \ argument
10267 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \ argument
10275 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \ argument
10278 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \ argument
10281 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \ argument
10285 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \ argument
10306 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \ argument
10309 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \ argument
10312 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \ argument
10316 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \ argument
10338 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \ argument
10341 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \ argument
10344 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \ argument
10348 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \ argument
10370 #define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \ argument
10390 #define MAC_PCU_NAV__VALUE__READ(src) (u_int32_t)(src) & 0x03ffffffU argument
10391 #define MAC_PCU_NAV__VALUE__WRITE(src) ((u_int32_t)(src) & 0x03ffffffU) argument
10392 #define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \ argument
10396 #define MAC_PCU_NAV__VALUE__VERIFY(src) (!(((u_int32_t)(src) & ~0x03ffffffU))) argument
10415 #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \ argument
10435 #define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10453 #define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10471 #define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10489 #define MAC_PCU_BEACON_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10507 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \ argument
10510 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \ argument
10513 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \ argument
10517 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \ argument
10538 #define MAC_PCU_BASIC_SET__MCS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
10539 #define MAC_PCU_BASIC_SET__MCS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
10540 #define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \ argument
10544 #define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \ argument
10565 #define MAC_PCU_MGMT_SEQ__MIN__READ(src) (u_int32_t)(src) & 0x00000fffU argument
10566 #define MAC_PCU_MGMT_SEQ__MIN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) argument
10567 #define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \ argument
10571 #define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \ argument
10579 #define MAC_PCU_MGMT_SEQ__MAX__READ(src) \ argument
10582 #define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \ argument
10585 #define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \ argument
10589 #define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \ argument
10610 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \ argument
10613 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \ argument
10616 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \ argument
10620 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \ argument
10628 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \ argument
10631 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \ argument
10634 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \ argument
10638 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \ argument
10646 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \ argument
10649 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \ argument
10652 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \ argument
10656 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \ argument
10664 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \ argument
10667 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \ argument
10670 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ argument
10674 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \ argument
10682 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \ argument
10685 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \ argument
10688 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \ argument
10692 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \ argument
10713 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \ argument
10716 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \ argument
10719 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \ argument
10723 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \ argument
10744 #define MAC_PCU_TX_ANT_1__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
10745 #define MAC_PCU_TX_ANT_1__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
10746 #define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \ argument
10750 #define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \ argument
10771 #define MAC_PCU_TX_ANT_2__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
10772 #define MAC_PCU_TX_ANT_2__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
10773 #define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \ argument
10777 #define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \ argument
10798 #define MAC_PCU_TX_ANT_3__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
10799 #define MAC_PCU_TX_ANT_3__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
10800 #define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \ argument
10804 #define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \ argument
10825 #define MAC_PCU_TX_ANT_4__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
10826 #define MAC_PCU_TX_ANT_4__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
10827 #define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \ argument
10831 #define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \ argument
10852 #define MAC_PCU_XRMODE__POLL_TYPE__READ(src) (u_int32_t)(src) & 0x0000003fU argument
10853 #define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
10854 #define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \ argument
10858 #define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \ argument
10866 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \ argument
10869 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \ argument
10872 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \ argument
10876 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \ argument
10890 #define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \ argument
10893 #define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \ argument
10896 #define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \ argument
10900 #define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \ argument
10921 #define MAC_PCU_XRDEL__SLOT_DELAY__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10922 #define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
10923 #define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \ argument
10927 #define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \ argument
10935 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \ argument
10938 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \ argument
10941 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \ argument
10945 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \ argument
10966 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
10967 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \ argument
10970 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \ argument
10974 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \ argument
10982 #define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \ argument
10985 #define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \ argument
10988 #define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \ argument
10992 #define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \ argument
11013 #define MAC_PCU_XRCRP__SEND_CHIRP__READ(src) (u_int32_t)(src) & 0x00000001U argument
11014 #define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
11015 #define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \ argument
11019 #define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \ argument
11033 #define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \ argument
11036 #define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \ argument
11039 #define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \ argument
11043 #define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \ argument
11064 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U argument
11065 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \ argument
11068 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \ argument
11072 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \ argument
11086 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \ argument
11089 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \ argument
11092 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \ argument
11096 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \ argument
11110 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \ argument
11113 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \ argument
11116 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \ argument
11120 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \ argument
11134 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \ argument
11137 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \ argument
11140 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \ argument
11144 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \ argument
11158 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \ argument
11161 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \ argument
11164 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \ argument
11168 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \ argument
11182 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \ argument
11185 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \ argument
11188 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \ argument
11192 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \ argument
11206 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \ argument
11209 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \ argument
11212 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \ argument
11216 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \ argument
11224 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \ argument
11227 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \ argument
11230 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \ argument
11234 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \ argument
11255 #define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \ argument
11258 #define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \ argument
11261 #define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \ argument
11265 #define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \ argument
11279 #define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \ argument
11282 #define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \ argument
11285 #define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \ argument
11289 #define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \ argument
11310 #define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \ argument
11313 #define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \ argument
11316 #define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \ argument
11320 #define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \ argument
11341 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \ argument
11344 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \ argument
11347 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \ argument
11351 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \ argument
11359 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \ argument
11362 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \ argument
11365 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \ argument
11369 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \ argument
11377 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \ argument
11380 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \ argument
11383 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \ argument
11387 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \ argument
11414 #define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11415 #define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \ argument
11418 #define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \ argument
11422 #define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \ argument
11443 #define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
11444 #define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \ argument
11447 #define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \ argument
11451 #define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \ argument
11472 #define MAC_PCU_TPC__ACK_PWR__READ(src) (u_int32_t)(src) & 0x0000003fU argument
11473 #define MAC_PCU_TPC__ACK_PWR__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
11474 #define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \ argument
11478 #define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \ argument
11486 #define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8) argument
11487 #define MAC_PCU_TPC__CTS_PWR__WRITE(src) \ argument
11490 #define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \ argument
11494 #define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \ argument
11502 #define MAC_PCU_TPC__CHIRP_PWR__READ(src) \ argument
11505 #define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \ argument
11508 #define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \ argument
11512 #define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \ argument
11520 #define MAC_PCU_TPC__RPT_PWR__READ(src) \ argument
11523 #define MAC_PCU_TPC__RPT_PWR__WRITE(src) \ argument
11526 #define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \ argument
11530 #define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \ argument
11551 #define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11552 #define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \ argument
11555 #define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \ argument
11559 #define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \ argument
11580 #define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11581 #define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \ argument
11584 #define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \ argument
11588 #define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \ argument
11609 #define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11610 #define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \ argument
11613 #define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \ argument
11617 #define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \ argument
11638 #define MAC_PCU_CYCLE_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11639 #define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
11640 #define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \ argument
11644 #define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \ argument
11665 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \ argument
11668 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \ argument
11671 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \ argument
11675 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \ argument
11702 #define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \ argument
11705 #define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \ argument
11708 #define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \ argument
11712 #define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \ argument
11733 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \ argument
11736 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \ argument
11739 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \ argument
11743 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \ argument
11751 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \ argument
11754 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \ argument
11757 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \ argument
11761 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \ argument
11769 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \ argument
11772 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \ argument
11775 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \ argument
11779 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \ argument
11800 #define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
11801 #define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \ argument
11804 #define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \ argument
11808 #define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \ argument
11829 #define MAC_PCU_XRLAT__VALUE__READ(src) (u_int32_t)(src) & 0x00000fffU argument
11830 #define MAC_PCU_XRLAT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) argument
11831 #define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \ argument
11835 #define MAC_PCU_XRLAT__VALUE__VERIFY(src) \ argument
11856 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \ argument
11859 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \ argument
11862 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \ argument
11866 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \ argument
11874 #define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \ argument
11877 #define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \ argument
11880 #define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \ argument
11884 #define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \ argument
11911 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \ argument
11914 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \ argument
11917 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \ argument
11921 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \ argument
11929 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \ argument
11932 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \ argument
11935 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \ argument
11939 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \ argument
11947 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \ argument
11950 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \ argument
11953 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \ argument
11957 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \ argument
11965 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \ argument
11968 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \ argument
11971 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \ argument
11975 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \ argument
11983 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \ argument
11986 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \ argument
11989 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \ argument
11993 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \ argument
12001 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \ argument
12004 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \ argument
12007 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \ argument
12011 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \ argument
12019 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \ argument
12022 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \ argument
12025 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \ argument
12029 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \ argument
12037 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \ argument
12040 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \ argument
12043 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \ argument
12047 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \ argument
12055 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \ argument
12058 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \ argument
12061 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \ argument
12065 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \ argument
12092 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \ argument
12095 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \ argument
12098 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \ argument
12102 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \ argument
12110 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \ argument
12113 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \ argument
12116 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \ argument
12120 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \ argument
12128 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \ argument
12131 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \ argument
12134 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \ argument
12138 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \ argument
12146 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \ argument
12149 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \ argument
12152 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \ argument
12156 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \ argument
12164 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \ argument
12167 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \ argument
12170 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \ argument
12174 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \ argument
12182 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \ argument
12185 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \ argument
12188 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \ argument
12192 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \ argument
12200 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \ argument
12203 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \ argument
12206 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \ argument
12210 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \ argument
12218 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \ argument
12221 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \ argument
12224 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \ argument
12228 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \ argument
12249 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \ argument
12252 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \ argument
12255 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \ argument
12259 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \ argument
12273 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \ argument
12276 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \ argument
12279 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \ argument
12283 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \ argument
12297 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \ argument
12300 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \ argument
12303 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \ argument
12307 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \ argument
12321 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \ argument
12324 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \ argument
12327 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \ argument
12331 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \ argument
12345 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \ argument
12348 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \ argument
12351 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \ argument
12355 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \ argument
12369 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \ argument
12372 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \ argument
12375 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \ argument
12379 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \ argument
12393 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \ argument
12396 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \ argument
12399 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \ argument
12403 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \ argument
12417 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \ argument
12420 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \ argument
12423 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \ argument
12427 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \ argument
12441 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \ argument
12444 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \ argument
12447 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \ argument
12451 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \ argument
12465 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \ argument
12468 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \ argument
12471 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \ argument
12475 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \ argument
12489 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \ argument
12492 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \ argument
12495 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \ argument
12499 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \ argument
12513 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \ argument
12516 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \ argument
12519 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \ argument
12523 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \ argument
12537 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \ argument
12540 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \ argument
12543 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \ argument
12547 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \ argument
12561 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \ argument
12564 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \ argument
12567 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \ argument
12571 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \ argument
12585 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \ argument
12588 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \ argument
12591 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \ argument
12595 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \ argument
12609 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \ argument
12612 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \ argument
12615 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \ argument
12619 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \ argument
12633 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \ argument
12636 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \ argument
12639 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \ argument
12643 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \ argument
12657 #define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \ argument
12660 #define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \ argument
12663 #define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \ argument
12667 #define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \ argument
12681 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \ argument
12684 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \ argument
12687 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \ argument
12691 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \ argument
12705 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \ argument
12708 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \ argument
12711 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \ argument
12715 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \ argument
12729 #define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \ argument
12732 #define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \ argument
12735 #define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \ argument
12739 #define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \ argument
12753 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \ argument
12756 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \ argument
12759 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \ argument
12763 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \ argument
12777 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \ argument
12780 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \ argument
12783 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \ argument
12787 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \ argument
12801 #define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \ argument
12804 #define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \ argument
12807 #define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \ argument
12811 #define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \ argument
12832 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \ argument
12835 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \ argument
12838 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \ argument
12842 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \ argument
12863 #define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
12864 #define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \ argument
12867 #define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \ argument
12871 #define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \ argument
12892 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
12893 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \ argument
12896 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \ argument
12900 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \ argument
12921 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \ argument
12924 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \ argument
12927 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \ argument
12931 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \ argument
12952 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
12953 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \ argument
12956 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \ argument
12960 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \ argument
12981 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \ argument
12984 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \ argument
12987 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \ argument
12991 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \ argument
13012 #define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
13013 #define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \ argument
13016 #define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \ argument
13020 #define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \ argument
13041 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__READ(src) \ argument
13044 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__WRITE(src) \ argument
13047 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__MODIFY(dst, src) \ argument
13051 #define MAC_PCU_MISC_MODE4__EV_85395_FIX_DISABLE__VERIFY(src) \ argument
13065 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__READ(src) \ argument
13068 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__WRITE(src) \ argument
13071 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__MODIFY(dst, src) \ argument
13075 #define MAC_PCU_MISC_MODE4__MIN_AVAILABLE_FIFO_DEPTH__VERIFY(src) \ argument
13083 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__READ(src) \ argument
13086 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__WRITE(src) \ argument
13089 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__MODIFY(dst, src) \ argument
13093 #define MAC_PCU_MISC_MODE4__EV_83864_FIX_ENABLE__VERIFY(src) \ argument
13120 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \ argument
13123 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \ argument
13126 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \ argument
13130 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \ argument
13151 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU argument
13152 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \ argument
13155 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \ argument
13159 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \ argument
13180 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \ argument
13183 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \ argument
13186 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \ argument
13190 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \ argument
13211 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \ argument
13214 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \ argument
13217 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \ argument
13221 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \ argument
13229 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \ argument
13232 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \ argument
13235 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \ argument
13239 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \ argument
13253 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \ argument
13256 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \ argument
13259 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \ argument
13263 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \ argument
13277 #define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \ argument
13280 #define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \ argument
13283 #define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \ argument
13287 #define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \ argument
13295 #define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \ argument
13298 #define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \ argument
13301 #define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \ argument
13305 #define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \ argument
13319 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \ argument
13322 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \ argument
13325 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \ argument
13329 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \ argument
13337 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \ argument
13340 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \ argument
13343 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \ argument
13347 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \ argument
13361 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \ argument
13364 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \ argument
13367 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \ argument
13371 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \ argument
13379 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \ argument
13382 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \ argument
13385 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \ argument
13389 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \ argument
13410 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \ argument
13413 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \ argument
13416 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \ argument
13420 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \ argument
13441 #define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
13442 #define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
13443 #define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \ argument
13447 #define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \ argument
13468 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \ argument
13471 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \ argument
13474 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \ argument
13478 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \ argument
13486 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \ argument
13494 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \ argument
13497 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \ argument
13500 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \ argument
13504 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \ argument
13518 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \ argument
13521 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \ argument
13524 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \ argument
13528 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \ argument
13542 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \ argument
13545 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \ argument
13548 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \ argument
13552 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \ argument
13566 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \ argument
13569 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \ argument
13572 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \ argument
13576 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \ argument
13590 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \ argument
13593 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \ argument
13596 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \ argument
13600 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \ argument
13614 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \ argument
13617 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \ argument
13620 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \ argument
13624 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \ argument
13632 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \ argument
13635 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \ argument
13638 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \ argument
13642 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \ argument
13656 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \ argument
13659 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \ argument
13662 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \ argument
13666 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \ argument
13680 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \ argument
13683 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \ argument
13686 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \ argument
13690 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \ argument
13698 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \ argument
13701 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \ argument
13704 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \ argument
13708 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \ argument
13716 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \ argument
13719 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \ argument
13722 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \ argument
13726 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \ argument
13740 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \ argument
13743 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \ argument
13746 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \ argument
13750 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \ argument
13777 #define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
13778 #define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \ argument
13781 #define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \ argument
13785 #define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \ argument
13806 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \ argument
13809 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \ argument
13812 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \ argument
13816 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \ argument
13824 #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \ argument
13845 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \ argument
13848 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \ argument
13851 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \ argument
13855 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \ argument
13876 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \ argument
13896 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \ argument
13916 #define MAC_PCU_TXSIFS__SIFS_TIME__READ(src) (u_int32_t)(src) & 0x000000ffU argument
13917 #define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
13918 #define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \ argument
13922 #define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \ argument
13930 #define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \ argument
13933 #define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \ argument
13936 #define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \ argument
13940 #define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \ argument
13948 #define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \ argument
13951 #define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \ argument
13954 #define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \ argument
13958 #define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \ argument
13979 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \ argument
13982 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \ argument
13985 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \ argument
13989 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \ argument
13997 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \ argument
14000 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \ argument
14003 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \ argument
14007 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \ argument
14015 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \ argument
14018 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \ argument
14021 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \ argument
14025 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \ argument
14033 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \ argument
14036 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \ argument
14039 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \ argument
14043 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \ argument
14070 #define MAC_PCU_TXOP_X__VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14071 #define MAC_PCU_TXOP_X__VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
14072 #define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \ argument
14076 #define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \ argument
14097 #define MAC_PCU_TXOP_0_3__VALUE_0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14098 #define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
14099 #define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \ argument
14103 #define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \ argument
14111 #define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \ argument
14114 #define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \ argument
14117 #define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \ argument
14121 #define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \ argument
14129 #define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \ argument
14132 #define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \ argument
14135 #define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \ argument
14139 #define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \ argument
14147 #define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \ argument
14150 #define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \ argument
14153 #define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \ argument
14157 #define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \ argument
14178 #define MAC_PCU_TXOP_4_7__VALUE_4__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14179 #define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
14180 #define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \ argument
14184 #define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \ argument
14192 #define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \ argument
14195 #define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \ argument
14198 #define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \ argument
14202 #define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \ argument
14210 #define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \ argument
14213 #define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \ argument
14216 #define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \ argument
14220 #define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \ argument
14228 #define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \ argument
14231 #define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \ argument
14234 #define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \ argument
14238 #define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \ argument
14259 #define MAC_PCU_TXOP_8_11__VALUE_8__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14260 #define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
14261 #define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \ argument
14265 #define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \ argument
14273 #define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \ argument
14276 #define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \ argument
14279 #define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \ argument
14283 #define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \ argument
14291 #define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \ argument
14294 #define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \ argument
14297 #define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \ argument
14301 #define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \ argument
14309 #define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \ argument
14312 #define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \ argument
14315 #define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \ argument
14319 #define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \ argument
14340 #define MAC_PCU_TXOP_12_15__VALUE_12__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14341 #define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \ argument
14344 #define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \ argument
14348 #define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \ argument
14356 #define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \ argument
14359 #define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \ argument
14362 #define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \ argument
14366 #define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \ argument
14374 #define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \ argument
14377 #define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \ argument
14380 #define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \ argument
14384 #define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \ argument
14392 #define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \ argument
14395 #define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \ argument
14398 #define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \ argument
14402 #define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \ argument
14423 #define MAC_PCU_GENERIC_TIMERS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
14424 #define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \ argument
14427 #define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \ argument
14431 #define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \ argument
14452 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \ argument
14455 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \ argument
14458 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \ argument
14462 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \ argument
14470 #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \ argument
14478 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \ argument
14481 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \ argument
14484 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \ argument
14488 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \ argument
14509 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \ argument
14512 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \ argument
14515 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \ argument
14519 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \ argument
14527 #define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \ argument
14530 #define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \ argument
14533 #define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \ argument
14537 #define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \ argument
14551 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \ argument
14565 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \ argument
14568 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \ argument
14571 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \ argument
14575 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \ argument
14589 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \ argument
14592 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \ argument
14595 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \ argument
14599 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \ argument
14613 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \ argument
14640 #define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
14641 #define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \ argument
14644 #define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \ argument
14648 #define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \ argument
14669 #define MAC_PCU_SLP32_INC__TSF_INC__READ(src) (u_int32_t)(src) & 0x000fffffU argument
14670 #define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU) argument
14671 #define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \ argument
14675 #define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \ argument
14696 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU argument
14697 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \ argument
14700 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \ argument
14704 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \ argument
14725 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU argument
14726 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \ argument
14729 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \ argument
14733 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \ argument
14754 #define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src) (u_int32_t)(src) & 0x00000001U argument
14755 #define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
14756 #define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \ argument
14760 #define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \ argument
14774 #define MAC_PCU_SLP_MIB3__PENDING__READ(src) \ argument
14801 #define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14802 #define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \ argument
14805 #define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \ argument
14809 #define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \ argument
14817 #define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \ argument
14825 #define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \ argument
14828 #define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \ argument
14831 #define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \ argument
14835 #define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \ argument
14849 #define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \ argument
14863 #define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \ argument
14866 #define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \ argument
14869 #define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \ argument
14873 #define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \ argument
14887 #define MAC_PCU_WOW1__INTR_DETECT__READ(src) \ argument
14901 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \ argument
14915 #define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \ argument
14929 #define MAC_PCU_WOW1__CW_BITS__READ(src) \ argument
14932 #define MAC_PCU_WOW1__CW_BITS__WRITE(src) \ argument
14935 #define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \ argument
14939 #define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \ argument
14960 #define MAC_PCU_WOW2__AIFS__READ(src) (u_int32_t)(src) & 0x000000ffU argument
14961 #define MAC_PCU_WOW2__AIFS__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
14962 #define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \ argument
14966 #define MAC_PCU_WOW2__AIFS__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
14972 #define MAC_PCU_WOW2__SLOT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
14973 #define MAC_PCU_WOW2__SLOT__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
14974 #define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \ argument
14978 #define MAC_PCU_WOW2__SLOT__VERIFY(src) \ argument
14986 #define MAC_PCU_WOW2__TRY_CNT__READ(src) \ argument
14989 #define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \ argument
14992 #define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \ argument
14996 #define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \ argument
15017 #define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src) (u_int32_t)(src) & 0x00000001U argument
15018 #define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \ argument
15021 #define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \ argument
15025 #define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \ argument
15039 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \ argument
15042 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \ argument
15045 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \ argument
15049 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \ argument
15063 #define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \ argument
15077 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \ argument
15080 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \ argument
15083 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \ argument
15087 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \ argument
15101 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \ argument
15104 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \ argument
15107 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \ argument
15111 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \ argument
15119 #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \ argument
15127 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \ argument
15130 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \ argument
15133 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \ argument
15137 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \ argument
15158 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \ argument
15161 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \ argument
15164 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \ argument
15168 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \ argument
15189 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \ argument
15192 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \ argument
15195 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \ argument
15199 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \ argument
15220 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \ argument
15223 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \ argument
15226 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \ argument
15230 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \ argument
15257 #define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src) (u_int32_t)(src) & 0xffffffffU argument
15258 #define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \ argument
15261 #define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \ argument
15265 #define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \ argument
15286 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \ argument
15289 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \ argument
15292 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \ argument
15296 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \ argument
15317 #define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
15318 #define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \ argument
15321 #define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \ argument
15325 #define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \ argument
15339 #define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \ argument
15342 #define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \ argument
15345 #define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \ argument
15349 #define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \ argument
15363 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \ argument
15366 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \ argument
15369 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \ argument
15373 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \ argument
15400 #define PCU_1US__SCALER__READ(src) (u_int32_t)(src) & 0x0000007fU argument
15401 #define PCU_1US__SCALER__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) argument
15402 #define PCU_1US__SCALER__MODIFY(dst, src) \ argument
15406 #define PCU_1US__SCALER__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) argument
15425 #define PCU_KA__DEL__READ(src) (u_int32_t)(src) & 0x00000fffU argument
15426 #define PCU_KA__DEL__WRITE(src) ((u_int32_t)(src) & 0x00000fffU) argument
15427 #define PCU_KA__DEL__MODIFY(dst, src) \ argument
15431 #define PCU_KA__DEL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000fffU))) argument
15450 #define WOW_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU argument
15451 #define WOW_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
15452 #define WOW_EXACT__LENGTH__MODIFY(dst, src) \ argument
15456 #define WOW_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
15462 #define WOW_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
15463 #define WOW_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
15464 #define WOW_EXACT__OFFSET__MODIFY(dst, src) \ argument
15468 #define WOW_EXACT__OFFSET__VERIFY(src) \ argument
15489 #define PCU_WOW4__OFFSET0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
15490 #define PCU_WOW4__OFFSET0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
15491 #define PCU_WOW4__OFFSET0__MODIFY(dst, src) \ argument
15495 #define PCU_WOW4__OFFSET0__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
15501 #define PCU_WOW4__OFFSET1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
15502 #define PCU_WOW4__OFFSET1__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
15503 #define PCU_WOW4__OFFSET1__MODIFY(dst, src) \ argument
15507 #define PCU_WOW4__OFFSET1__VERIFY(src) \ argument
15515 #define PCU_WOW4__OFFSET2__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) argument
15516 #define PCU_WOW4__OFFSET2__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) argument
15517 #define PCU_WOW4__OFFSET2__MODIFY(dst, src) \ argument
15521 #define PCU_WOW4__OFFSET2__VERIFY(src) \ argument
15529 #define PCU_WOW4__OFFSET3__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) argument
15530 #define PCU_WOW4__OFFSET3__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) argument
15531 #define PCU_WOW4__OFFSET3__MODIFY(dst, src) \ argument
15535 #define PCU_WOW4__OFFSET3__VERIFY(src) \ argument
15556 #define PCU_WOW5__OFFSET4__READ(src) (u_int32_t)(src) & 0x000000ffU argument
15557 #define PCU_WOW5__OFFSET4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
15558 #define PCU_WOW5__OFFSET4__MODIFY(dst, src) \ argument
15562 #define PCU_WOW5__OFFSET4__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
15568 #define PCU_WOW5__OFFSET5__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
15569 #define PCU_WOW5__OFFSET5__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
15570 #define PCU_WOW5__OFFSET5__MODIFY(dst, src) \ argument
15574 #define PCU_WOW5__OFFSET5__VERIFY(src) \ argument
15582 #define PCU_WOW5__OFFSET6__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) argument
15583 #define PCU_WOW5__OFFSET6__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) argument
15584 #define PCU_WOW5__OFFSET6__MODIFY(dst, src) \ argument
15588 #define PCU_WOW5__OFFSET6__VERIFY(src) \ argument
15596 #define PCU_WOW5__OFFSET7__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) argument
15597 #define PCU_WOW5__OFFSET7__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) argument
15598 #define PCU_WOW5__OFFSET7__MODIFY(dst, src) \ argument
15602 #define PCU_WOW5__OFFSET7__VERIFY(src) \ argument
15623 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \ argument
15626 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \ argument
15629 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \ argument
15633 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \ argument
15641 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \ argument
15644 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \ argument
15647 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \ argument
15651 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \ argument
15659 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \ argument
15662 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \ argument
15665 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \ argument
15669 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \ argument
15690 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \ argument
15693 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \ argument
15696 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \ argument
15700 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \ argument
15714 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \ argument
15717 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \ argument
15720 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \ argument
15724 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \ argument
15738 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \ argument
15741 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \ argument
15744 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \ argument
15748 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \ argument
15762 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \ argument
15765 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \ argument
15768 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \ argument
15772 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \ argument
15786 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \ argument
15789 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \ argument
15792 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \ argument
15796 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \ argument
15810 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \ argument
15813 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \ argument
15816 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \ argument
15820 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \ argument
15834 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \ argument
15837 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \ argument
15840 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \ argument
15844 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \ argument
15858 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \ argument
15861 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \ argument
15864 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \ argument
15868 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \ argument
15882 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \ argument
15885 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \ argument
15888 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \ argument
15892 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \ argument
15906 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \ argument
15909 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \ argument
15912 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \ argument
15916 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \ argument
15930 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__READ(src) \ argument
15933 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__WRITE(src) \ argument
15936 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__MODIFY(dst, src) \ argument
15940 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE__VERIFY(src) \ argument
15954 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__READ(src) \ argument
15957 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__WRITE(src) \ argument
15960 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__MODIFY(dst, src) \ argument
15964 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX2_ENABLE__VERIFY(src) \ argument
15978 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__READ(src) \ argument
15981 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__WRITE(src) \ argument
15984 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__MODIFY(dst, src) \ argument
15988 #define MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX3_ENABLE__VERIFY(src) \ argument
16015 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \ argument
16018 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \ argument
16021 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \ argument
16025 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \ argument
16046 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \ argument
16049 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \ argument
16052 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \ argument
16056 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \ argument
16070 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \ argument
16073 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \ argument
16076 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \ argument
16080 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \ argument
16094 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \ argument
16097 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \ argument
16100 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \ argument
16104 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \ argument
16118 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \ argument
16121 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \ argument
16124 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \ argument
16128 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \ argument
16142 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \ argument
16145 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \ argument
16148 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \ argument
16152 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \ argument
16173 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU argument
16174 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \ argument
16177 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \ argument
16181 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \ argument
16189 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \ argument
16192 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \ argument
16195 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \ argument
16199 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \ argument
16213 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \ argument
16216 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \ argument
16219 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \ argument
16223 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \ argument
16237 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \ argument
16240 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \ argument
16243 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \ argument
16247 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \ argument
16261 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \ argument
16264 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \ argument
16267 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \ argument
16271 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \ argument
16298 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \ argument
16301 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \ argument
16304 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \ argument
16308 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \ argument
16329 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \ argument
16332 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \ argument
16335 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \ argument
16339 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \ argument
16347 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__READ(src) \ argument
16350 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__WRITE(src) \ argument
16353 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__MODIFY(dst, src) \ argument
16357 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__ONE_RESP_EN__VERIFY(src) \ argument
16371 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__READ(src) \ argument
16374 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__WRITE(src) \ argument
16377 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__MODIFY(dst, src) \ argument
16381 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__FORCE_CHAIN_0__VERIFY(src) \ argument
16408 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \ argument
16411 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \ argument
16414 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \ argument
16418 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \ argument
16426 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \ argument
16429 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \ argument
16432 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \ argument
16436 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \ argument
16444 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \ argument
16447 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \ argument
16450 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \ argument
16454 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \ argument
16468 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \ argument
16471 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \ argument
16474 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \ argument
16478 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \ argument
16492 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \ argument
16495 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \ argument
16498 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \ argument
16502 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \ argument
16516 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \ argument
16519 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \ argument
16522 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \ argument
16526 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \ argument
16540 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \ argument
16543 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \ argument
16546 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \ argument
16550 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \ argument
16577 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \ argument
16580 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \ argument
16583 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \ argument
16587 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \ argument
16595 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \ argument
16598 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \ argument
16601 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \ argument
16605 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \ argument
16626 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \ argument
16629 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \ argument
16632 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \ argument
16636 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \ argument
16644 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \ argument
16647 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \ argument
16650 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \ argument
16654 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \ argument
16662 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__READ(src) \ argument
16665 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__WRITE(src) \ argument
16668 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__MODIFY(dst, src) \ argument
16672 #define MAC_PCU_PHY_ERROR_MASK_CONT__AIFS_VALUE__VERIFY(src) \ argument
16693 #define MAC_PCU_TX_TIMER__TX_TIMER__READ(src) (u_int32_t)(src) & 0x00007fffU argument
16694 #define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU) argument
16695 #define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \ argument
16699 #define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \ argument
16707 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \ argument
16710 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \ argument
16713 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \ argument
16717 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \ argument
16731 #define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \ argument
16734 #define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \ argument
16737 #define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \ argument
16741 #define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \ argument
16749 #define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \ argument
16752 #define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \ argument
16755 #define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \ argument
16759 #define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \ argument
16767 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \ argument
16770 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \ argument
16773 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \ argument
16777 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \ argument
16804 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \ argument
16807 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \ argument
16810 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \ argument
16814 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \ argument
16822 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \ argument
16825 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \ argument
16828 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \ argument
16832 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \ argument
16859 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \ argument
16862 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \ argument
16865 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \ argument
16869 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \ argument
16883 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \ argument
16886 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \ argument
16889 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \ argument
16893 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \ argument
16907 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \ argument
16910 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \ argument
16913 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \ argument
16917 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \ argument
16931 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \ argument
16934 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \ argument
16937 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \ argument
16941 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \ argument
16955 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \ argument
16958 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \ argument
16961 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \ argument
16965 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \ argument
16979 #define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \ argument
16982 #define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \ argument
16985 #define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \ argument
16989 #define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \ argument
17003 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \ argument
17006 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \ argument
17009 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \ argument
17013 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \ argument
17027 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \ argument
17030 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \ argument
17033 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \ argument
17037 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \ argument
17051 #define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \ argument
17054 #define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \ argument
17057 #define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \ argument
17061 #define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \ argument
17069 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \ argument
17072 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \ argument
17075 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \ argument
17079 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \ argument
17093 #define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \ argument
17096 #define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \ argument
17099 #define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \ argument
17103 #define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \ argument
17117 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \ argument
17120 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \ argument
17123 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \ argument
17127 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \ argument
17141 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \ argument
17144 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \ argument
17147 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \ argument
17151 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \ argument
17165 #define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \ argument
17168 #define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \ argument
17171 #define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \ argument
17175 #define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \ argument
17189 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \ argument
17192 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \ argument
17195 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \ argument
17199 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \ argument
17213 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \ argument
17216 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \ argument
17219 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \ argument
17223 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \ argument
17237 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \ argument
17240 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \ argument
17243 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \ argument
17247 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \ argument
17261 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \ argument
17264 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \ argument
17267 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \ argument
17271 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \ argument
17285 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \ argument
17288 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \ argument
17291 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \ argument
17295 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \ argument
17309 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \ argument
17312 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \ argument
17315 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \ argument
17319 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \ argument
17333 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \ argument
17336 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \ argument
17339 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \ argument
17343 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \ argument
17357 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \ argument
17360 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \ argument
17363 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \ argument
17367 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \ argument
17381 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \ argument
17384 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \ argument
17387 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \ argument
17391 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \ argument
17405 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \ argument
17408 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \ argument
17411 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \ argument
17415 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \ argument
17429 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \ argument
17432 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \ argument
17435 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \ argument
17439 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \ argument
17466 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \ argument
17469 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \ argument
17472 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \ argument
17476 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \ argument
17497 #define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \ argument
17517 #define ASYNC_FIFO_REG1__DBG__READ(src) (u_int32_t)(src) & 0x3fffffffU argument
17518 #define ASYNC_FIFO_REG1__DBG__WRITE(src) ((u_int32_t)(src) & 0x3fffffffU) argument
17519 #define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \ argument
17523 #define ASYNC_FIFO_REG1__DBG__VERIFY(src) \ argument
17544 #define ASYNC_FIFO_REG2__DBG__READ(src) (u_int32_t)(src) & 0x0fffffffU argument
17545 #define ASYNC_FIFO_REG2__DBG__WRITE(src) ((u_int32_t)(src) & 0x0fffffffU) argument
17546 #define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \ argument
17550 #define ASYNC_FIFO_REG2__DBG__VERIFY(src) \ argument
17571 #define ASYNC_FIFO_REG3__DBG__READ(src) (u_int32_t)(src) & 0x000003ffU argument
17572 #define ASYNC_FIFO_REG3__DBG__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
17573 #define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \ argument
17577 #define ASYNC_FIFO_REG3__DBG__VERIFY(src) \ argument
17585 #define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \ argument
17588 #define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \ argument
17591 #define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \ argument
17595 #define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \ argument
17609 #define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \ argument
17612 #define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \ argument
17615 #define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \ argument
17619 #define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \ argument
17646 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
17647 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \ argument
17650 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \ argument
17654 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \ argument
17675 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \ argument
17678 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \ argument
17681 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \ argument
17685 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \ argument
17693 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \ argument
17696 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \ argument
17699 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \ argument
17703 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \ argument
17711 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \ argument
17714 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \ argument
17717 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \ argument
17721 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \ argument
17729 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \ argument
17732 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \ argument
17735 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \ argument
17739 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \ argument
17760 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \ argument
17763 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \ argument
17766 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \ argument
17770 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \ argument
17778 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \ argument
17781 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \ argument
17784 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \ argument
17788 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \ argument
17796 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \ argument
17799 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \ argument
17802 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \ argument
17806 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \ argument
17814 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \ argument
17817 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \ argument
17820 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \ argument
17824 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \ argument
17845 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \ argument
17848 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \ argument
17851 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \ argument
17855 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \ argument
17876 #define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU argument
17877 #define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \ argument
17880 #define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \ argument
17884 #define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \ argument
17892 #define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \ argument
17913 #define WOW2_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU argument
17914 #define WOW2_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
17915 #define WOW2_EXACT__LENGTH__MODIFY(dst, src) \ argument
17919 #define WOW2_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
17925 #define WOW2_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
17926 #define WOW2_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
17927 #define WOW2_EXACT__OFFSET__MODIFY(dst, src) \ argument
17931 #define WOW2_EXACT__OFFSET__VERIFY(src) \ argument
17952 #define PCU_WOW6__OFFSET8__READ(src) (u_int32_t)(src) & 0x000000ffU argument
17953 #define PCU_WOW6__OFFSET8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
17954 #define PCU_WOW6__OFFSET8__MODIFY(dst, src) \ argument
17958 #define PCU_WOW6__OFFSET8__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
17964 #define PCU_WOW6__OFFSET9__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
17965 #define PCU_WOW6__OFFSET9__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
17966 #define PCU_WOW6__OFFSET9__MODIFY(dst, src) \ argument
17970 #define PCU_WOW6__OFFSET9__VERIFY(src) \ argument
17978 #define PCU_WOW6__OFFSET10__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) argument
17979 #define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) argument
17980 #define PCU_WOW6__OFFSET10__MODIFY(dst, src) \ argument
17984 #define PCU_WOW6__OFFSET10__VERIFY(src) \ argument
17992 #define PCU_WOW6__OFFSET11__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) argument
17993 #define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) argument
17994 #define PCU_WOW6__OFFSET11__MODIFY(dst, src) \ argument
17998 #define PCU_WOW6__OFFSET11__VERIFY(src) \ argument
18019 #define PCU_WOW7__OFFSET12__READ(src) (u_int32_t)(src) & 0x000000ffU argument
18020 #define PCU_WOW7__OFFSET12__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
18021 #define PCU_WOW7__OFFSET12__MODIFY(dst, src) \ argument
18025 #define PCU_WOW7__OFFSET12__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
18031 #define PCU_WOW7__OFFSET13__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
18032 #define PCU_WOW7__OFFSET13__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U) argument
18033 #define PCU_WOW7__OFFSET13__MODIFY(dst, src) \ argument
18037 #define PCU_WOW7__OFFSET13__VERIFY(src) \ argument
18045 #define PCU_WOW7__OFFSET14__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) argument
18046 #define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U) argument
18047 #define PCU_WOW7__OFFSET14__MODIFY(dst, src) \ argument
18051 #define PCU_WOW7__OFFSET14__VERIFY(src) \ argument
18059 #define PCU_WOW7__OFFSET15__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) argument
18060 #define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) argument
18061 #define PCU_WOW7__OFFSET15__MODIFY(dst, src) \ argument
18065 #define PCU_WOW7__OFFSET15__VERIFY(src) \ argument
18086 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \ argument
18089 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \ argument
18092 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \ argument
18096 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \ argument
18104 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \ argument
18107 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \ argument
18110 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \ argument
18114 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \ argument
18122 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \ argument
18125 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \ argument
18128 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \ argument
18132 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \ argument
18140 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \ argument
18143 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \ argument
18146 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \ argument
18150 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \ argument
18171 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \ argument
18174 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \ argument
18177 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \ argument
18181 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \ argument
18189 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \ argument
18192 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \ argument
18195 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \ argument
18199 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \ argument
18207 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \ argument
18210 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \ argument
18213 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \ argument
18217 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \ argument
18225 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \ argument
18228 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \ argument
18231 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \ argument
18235 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \ argument
18256 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \ argument
18259 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \ argument
18262 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \ argument
18266 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \ argument
18280 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__READ(src) \ argument
18283 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__WRITE(src) \ argument
18286 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__MODIFY(dst, src) \ argument
18290 #define MAC_PCU_LOCATION_MODE_CONTROL__UPLOAD_H_DISABLE__VERIFY(src) \ argument
18317 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \ argument
18320 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \ argument
18323 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \ argument
18327 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \ argument
18348 #define MAC_PCU_TSF2_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
18349 #define MAC_PCU_TSF2_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
18350 #define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \ argument
18354 #define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \ argument
18375 #define MAC_PCU_TSF2_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU argument
18376 #define MAC_PCU_TSF2_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
18377 #define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \ argument
18381 #define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \ argument
18402 #define MAC_PCU_BSSID2_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU argument
18403 #define MAC_PCU_BSSID2_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
18404 #define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \ argument
18408 #define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \ argument
18429 #define MAC_PCU_BSSID2_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
18430 #define MAC_PCU_BSSID2_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
18431 #define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \ argument
18435 #define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \ argument
18443 #define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \ argument
18446 #define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \ argument
18449 #define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \ argument
18453 #define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \ argument
18480 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \ argument
18483 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \ argument
18486 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \ argument
18490 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \ argument
18504 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \ argument
18507 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \ argument
18510 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \ argument
18514 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \ argument
18528 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \ argument
18531 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \ argument
18534 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \ argument
18538 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \ argument
18552 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \ argument
18555 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \ argument
18558 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \ argument
18562 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \ argument
18576 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \ argument
18579 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \ argument
18582 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \ argument
18586 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \ argument
18600 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \ argument
18603 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \ argument
18606 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \ argument
18610 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \ argument
18624 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \ argument
18627 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \ argument
18630 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \ argument
18634 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \ argument
18648 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \ argument
18651 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \ argument
18654 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \ argument
18658 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \ argument
18672 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \ argument
18675 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \ argument
18678 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \ argument
18682 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \ argument
18696 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \ argument
18699 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \ argument
18702 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \ argument
18706 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \ argument
18720 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \ argument
18723 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \ argument
18726 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \ argument
18730 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \ argument
18744 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__READ(src) \ argument
18747 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__WRITE(src) \ argument
18750 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__MODIFY(dst, src) \ argument
18754 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE2_EN__VERIFY(src) \ argument
18768 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__READ(src) \ argument
18771 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__WRITE(src) \ argument
18774 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__MODIFY(dst, src) \ argument
18778 #define MAC_PCU_DIRECT_CONNECT__BC_MC_WAPI_MODE_AP_SEL__VERIFY(src) \ argument
18792 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__READ(src) \ argument
18795 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__WRITE(src) \ argument
18798 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__MODIFY(dst, src) \ argument
18802 #define MAC_PCU_DIRECT_CONNECT__DESC_SVD_TSF_SEL_EN__VERIFY(src) \ argument
18829 #define MAC_PCU_TID_TO_AC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
18830 #define MAC_PCU_TID_TO_AC__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
18831 #define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \ argument
18835 #define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \ argument
18856 #define MAC_PCU_HP_QUEUE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
18857 #define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
18858 #define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \ argument
18862 #define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \ argument
18876 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \ argument
18879 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \ argument
18882 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \ argument
18886 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \ argument
18900 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \ argument
18903 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \ argument
18906 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \ argument
18910 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \ argument
18924 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \ argument
18927 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \ argument
18930 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \ argument
18934 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \ argument
18948 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \ argument
18951 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \ argument
18954 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \ argument
18958 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \ argument
18972 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \ argument
18975 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \ argument
18978 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \ argument
18982 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \ argument
18996 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \ argument
18999 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \ argument
19002 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \ argument
19006 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \ argument
19020 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \ argument
19023 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \ argument
19026 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \ argument
19030 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \ argument
19044 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \ argument
19047 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \ argument
19050 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \ argument
19054 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \ argument
19062 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \ argument
19065 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \ argument
19068 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \ argument
19072 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \ argument
19080 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \ argument
19083 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \ argument
19086 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \ argument
19090 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \ argument
19098 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \ argument
19101 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \ argument
19104 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \ argument
19108 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \ argument
19116 #define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \ argument
19119 #define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \ argument
19122 #define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \ argument
19126 #define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \ argument
19140 #define MAC_PCU_HP_QUEUE__PM_CHANGE__READ(src) \ argument
19143 #define MAC_PCU_HP_QUEUE__PM_CHANGE__WRITE(src) \ argument
19146 #define MAC_PCU_HP_QUEUE__PM_CHANGE__MODIFY(dst, src) \ argument
19150 #define MAC_PCU_HP_QUEUE__PM_CHANGE__VERIFY(src) \ argument
19164 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__READ(src) \ argument
19167 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__WRITE(src) \ argument
19170 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__MODIFY(dst, src) \ argument
19174 #define MAC_PCU_HP_QUEUE__NON_UAPSD_EN__VERIFY(src) \ argument
19201 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \ argument
19204 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \ argument
19207 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \ argument
19211 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \ argument
19232 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \ argument
19235 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \ argument
19238 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \ argument
19242 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \ argument
19263 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \ argument
19266 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \ argument
19269 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \ argument
19273 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \ argument
19294 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \ argument
19297 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \ argument
19300 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \ argument
19304 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \ argument
19325 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \ argument
19328 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \ argument
19331 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \ argument
19335 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \ argument
19356 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \ argument
19359 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \ argument
19362 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \ argument
19366 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \ argument
19387 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \ argument
19390 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \ argument
19393 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \ argument
19397 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \ argument
19418 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \ argument
19421 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \ argument
19424 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \ argument
19428 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \ argument
19442 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \ argument
19445 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \ argument
19448 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \ argument
19452 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \ argument
19466 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \ argument
19469 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \ argument
19472 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \ argument
19476 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \ argument
19490 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \ argument
19493 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \ argument
19496 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \ argument
19500 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \ argument
19514 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \ argument
19517 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \ argument
19520 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \ argument
19524 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \ argument
19538 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \ argument
19541 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \ argument
19544 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \ argument
19548 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \ argument
19562 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \ argument
19565 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \ argument
19568 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \ argument
19572 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \ argument
19586 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \ argument
19589 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \ argument
19592 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \ argument
19596 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \ argument
19610 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \ argument
19613 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \ argument
19616 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \ argument
19620 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \ argument
19628 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \ argument
19631 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \ argument
19634 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \ argument
19638 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \ argument
19646 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \ argument
19649 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \ argument
19652 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \ argument
19656 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \ argument
19677 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \ argument
19680 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \ argument
19683 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \ argument
19687 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \ argument
19701 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \ argument
19704 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \ argument
19707 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \ argument
19711 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \ argument
19725 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \ argument
19728 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \ argument
19731 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \ argument
19735 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \ argument
19749 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \ argument
19752 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \ argument
19755 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \ argument
19759 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \ argument
19767 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \ argument
19770 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \ argument
19773 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \ argument
19777 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \ argument
19798 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \ argument
19801 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \ argument
19804 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \ argument
19808 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \ argument
19822 #define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \ argument
19825 #define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \ argument
19828 #define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \ argument
19832 #define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \ argument
19846 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \ argument
19849 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \ argument
19852 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \ argument
19856 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \ argument
19870 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \ argument
19873 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \ argument
19876 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \ argument
19880 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \ argument
19894 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \ argument
19897 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \ argument
19900 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \ argument
19904 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \ argument
19918 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \ argument
19921 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \ argument
19924 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \ argument
19928 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \ argument
19942 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \ argument
19945 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \ argument
19948 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \ argument
19952 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \ argument
19966 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \ argument
19969 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \ argument
19972 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \ argument
19976 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \ argument
19990 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \ argument
19993 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \ argument
19996 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \ argument
20000 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \ argument
20008 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \ argument
20011 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \ argument
20014 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \ argument
20018 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \ argument
20032 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \ argument
20035 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \ argument
20038 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \ argument
20042 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \ argument
20056 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \ argument
20059 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \ argument
20062 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \ argument
20066 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \ argument
20080 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__READ(src) \ argument
20083 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__WRITE(src) \ argument
20086 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__MODIFY(dst, src) \ argument
20090 #define MAC_PCU_MISC_MODE3__SELF_GEN_SMOOTHING__VERIFY(src) \ argument
20104 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__READ(src) \ argument
20107 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__WRITE(src) \ argument
20110 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__MODIFY(dst, src) \ argument
20114 #define MAC_PCU_MISC_MODE3__SMOOTHING_FORCE__VERIFY(src) \ argument
20128 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__READ(src) \ argument
20131 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__WRITE(src) \ argument
20134 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__MODIFY(dst, src) \ argument
20138 #define MAC_PCU_MISC_MODE3__KEY_MISS_FIX__VERIFY(src) \ argument
20152 #define MAC_PCU_MISC_MODE3__RESERVED1__READ(src) \ argument
20155 #define MAC_PCU_MISC_MODE3__RESERVED1__WRITE(src) \ argument
20158 #define MAC_PCU_MISC_MODE3__RESERVED1__MODIFY(dst, src) \ argument
20162 #define MAC_PCU_MISC_MODE3__RESERVED1__VERIFY(src) \ argument
20170 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__READ(src) \ argument
20173 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__WRITE(src) \ argument
20176 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__MODIFY(dst, src) \ argument
20180 #define MAC_PCU_MISC_MODE3__PHY_ERROR_AIFS_MASK_ENABLE__VERIFY(src) \ argument
20194 #define MAC_PCU_MISC_MODE3__RESERVED__READ(src) \ argument
20197 #define MAC_PCU_MISC_MODE3__RESERVED__WRITE(src) \ argument
20200 #define MAC_PCU_MISC_MODE3__RESERVED__MODIFY(dst, src) \ argument
20204 #define MAC_PCU_MISC_MODE3__RESERVED__VERIFY(src) \ argument
20212 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__READ(src) \ argument
20215 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__WRITE(src) \ argument
20218 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__MODIFY(dst, src) \ argument
20222 #define MAC_PCU_MISC_MODE3__PER_STA_WEP_ENTRY_ENABLE__VERIFY(src) \ argument
20236 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__READ(src) \ argument
20239 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__WRITE(src) \ argument
20242 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__MODIFY(dst, src) \ argument
20246 #define MAC_PCU_MISC_MODE3__BC_MC_WAPI_MODE2__VERIFY(src) \ argument
20273 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__READ(src) \ argument
20276 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__WRITE(src) \ argument
20279 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__MODIFY(dst, src) \ argument
20283 #define MAC_PCU_FILTER_RSSI_AVE__AVE_VALUE__VERIFY(src) \ argument
20291 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__READ(src) \ argument
20294 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__WRITE(src) \ argument
20297 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__MODIFY(dst, src) \ argument
20301 #define MAC_PCU_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT__VERIFY(src) \ argument
20309 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__READ(src) \ argument
20312 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__WRITE(src) \ argument
20315 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__MODIFY(dst, src) \ argument
20319 #define MAC_PCU_FILTER_RSSI_AVE__ENABLE__VERIFY(src) \ argument
20333 #define MAC_PCU_FILTER_RSSI_AVE__RESET__READ(src) \ argument
20336 #define MAC_PCU_FILTER_RSSI_AVE__RESET__WRITE(src) \ argument
20339 #define MAC_PCU_FILTER_RSSI_AVE__RESET__MODIFY(dst, src) \ argument
20343 #define MAC_PCU_FILTER_RSSI_AVE__RESET__VERIFY(src) \ argument
20370 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__READ(src) \ argument
20373 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__WRITE(src) \ argument
20376 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__MODIFY(dst, src) \ argument
20380 #define MAC_PCU_PHY_ERROR_AIFS_MASK__VALUE__VERIFY(src) \ argument
20401 #define MAC_PCU_PS_FILTER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U argument
20402 #define MAC_PCU_PS_FILTER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
20403 #define MAC_PCU_PS_FILTER__ENABLE__MODIFY(dst, src) \ argument
20407 #define MAC_PCU_PS_FILTER__ENABLE__VERIFY(src) \ argument
20421 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__READ(src) \ argument
20424 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__WRITE(src) \ argument
20427 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__MODIFY(dst, src) \ argument
20431 #define MAC_PCU_PS_FILTER__PS_SAVE_ENABLE__VERIFY(src) \ argument
20458 #define MAC_PCU_TXBUF_BA__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
20459 #define MAC_PCU_TXBUF_BA__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
20460 #define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \ argument
20464 #define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \ argument
20485 #define MAC_PCU_KEY_CACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
20486 #define MAC_PCU_KEY_CACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
20487 #define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \ argument
20491 #define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \ argument
20512 #define TIMING_CONTROLS_1__STE_THR__READ(src) (u_int32_t)(src) & 0x0000007fU argument
20513 #define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) argument
20514 #define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \ argument
20518 #define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \ argument
20526 #define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \ argument
20529 #define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \ argument
20532 #define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \ argument
20536 #define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \ argument
20544 #define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \ argument
20547 #define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \ argument
20550 #define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \ argument
20554 #define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \ argument
20562 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \ argument
20565 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \ argument
20568 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \ argument
20572 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \ argument
20586 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \ argument
20589 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \ argument
20592 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \ argument
20596 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \ argument
20604 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \ argument
20607 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \ argument
20610 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \ argument
20614 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \ argument
20622 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \ argument
20625 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \ argument
20628 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \ argument
20632 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \ argument
20646 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \ argument
20649 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \ argument
20652 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \ argument
20656 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \ argument
20670 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \ argument
20673 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \ argument
20676 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \ argument
20680 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \ argument
20694 #define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \ argument
20697 #define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \ argument
20700 #define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \ argument
20704 #define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \ argument
20712 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \ argument
20715 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \ argument
20718 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \ argument
20722 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \ argument
20736 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \ argument
20739 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \ argument
20742 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \ argument
20746 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \ argument
20760 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \ argument
20763 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \ argument
20766 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \ argument
20770 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \ argument
20778 #define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \ argument
20781 #define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \ argument
20784 #define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \ argument
20788 #define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \ argument
20815 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \ argument
20818 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \ argument
20821 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ argument
20825 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \ argument
20833 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \ argument
20836 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \ argument
20839 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \ argument
20843 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \ argument
20857 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \ argument
20860 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \ argument
20863 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \ argument
20867 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \ argument
20881 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \ argument
20884 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \ argument
20887 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \ argument
20891 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \ argument
20905 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \ argument
20908 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \ argument
20911 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \ argument
20915 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \ argument
20929 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \ argument
20932 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \ argument
20935 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \ argument
20939 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \ argument
20947 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \ argument
20950 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \ argument
20953 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \ argument
20957 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \ argument
20965 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \ argument
20968 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \ argument
20971 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \ argument
20975 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \ argument
20989 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \ argument
20992 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \ argument
20995 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \ argument
20999 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \ argument
21013 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \ argument
21016 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \ argument
21019 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \ argument
21023 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \ argument
21037 #define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \ argument
21040 #define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \ argument
21043 #define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \ argument
21047 #define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \ argument
21061 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \ argument
21064 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \ argument
21067 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \ argument
21071 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \ argument
21098 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \ argument
21101 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \ argument
21104 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \ argument
21108 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \ argument
21116 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \ argument
21119 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \ argument
21122 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \ argument
21126 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \ argument
21140 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \ argument
21143 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \ argument
21146 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \ argument
21150 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \ argument
21164 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \ argument
21167 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \ argument
21170 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \ argument
21174 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \ argument
21188 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \ argument
21191 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \ argument
21194 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \ argument
21198 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \ argument
21212 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \ argument
21215 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \ argument
21218 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \ argument
21222 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \ argument
21236 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \ argument
21239 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \ argument
21242 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \ argument
21246 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \ argument
21254 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \ argument
21257 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \ argument
21260 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \ argument
21264 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \ argument
21285 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \ argument
21288 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \ argument
21291 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \ argument
21295 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \ argument
21303 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \ argument
21306 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \ argument
21309 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \ argument
21313 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \ argument
21327 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \ argument
21330 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \ argument
21333 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \ argument
21337 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \ argument
21345 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \ argument
21348 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \ argument
21351 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \ argument
21355 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \ argument
21363 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \ argument
21366 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \ argument
21369 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \ argument
21373 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \ argument
21387 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \ argument
21390 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \ argument
21393 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \ argument
21397 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \ argument
21411 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \ argument
21414 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \ argument
21417 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \ argument
21421 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \ argument
21435 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \ argument
21438 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \ argument
21441 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \ argument
21445 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \ argument
21472 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \ argument
21475 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \ argument
21478 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \ argument
21482 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \ argument
21496 #define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \ argument
21499 #define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \ argument
21502 #define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \ argument
21506 #define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \ argument
21514 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \ argument
21517 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \ argument
21520 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \ argument
21524 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \ argument
21538 #define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \ argument
21541 #define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \ argument
21544 #define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \ argument
21548 #define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \ argument
21556 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \ argument
21559 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \ argument
21562 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \ argument
21566 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \ argument
21574 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \ argument
21577 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \ argument
21580 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \ argument
21584 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \ argument
21598 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \ argument
21601 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \ argument
21604 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \ argument
21608 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \ argument
21635 #define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \ argument
21638 #define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \ argument
21641 #define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \ argument
21645 #define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \ argument
21653 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \ argument
21656 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \ argument
21659 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \ argument
21663 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \ argument
21671 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \ argument
21674 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \ argument
21677 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \ argument
21681 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \ argument
21689 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \ argument
21692 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \ argument
21695 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \ argument
21699 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \ argument
21707 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \ argument
21710 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \ argument
21713 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \ argument
21717 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \ argument
21738 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \ argument
21741 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \ argument
21744 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \ argument
21748 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \ argument
21756 #define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \ argument
21759 #define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \ argument
21762 #define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \ argument
21766 #define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \ argument
21774 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \ argument
21777 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \ argument
21780 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \ argument
21784 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \ argument
21798 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \ argument
21801 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \ argument
21804 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \ argument
21808 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \ argument
21835 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \ argument
21838 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \ argument
21841 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \ argument
21845 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \ argument
21853 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \ argument
21856 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \ argument
21859 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \ argument
21863 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \ argument
21877 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \ argument
21880 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \ argument
21883 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \ argument
21887 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \ argument
21901 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \ argument
21904 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \ argument
21907 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \ argument
21911 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \ argument
21919 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \ argument
21922 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \ argument
21925 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \ argument
21929 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \ argument
21956 #define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src) (u_int32_t)(src) & 0x0000003fU argument
21957 #define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \ argument
21960 #define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \ argument
21964 #define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \ argument
21972 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \ argument
21975 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \ argument
21978 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \ argument
21982 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \ argument
21990 #define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \ argument
21993 #define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \ argument
21996 #define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \ argument
22000 #define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \ argument
22008 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \ argument
22011 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \ argument
22014 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \ argument
22018 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \ argument
22026 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \ argument
22029 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \ argument
22032 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \ argument
22036 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \ argument
22057 #define SFCORR__M2COUNT_THR__READ(src) (u_int32_t)(src) & 0x0000001fU argument
22058 #define SFCORR__M2COUNT_THR__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
22059 #define SFCORR__M2COUNT_THR__MODIFY(dst, src) \ argument
22063 #define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
22069 #define SFCORR__ADCSAT_THRESH__READ(src) \ argument
22072 #define SFCORR__ADCSAT_THRESH__WRITE(src) \ argument
22075 #define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \ argument
22079 #define SFCORR__ADCSAT_THRESH__VERIFY(src) \ argument
22087 #define SFCORR__ADCSAT_ICOUNT__READ(src) \ argument
22090 #define SFCORR__ADCSAT_ICOUNT__WRITE(src) \ argument
22093 #define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \ argument
22097 #define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \ argument
22105 #define SFCORR__M1_THRES__READ(src) (((u_int32_t)(src) & 0x00fe0000U) >> 17) argument
22106 #define SFCORR__M1_THRES__WRITE(src) (((u_int32_t)(src) << 17) & 0x00fe0000U) argument
22107 #define SFCORR__M1_THRES__MODIFY(dst, src) \ argument
22111 #define SFCORR__M1_THRES__VERIFY(src) \ argument
22119 #define SFCORR__M2_THRES__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) argument
22120 #define SFCORR__M2_THRES__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) argument
22121 #define SFCORR__M2_THRES__MODIFY(dst, src) \ argument
22125 #define SFCORR__M2_THRES__VERIFY(src) \ argument
22146 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \ argument
22149 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \ argument
22152 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \ argument
22156 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \ argument
22170 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \ argument
22173 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \ argument
22176 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \ argument
22180 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \ argument
22188 #define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \ argument
22191 #define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \ argument
22194 #define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \ argument
22198 #define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \ argument
22206 #define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \ argument
22209 #define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \ argument
22212 #define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \ argument
22216 #define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \ argument
22224 #define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \ argument
22227 #define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \ argument
22230 #define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \ argument
22234 #define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \ argument
22255 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \ argument
22258 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \ argument
22261 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \ argument
22265 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \ argument
22273 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \ argument
22276 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \ argument
22279 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \ argument
22283 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \ argument
22291 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \ argument
22294 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \ argument
22297 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \ argument
22301 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \ argument
22309 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \ argument
22312 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \ argument
22315 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \ argument
22319 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \ argument
22327 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \ argument
22330 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \ argument
22333 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \ argument
22337 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \ argument
22364 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \ argument
22367 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \ argument
22370 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \ argument
22374 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \ argument
22382 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \ argument
22385 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \ argument
22388 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \ argument
22392 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \ argument
22400 #define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \ argument
22421 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \ argument
22424 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \ argument
22427 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \ argument
22431 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \ argument
22445 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \ argument
22448 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \ argument
22451 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \ argument
22455 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \ argument
22463 #define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \ argument
22466 #define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \ argument
22469 #define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \ argument
22473 #define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \ argument
22481 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \ argument
22484 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \ argument
22487 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \ argument
22491 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \ argument
22499 #define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \ argument
22502 #define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \ argument
22505 #define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \ argument
22509 #define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \ argument
22517 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \ argument
22520 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \ argument
22523 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \ argument
22527 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \ argument
22535 #define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \ argument
22538 #define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \ argument
22541 #define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \ argument
22545 #define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \ argument
22572 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \ argument
22575 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \ argument
22578 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \ argument
22582 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \ argument
22590 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \ argument
22593 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \ argument
22596 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \ argument
22600 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \ argument
22608 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \ argument
22611 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \ argument
22614 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \ argument
22618 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \ argument
22632 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \ argument
22635 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \ argument
22638 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \ argument
22642 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \ argument
22656 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \ argument
22659 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \ argument
22662 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \ argument
22666 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \ argument
22680 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \ argument
22683 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \ argument
22686 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \ argument
22690 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \ argument
22698 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \ argument
22701 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \ argument
22704 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \ argument
22708 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \ argument
22722 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \ argument
22725 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \ argument
22728 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \ argument
22732 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \ argument
22746 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \ argument
22749 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \ argument
22752 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \ argument
22756 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \ argument
22764 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \ argument
22767 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \ argument
22770 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \ argument
22774 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \ argument
22801 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \ argument
22804 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \ argument
22807 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \ argument
22811 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \ argument
22819 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \ argument
22822 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \ argument
22825 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \ argument
22829 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \ argument
22843 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \ argument
22846 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \ argument
22849 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \ argument
22853 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \ argument
22861 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \ argument
22864 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \ argument
22867 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \ argument
22871 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \ argument
22879 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \ argument
22882 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \ argument
22885 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \ argument
22889 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \ argument
22916 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \ argument
22919 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \ argument
22922 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \ argument
22926 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \ argument
22940 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \ argument
22943 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \ argument
22946 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \ argument
22950 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \ argument
22958 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \ argument
22961 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \ argument
22964 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \ argument
22968 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \ argument
22982 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \ argument
22985 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \ argument
22988 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \ argument
22992 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \ argument
23006 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \ argument
23009 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \ argument
23012 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \ argument
23016 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \ argument
23024 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \ argument
23027 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \ argument
23030 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \ argument
23034 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \ argument
23042 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \ argument
23045 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \ argument
23048 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \ argument
23052 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \ argument
23079 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \ argument
23082 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \ argument
23085 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \ argument
23089 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \ argument
23097 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \ argument
23100 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \ argument
23103 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \ argument
23107 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \ argument
23115 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \ argument
23118 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \ argument
23121 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \ argument
23125 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \ argument
23146 #define TX_CRC__TX_CRC__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
23164 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \ argument
23167 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \ argument
23170 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \ argument
23174 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \ argument
23182 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \ argument
23185 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \ argument
23188 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \ argument
23192 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \ argument
23213 #define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
23219 #define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \ argument
23227 #define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \ argument
23247 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \ argument
23250 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \ argument
23253 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \ argument
23257 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \ argument
23265 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \ argument
23268 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \ argument
23271 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \ argument
23275 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \ argument
23283 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \ argument
23286 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \ argument
23289 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \ argument
23293 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \ argument
23301 #define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \ argument
23304 #define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \ argument
23307 #define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \ argument
23311 #define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \ argument
23319 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \ argument
23322 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \ argument
23325 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \ argument
23329 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \ argument
23343 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \ argument
23346 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \ argument
23349 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \ argument
23353 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \ argument
23361 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \ argument
23364 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \ argument
23367 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \ argument
23371 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \ argument
23379 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \ argument
23382 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \ argument
23385 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \ argument
23389 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \ argument
23397 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \ argument
23400 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \ argument
23403 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \ argument
23407 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \ argument
23434 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__READ(src) \ argument
23437 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__WRITE(src) \ argument
23440 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__MODIFY(dst, src) \ argument
23444 #define GREEN_TX_CONTROL_1__GREEN_TX_ENABLE__VERIFY(src) \ argument
23458 #define GREEN_TX_CONTROL_1__GREEN_CASES__READ(src) \ argument
23461 #define GREEN_TX_CONTROL_1__GREEN_CASES__WRITE(src) \ argument
23464 #define GREEN_TX_CONTROL_1__GREEN_CASES__MODIFY(dst, src) \ argument
23468 #define GREEN_TX_CONTROL_1__GREEN_CASES__VERIFY(src) \ argument
23495 #define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \ argument
23515 #define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \ argument
23535 #define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \ argument
23555 #define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \ argument
23575 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \ argument
23578 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \ argument
23581 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \ argument
23585 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \ argument
23599 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \ argument
23602 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \ argument
23605 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \ argument
23609 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \ argument
23617 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \ argument
23620 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \ argument
23623 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \ argument
23627 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \ argument
23635 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \ argument
23638 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \ argument
23641 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \ argument
23645 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \ argument
23666 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \ argument
23669 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \ argument
23672 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \ argument
23676 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \ argument
23684 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \ argument
23687 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \ argument
23690 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \ argument
23694 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \ argument
23702 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \ argument
23705 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \ argument
23708 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \ argument
23712 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \ argument
23720 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \ argument
23723 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \ argument
23726 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \ argument
23730 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \ argument
23738 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \ argument
23741 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \ argument
23744 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \ argument
23748 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \ argument
23762 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \ argument
23765 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \ argument
23768 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \ argument
23772 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \ argument
23799 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \ argument
23802 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \ argument
23805 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ argument
23809 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \ argument
23817 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \ argument
23820 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \ argument
23823 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ argument
23827 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \ argument
23835 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \ argument
23838 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \ argument
23841 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \ argument
23845 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \ argument
23859 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \ argument
23862 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \ argument
23865 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \ argument
23869 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \ argument
23877 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \ argument
23880 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \ argument
23883 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \ argument
23887 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \ argument
23895 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \ argument
23898 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \ argument
23901 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \ argument
23905 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \ argument
23932 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \ argument
23935 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \ argument
23938 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \ argument
23942 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \ argument
23963 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \ argument
23966 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \ argument
23969 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \ argument
23973 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \ argument
23994 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \ argument
23997 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \ argument
24000 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \ argument
24004 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \ argument
24025 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \ argument
24028 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \ argument
24031 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \ argument
24035 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \ argument
24049 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \ argument
24052 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \ argument
24055 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \ argument
24059 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \ argument
24073 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \ argument
24076 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \ argument
24079 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \ argument
24083 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \ argument
24091 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \ argument
24094 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \ argument
24097 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \ argument
24101 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \ argument
24122 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \ argument
24125 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \ argument
24128 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \ argument
24132 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \ argument
24146 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \ argument
24149 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \ argument
24152 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \ argument
24156 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \ argument
24170 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \ argument
24173 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \ argument
24176 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \ argument
24180 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \ argument
24194 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \ argument
24197 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \ argument
24200 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \ argument
24204 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \ argument
24212 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \ argument
24215 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \ argument
24218 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \ argument
24222 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \ argument
24230 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \ argument
24233 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \ argument
24236 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \ argument
24240 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \ argument
24248 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \ argument
24251 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \ argument
24254 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \ argument
24258 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \ argument
24285 #define PA_GAIN123_B0__PA_GAIN1_0__READ(src) (u_int32_t)(src) & 0x000003ffU argument
24286 #define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
24287 #define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \ argument
24291 #define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \ argument
24299 #define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \ argument
24302 #define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \ argument
24305 #define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \ argument
24309 #define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \ argument
24317 #define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \ argument
24320 #define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \ argument
24323 #define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \ argument
24327 #define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \ argument
24348 #define PA_GAIN45_B0__PA_GAIN4_0__READ(src) (u_int32_t)(src) & 0x000003ffU argument
24349 #define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
24350 #define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \ argument
24354 #define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \ argument
24362 #define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \ argument
24365 #define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \ argument
24368 #define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \ argument
24372 #define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \ argument
24380 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \ argument
24383 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \ argument
24386 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \ argument
24390 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \ argument
24411 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \ argument
24414 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \ argument
24417 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \ argument
24421 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \ argument
24442 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \ argument
24445 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \ argument
24448 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \ argument
24452 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \ argument
24473 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \ argument
24476 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \ argument
24479 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \ argument
24483 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \ argument
24504 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \ argument
24507 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \ argument
24510 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \ argument
24514 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \ argument
24535 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \ argument
24538 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \ argument
24541 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \ argument
24545 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \ argument
24566 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \ argument
24569 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \ argument
24572 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \ argument
24576 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \ argument
24597 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \ argument
24600 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \ argument
24603 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \ argument
24607 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \ argument
24628 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \ argument
24631 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \ argument
24634 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \ argument
24638 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \ argument
24659 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU argument
24660 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) argument
24661 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ argument
24665 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ argument
24686 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ argument
24706 #define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__READ(src) \ argument
24709 #define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__WRITE(src) \ argument
24712 #define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__MODIFY(dst, src) \ argument
24716 #define CHN_TABLES_INTF_ADDR__CHN_TABLES_ADDR__VERIFY(src) \ argument
24724 #define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__READ(src) \ argument
24727 #define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__WRITE(src) \ argument
24730 #define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__MODIFY(dst, src) \ argument
24734 #define CHN_TABLES_INTF_ADDR__CHN_ADDR_AUTO_INCR__VERIFY(src) \ argument
24761 #define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__READ(src) \ argument
24764 #define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__WRITE(src) \ argument
24767 #define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__MODIFY(dst, src) \ argument
24771 #define CHN_TABLES_INTF_DATA__CHN_TABLES_DATA__VERIFY(src) \ argument
24792 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \ argument
24795 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \ argument
24798 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \ argument
24802 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \ argument
24810 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \ argument
24813 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \ argument
24816 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \ argument
24820 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \ argument
24847 #define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
24848 #define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \ argument
24851 #define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \ argument
24855 #define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \ argument
24876 #define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
24877 #define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \ argument
24880 #define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \ argument
24884 #define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \ argument
24892 #define LDPC_CNTL2__LDPC_LATENCY__READ(src) \ argument
24895 #define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \ argument
24898 #define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \ argument
24902 #define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \ argument
24923 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \ argument
24926 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \ argument
24929 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \ argument
24933 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \ argument
24941 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \ argument
24944 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \ argument
24947 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \ argument
24951 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \ argument
24959 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \ argument
24962 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \ argument
24965 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \ argument
24969 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \ argument
24977 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \ argument
24980 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \ argument
24983 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \ argument
24987 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \ argument
25008 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \ argument
25011 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \ argument
25014 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \ argument
25018 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \ argument
25026 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \ argument
25029 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \ argument
25032 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \ argument
25036 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \ argument
25044 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \ argument
25047 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \ argument
25050 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \ argument
25054 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \ argument
25062 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \ argument
25065 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \ argument
25068 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \ argument
25072 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \ argument
25093 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \ argument
25096 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \ argument
25099 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \ argument
25103 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \ argument
25111 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \ argument
25114 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \ argument
25117 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \ argument
25121 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \ argument
25142 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \ argument
25145 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \ argument
25148 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \ argument
25152 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \ argument
25160 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \ argument
25163 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \ argument
25166 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \ argument
25170 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \ argument
25178 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \ argument
25181 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \ argument
25184 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \ argument
25188 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \ argument
25209 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \ argument
25212 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \ argument
25215 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \ argument
25219 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \ argument
25240 #define TSTADC__TSTADC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU argument
25246 #define TSTADC__TSTADC_OUT_I__READ(src) \ argument
25266 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \ argument
25269 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \ argument
25272 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \ argument
25276 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \ argument
25284 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \ argument
25287 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \ argument
25290 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \ argument
25294 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \ argument
25302 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \ argument
25305 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \ argument
25308 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \ argument
25312 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \ argument
25320 #define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \ argument
25323 #define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \ argument
25326 #define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \ argument
25330 #define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \ argument
25338 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \ argument
25341 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \ argument
25344 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \ argument
25348 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \ argument
25356 #define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \ argument
25359 #define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \ argument
25362 #define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \ argument
25366 #define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \ argument
25374 #define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \ argument
25377 #define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \ argument
25380 #define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \ argument
25384 #define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \ argument
25392 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \ argument
25395 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \ argument
25398 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \ argument
25402 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \ argument
25429 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \ argument
25432 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \ argument
25435 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \ argument
25439 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \ argument
25447 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \ argument
25450 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \ argument
25453 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \ argument
25457 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \ argument
25465 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \ argument
25468 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \ argument
25471 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \ argument
25475 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \ argument
25483 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \ argument
25486 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \ argument
25489 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \ argument
25493 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \ argument
25501 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \ argument
25504 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \ argument
25507 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \ argument
25511 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \ argument
25519 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \ argument
25522 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \ argument
25525 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \ argument
25529 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \ argument
25550 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \ argument
25553 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \ argument
25556 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \ argument
25560 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \ argument
25568 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \ argument
25571 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \ argument
25574 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \ argument
25578 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \ argument
25586 #define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \ argument
25589 #define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \ argument
25592 #define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \ argument
25596 #define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \ argument
25617 #define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src) (u_int32_t)(src) & 0x0000000fU argument
25618 #define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \ argument
25621 #define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \ argument
25625 #define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \ argument
25633 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \ argument
25636 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \ argument
25639 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \ argument
25643 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \ argument
25651 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \ argument
25654 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \ argument
25657 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \ argument
25661 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \ argument
25675 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \ argument
25678 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \ argument
25681 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \ argument
25685 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \ argument
25699 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \ argument
25702 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \ argument
25705 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \ argument
25709 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \ argument
25723 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \ argument
25726 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \ argument
25729 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \ argument
25733 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \ argument
25741 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \ argument
25744 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \ argument
25747 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \ argument
25751 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \ argument
25759 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \ argument
25762 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \ argument
25765 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \ argument
25769 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \ argument
25796 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \ argument
25799 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \ argument
25802 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \ argument
25806 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \ argument
25814 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \ argument
25817 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \ argument
25820 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \ argument
25824 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \ argument
25832 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \ argument
25835 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \ argument
25838 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \ argument
25842 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \ argument
25850 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \ argument
25853 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \ argument
25856 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \ argument
25860 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \ argument
25868 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \ argument
25871 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \ argument
25874 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \ argument
25878 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \ argument
25899 #define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \ argument
25902 #define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \ argument
25905 #define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \ argument
25909 #define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \ argument
25917 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \ argument
25920 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \ argument
25923 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \ argument
25927 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \ argument
25941 #define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \ argument
25944 #define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \ argument
25947 #define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \ argument
25951 #define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \ argument
25959 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \ argument
25962 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \ argument
25965 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \ argument
25969 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \ argument
25983 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \ argument
25986 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \ argument
25989 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \ argument
25993 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \ argument
26007 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \ argument
26010 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \ argument
26013 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \ argument
26017 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \ argument
26031 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \ argument
26034 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \ argument
26037 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \ argument
26041 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \ argument
26055 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \ argument
26058 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \ argument
26061 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \ argument
26065 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \ argument
26092 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \ argument
26095 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \ argument
26098 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \ argument
26102 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \ argument
26116 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \ argument
26119 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \ argument
26122 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \ argument
26126 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \ argument
26140 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \ argument
26143 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \ argument
26146 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \ argument
26150 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \ argument
26164 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \ argument
26167 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \ argument
26170 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \ argument
26174 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \ argument
26188 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \ argument
26191 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \ argument
26194 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \ argument
26198 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \ argument
26212 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \ argument
26215 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \ argument
26218 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \ argument
26222 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \ argument
26249 #define SETTLING_TIME__AGC_SETTLING__READ(src) (u_int32_t)(src) & 0x0000007fU argument
26250 #define SETTLING_TIME__AGC_SETTLING__WRITE(src) \ argument
26253 #define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \ argument
26257 #define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \ argument
26265 #define SETTLING_TIME__SWITCH_SETTLING__READ(src) \ argument
26268 #define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \ argument
26271 #define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \ argument
26275 #define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \ argument
26283 #define SETTLING_TIME__ADCSAT_THRL__READ(src) \ argument
26286 #define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \ argument
26289 #define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \ argument
26293 #define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \ argument
26301 #define SETTLING_TIME__ADCSAT_THRH__READ(src) \ argument
26304 #define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \ argument
26307 #define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \ argument
26311 #define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \ argument
26319 #define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \ argument
26322 #define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \ argument
26325 #define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \ argument
26329 #define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \ argument
26350 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \ argument
26353 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \ argument
26356 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \ argument
26360 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \ argument
26368 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \ argument
26371 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \ argument
26374 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \ argument
26378 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \ argument
26386 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \ argument
26389 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \ argument
26392 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \ argument
26396 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \ argument
26410 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \ argument
26413 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \ argument
26416 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \ argument
26420 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \ argument
26434 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \ argument
26437 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \ argument
26440 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \ argument
26444 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \ argument
26452 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \ argument
26455 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \ argument
26458 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \ argument
26462 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \ argument
26483 #define GAINS_MIN_OFFSETS__OFFSETC1__READ(src) (u_int32_t)(src) & 0x0000007fU argument
26484 #define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \ argument
26487 #define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \ argument
26491 #define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \ argument
26499 #define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \ argument
26502 #define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \ argument
26505 #define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \ argument
26509 #define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \ argument
26517 #define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \ argument
26520 #define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \ argument
26523 #define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \ argument
26527 #define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \ argument
26535 #define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \ argument
26538 #define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \ argument
26541 #define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \ argument
26545 #define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \ argument
26559 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \ argument
26562 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \ argument
26565 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \ argument
26569 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \ argument
26583 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \ argument
26586 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \ argument
26589 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \ argument
26593 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \ argument
26607 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \ argument
26610 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \ argument
26613 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \ argument
26617 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \ argument
26631 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \ argument
26634 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \ argument
26637 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \ argument
26641 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \ argument
26668 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \ argument
26671 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \ argument
26674 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \ argument
26678 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \ argument
26686 #define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \ argument
26689 #define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \ argument
26692 #define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \ argument
26696 #define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \ argument
26704 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \ argument
26707 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \ argument
26710 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \ argument
26714 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \ argument
26722 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \ argument
26725 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \ argument
26728 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \ argument
26732 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \ argument
26746 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \ argument
26749 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \ argument
26752 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \ argument
26756 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \ argument
26783 #define FIND_SIGNAL__RELSTEP__READ(src) (u_int32_t)(src) & 0x0000003fU argument
26784 #define FIND_SIGNAL__RELSTEP__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
26785 #define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \ argument
26789 #define FIND_SIGNAL__RELSTEP__VERIFY(src) \ argument
26797 #define FIND_SIGNAL__RELPWR__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) argument
26798 #define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U) argument
26799 #define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \ argument
26803 #define FIND_SIGNAL__RELPWR__VERIFY(src) \ argument
26811 #define FIND_SIGNAL__FIRSTEP__READ(src) \ argument
26814 #define FIND_SIGNAL__FIRSTEP__WRITE(src) \ argument
26817 #define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \ argument
26821 #define FIND_SIGNAL__FIRSTEP__VERIFY(src) \ argument
26829 #define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) argument
26830 #define FIND_SIGNAL__FIRPWR__WRITE(src) \ argument
26833 #define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \ argument
26837 #define FIND_SIGNAL__FIRPWR__VERIFY(src) \ argument
26845 #define FIND_SIGNAL__M1COUNT_MAX__READ(src) \ argument
26848 #define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \ argument
26851 #define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \ argument
26855 #define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \ argument
26876 #define AGC__COARSEPWR_CONST__READ(src) (u_int32_t)(src) & 0x0000007fU argument
26877 #define AGC__COARSEPWR_CONST__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) argument
26878 #define AGC__COARSEPWR_CONST__MODIFY(dst, src) \ argument
26882 #define AGC__COARSEPWR_CONST__VERIFY(src) \ argument
26890 #define AGC__COARSE_LOW__READ(src) (((u_int32_t)(src) & 0x00007f80U) >> 7) argument
26891 #define AGC__COARSE_LOW__WRITE(src) (((u_int32_t)(src) << 7) & 0x00007f80U) argument
26892 #define AGC__COARSE_LOW__MODIFY(dst, src) \ argument
26896 #define AGC__COARSE_LOW__VERIFY(src) \ argument
26904 #define AGC__COARSE_HIGH__READ(src) (((u_int32_t)(src) & 0x003f8000U) >> 15) argument
26905 #define AGC__COARSE_HIGH__WRITE(src) (((u_int32_t)(src) << 15) & 0x003f8000U) argument
26906 #define AGC__COARSE_HIGH__MODIFY(dst, src) \ argument
26910 #define AGC__COARSE_HIGH__VERIFY(src) \ argument
26918 #define AGC__QUICK_DROP__READ(src) (((u_int32_t)(src) & 0x3fc00000U) >> 22) argument
26919 #define AGC__QUICK_DROP__WRITE(src) (((u_int32_t)(src) << 22) & 0x3fc00000U) argument
26920 #define AGC__QUICK_DROP__MODIFY(dst, src) \ argument
26924 #define AGC__QUICK_DROP__VERIFY(src) \ argument
26932 #define AGC__RSSI_OUT_SELECT__READ(src) \ argument
26935 #define AGC__RSSI_OUT_SELECT__WRITE(src) \ argument
26938 #define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \ argument
26942 #define AGC__RSSI_OUT_SELECT__VERIFY(src) \ argument
26963 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \ argument
26966 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \ argument
26969 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \ argument
26973 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \ argument
26981 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \ argument
26984 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \ argument
26987 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \ argument
26991 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \ argument
26999 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \ argument
27002 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \ argument
27005 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \ argument
27009 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \ argument
27017 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \ argument
27020 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \ argument
27023 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \ argument
27027 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \ argument
27035 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \ argument
27038 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \ argument
27041 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \ argument
27045 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \ argument
27066 #define CCA_B0__CF_MAXCCAPWR_0__READ(src) (u_int32_t)(src) & 0x000001ffU argument
27067 #define CCA_B0__CF_MAXCCAPWR_0__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) argument
27068 #define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \ argument
27072 #define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \ argument
27080 #define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \ argument
27083 #define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \ argument
27086 #define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \ argument
27090 #define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \ argument
27098 #define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12) argument
27099 #define CCA_B0__CF_THRESH62__WRITE(src) \ argument
27102 #define CCA_B0__CF_THRESH62__MODIFY(dst, src) \ argument
27106 #define CCA_B0__CF_THRESH62__VERIFY(src) \ argument
27114 #define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) argument
27133 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \ argument
27136 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \ argument
27139 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \ argument
27143 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \ argument
27151 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \ argument
27154 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \ argument
27157 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \ argument
27161 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \ argument
27175 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \ argument
27178 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \ argument
27181 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \ argument
27185 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \ argument
27193 #define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \ argument
27196 #define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \ argument
27199 #define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \ argument
27203 #define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \ argument
27230 #define RESTART__ENABLE_RESTART__READ(src) (u_int32_t)(src) & 0x00000001U argument
27231 #define RESTART__ENABLE_RESTART__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
27232 #define RESTART__ENABLE_RESTART__MODIFY(dst, src) \ argument
27236 #define RESTART__ENABLE_RESTART__VERIFY(src) \ argument
27250 #define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \ argument
27253 #define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \ argument
27256 #define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \ argument
27260 #define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \ argument
27268 #define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \ argument
27271 #define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \ argument
27274 #define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \ argument
27278 #define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \ argument
27292 #define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \ argument
27295 #define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \ argument
27298 #define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \ argument
27302 #define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \ argument
27310 #define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \ argument
27313 #define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \ argument
27316 #define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \ argument
27320 #define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \ argument
27328 #define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \ argument
27331 #define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \ argument
27334 #define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \ argument
27338 #define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \ argument
27346 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \ argument
27349 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \ argument
27352 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \ argument
27356 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \ argument
27370 #define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \ argument
27373 #define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \ argument
27376 #define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \ argument
27380 #define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \ argument
27388 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \ argument
27391 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \ argument
27394 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \ argument
27398 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \ argument
27412 #define RESTART__DISABLE_DC_RESTART__READ(src) \ argument
27415 #define RESTART__DISABLE_DC_RESTART__WRITE(src) \ argument
27418 #define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \ argument
27422 #define RESTART__DISABLE_DC_RESTART__VERIFY(src) \ argument
27436 #define RESTART__RESTART_MODE_BW40__READ(src) \ argument
27439 #define RESTART__RESTART_MODE_BW40__WRITE(src) \ argument
27442 #define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \ argument
27446 #define RESTART__RESTART_MODE_BW40__VERIFY(src) \ argument
27473 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \ argument
27476 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \ argument
27479 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \ argument
27483 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \ argument
27491 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \ argument
27494 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \ argument
27497 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \ argument
27501 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \ argument
27515 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \ argument
27518 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \ argument
27521 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \ argument
27525 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \ argument
27533 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \ argument
27536 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \ argument
27539 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \ argument
27543 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \ argument
27551 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \ argument
27554 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \ argument
27557 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \ argument
27561 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \ argument
27575 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \ argument
27578 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \ argument
27581 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \ argument
27585 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \ argument
27599 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \ argument
27602 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \ argument
27605 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \ argument
27609 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \ argument
27623 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \ argument
27626 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \ argument
27629 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \ argument
27633 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \ argument
27647 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \ argument
27650 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \ argument
27653 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \ argument
27657 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \ argument
27665 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \ argument
27668 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \ argument
27671 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \ argument
27675 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \ argument
27683 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \ argument
27686 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \ argument
27689 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \ argument
27693 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \ argument
27707 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \ argument
27710 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \ argument
27713 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \ argument
27717 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \ argument
27731 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__READ(src) \ argument
27734 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__WRITE(src) \ argument
27737 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__MODIFY(dst, src) \ argument
27741 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_SW_COM_LOCK__VERIFY(src) \ argument
27768 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \ argument
27771 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \ argument
27774 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \ argument
27778 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \ argument
27786 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \ argument
27789 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \ argument
27792 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \ argument
27796 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \ argument
27804 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \ argument
27807 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \ argument
27810 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \ argument
27814 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \ argument
27822 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \ argument
27825 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \ argument
27828 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \ argument
27832 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \ argument
27853 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \ argument
27856 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \ argument
27859 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \ argument
27863 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \ argument
27871 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \ argument
27874 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \ argument
27877 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \ argument
27881 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \ argument
27889 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \ argument
27892 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \ argument
27895 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \ argument
27899 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \ argument
27907 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \ argument
27910 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \ argument
27913 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \ argument
27917 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \ argument
27925 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \ argument
27928 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \ argument
27931 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \ argument
27935 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \ argument
27943 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \ argument
27946 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \ argument
27949 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \ argument
27953 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \ argument
27961 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \ argument
27964 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \ argument
27967 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \ argument
27971 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \ argument
27992 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \ argument
27995 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \ argument
27998 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \ argument
28002 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \ argument
28010 #define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \ argument
28013 #define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \ argument
28016 #define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \ argument
28020 #define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \ argument
28028 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \ argument
28031 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \ argument
28034 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \ argument
28038 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \ argument
28046 #define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \ argument
28049 #define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \ argument
28052 #define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \ argument
28056 #define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \ argument
28064 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \ argument
28067 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \ argument
28070 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \ argument
28074 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \ argument
28082 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \ argument
28085 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \ argument
28088 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \ argument
28092 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \ argument
28106 #define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \ argument
28109 #define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \ argument
28112 #define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \ argument
28116 #define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \ argument
28143 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \ argument
28146 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \ argument
28149 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \ argument
28153 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \ argument
28161 #define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \ argument
28164 #define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \ argument
28167 #define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \ argument
28171 #define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \ argument
28179 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \ argument
28182 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \ argument
28185 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \ argument
28189 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \ argument
28203 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \ argument
28206 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \ argument
28209 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \ argument
28213 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \ argument
28240 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \ argument
28243 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \ argument
28246 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \ argument
28250 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \ argument
28264 #define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \ argument
28267 #define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \ argument
28270 #define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \ argument
28274 #define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \ argument
28288 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \ argument
28291 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \ argument
28294 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \ argument
28298 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \ argument
28306 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__READ(src) \ argument
28309 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__WRITE(src) \ argument
28312 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__MODIFY(dst, src) \ argument
28316 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW_0__VERIFY(src) \ argument
28324 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__READ(src) \ argument
28327 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__WRITE(src) \ argument
28330 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__MODIFY(dst, src) \ argument
28334 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED_0__VERIFY(src) \ argument
28342 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__READ(src) \ argument
28345 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__WRITE(src) \ argument
28348 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__MODIFY(dst, src) \ argument
28352 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH_0__VERIFY(src) \ argument
28360 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \ argument
28363 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \ argument
28366 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \ argument
28370 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \ argument
28378 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \ argument
28381 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \ argument
28384 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \ argument
28388 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \ argument
28402 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \ argument
28405 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \ argument
28408 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \ argument
28412 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \ argument
28439 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \ argument
28442 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \ argument
28445 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \ argument
28449 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \ argument
28457 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__READ(src) \ argument
28460 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__WRITE(src) \ argument
28463 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__MODIFY(dst, src) \ argument
28467 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW_0__VERIFY(src) \ argument
28475 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__READ(src) \ argument
28478 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__WRITE(src) \ argument
28481 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__MODIFY(dst, src) \ argument
28485 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED_0__VERIFY(src) \ argument
28493 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__READ(src) \ argument
28496 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__WRITE(src) \ argument
28499 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__MODIFY(dst, src) \ argument
28503 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH_0__VERIFY(src) \ argument
28511 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__READ(src) \ argument
28514 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__WRITE(src) \ argument
28517 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__MODIFY(dst, src) \ argument
28521 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON_0__VERIFY(src) \ argument
28529 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__READ(src) \ argument
28532 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__WRITE(src) \ argument
28535 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \ argument
28539 #define PEAK_DET_CTRL_2__ENABLE_RFSAT_RESTART__VERIFY(src) \ argument
28566 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \ argument
28569 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \ argument
28572 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \ argument
28576 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \ argument
28584 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \ argument
28587 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \ argument
28590 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \ argument
28594 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \ argument
28602 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \ argument
28605 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \ argument
28608 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \ argument
28612 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \ argument
28620 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \ argument
28623 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \ argument
28626 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \ argument
28630 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \ argument
28644 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \ argument
28647 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \ argument
28650 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \ argument
28654 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \ argument
28668 #define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__READ(src) \ argument
28671 #define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__WRITE(src) \ argument
28674 #define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__MODIFY(dst, src) \ argument
28678 #define RX_GAIN_BOUNDS_1__RF_MB_GAIN_DELTA_MAX_DB__VERIFY(src) \ argument
28699 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \ argument
28702 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \ argument
28705 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \ argument
28709 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \ argument
28717 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \ argument
28720 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \ argument
28723 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \ argument
28727 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \ argument
28735 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \ argument
28738 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \ argument
28741 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \ argument
28745 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \ argument
28753 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \ argument
28756 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \ argument
28759 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \ argument
28763 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \ argument
28784 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \ argument
28787 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \ argument
28790 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \ argument
28794 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \ argument
28802 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \ argument
28805 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \ argument
28808 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \ argument
28812 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \ argument
28820 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \ argument
28823 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \ argument
28826 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \ argument
28830 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \ argument
28851 #define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src) (u_int32_t)(src) & 0x00000001U argument
28852 #define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \ argument
28855 #define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \ argument
28859 #define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \ argument
28873 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \ argument
28876 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \ argument
28879 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \ argument
28883 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \ argument
28891 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \ argument
28894 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \ argument
28897 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \ argument
28901 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \ argument
28909 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \ argument
28912 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \ argument
28915 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \ argument
28919 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \ argument
28933 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \ argument
28936 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \ argument
28939 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \ argument
28943 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \ argument
28964 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__READ(src) \ argument
28967 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__WRITE(src) \ argument
28970 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__MODIFY(dst, src) \ argument
28974 #define BT_COEX_1__PEAK_DET_TALLY_THR_LOW_1__VERIFY(src) \ argument
28982 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__READ(src) \ argument
28985 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__WRITE(src) \ argument
28988 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__MODIFY(dst, src) \ argument
28992 #define BT_COEX_1__PEAK_DET_TALLY_THR_MED_1__VERIFY(src) \ argument
29000 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__READ(src) \ argument
29003 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__WRITE(src) \ argument
29006 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__MODIFY(dst, src) \ argument
29010 #define BT_COEX_1__PEAK_DET_TALLY_THR_HIGH_1__VERIFY(src) \ argument
29018 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__READ(src) \ argument
29021 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__WRITE(src) \ argument
29024 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__MODIFY(dst, src) \ argument
29028 #define BT_COEX_1__RF_GAIN_DROP_DB_LOW_1__VERIFY(src) \ argument
29036 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__READ(src) \ argument
29039 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__WRITE(src) \ argument
29042 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__MODIFY(dst, src) \ argument
29046 #define BT_COEX_1__RF_GAIN_DROP_DB_MED_1__VERIFY(src) \ argument
29054 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__READ(src) \ argument
29057 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__WRITE(src) \ argument
29060 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__MODIFY(dst, src) \ argument
29064 #define BT_COEX_1__RF_GAIN_DROP_DB_HIGH_1__VERIFY(src) \ argument
29072 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__READ(src) \ argument
29075 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__WRITE(src) \ argument
29078 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__MODIFY(dst, src) \ argument
29082 #define BT_COEX_1__BT_TX_DISABLE_NF_CAL__VERIFY(src) \ argument
29096 #define BT_COEX_1__BT_RX_DISABLE_NF_CAL__READ(src) \ argument
29099 #define BT_COEX_1__BT_RX_DISABLE_NF_CAL__WRITE(src) \ argument
29102 #define BT_COEX_1__BT_RX_DISABLE_NF_CAL__MODIFY(dst, src) \ argument
29106 #define BT_COEX_1__BT_RX_DISABLE_NF_CAL__VERIFY(src) \ argument
29133 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__READ(src) \ argument
29136 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__WRITE(src) \ argument
29139 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__MODIFY(dst, src) \ argument
29143 #define BT_COEX_2__PEAK_DET_TALLY_THR_LOW_2__VERIFY(src) \ argument
29151 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__READ(src) \ argument
29154 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__WRITE(src) \ argument
29157 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__MODIFY(dst, src) \ argument
29161 #define BT_COEX_2__PEAK_DET_TALLY_THR_MED_2__VERIFY(src) \ argument
29169 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__READ(src) \ argument
29172 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__WRITE(src) \ argument
29175 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__MODIFY(dst, src) \ argument
29179 #define BT_COEX_2__PEAK_DET_TALLY_THR_HIGH_2__VERIFY(src) \ argument
29187 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__READ(src) \ argument
29190 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__WRITE(src) \ argument
29193 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__MODIFY(dst, src) \ argument
29197 #define BT_COEX_2__RF_GAIN_DROP_DB_LOW_2__VERIFY(src) \ argument
29205 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__READ(src) \ argument
29208 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__WRITE(src) \ argument
29211 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__MODIFY(dst, src) \ argument
29215 #define BT_COEX_2__RF_GAIN_DROP_DB_MED_2__VERIFY(src) \ argument
29223 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__READ(src) \ argument
29226 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__WRITE(src) \ argument
29229 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__MODIFY(dst, src) \ argument
29233 #define BT_COEX_2__RF_GAIN_DROP_DB_HIGH_2__VERIFY(src) \ argument
29241 #define BT_COEX_2__RFSAT_RX_RX__READ(src) \ argument
29244 #define BT_COEX_2__RFSAT_RX_RX__WRITE(src) \ argument
29247 #define BT_COEX_2__RFSAT_RX_RX__MODIFY(dst, src) \ argument
29251 #define BT_COEX_2__RFSAT_RX_RX__VERIFY(src) \ argument
29272 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__READ(src) (u_int32_t)(src) & 0x00000003U argument
29273 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__WRITE(src) \ argument
29276 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__MODIFY(dst, src) \ argument
29280 #define BT_COEX_3__RFSAT_BT_SRCH_SRCH__VERIFY(src) \ argument
29288 #define BT_COEX_3__RFSAT_BT_RX_SRCH__READ(src) \ argument
29291 #define BT_COEX_3__RFSAT_BT_RX_SRCH__WRITE(src) \ argument
29294 #define BT_COEX_3__RFSAT_BT_RX_SRCH__MODIFY(dst, src) \ argument
29298 #define BT_COEX_3__RFSAT_BT_RX_SRCH__VERIFY(src) \ argument
29306 #define BT_COEX_3__RFSAT_BT_SRCH_RX__READ(src) \ argument
29309 #define BT_COEX_3__RFSAT_BT_SRCH_RX__WRITE(src) \ argument
29312 #define BT_COEX_3__RFSAT_BT_SRCH_RX__MODIFY(dst, src) \ argument
29316 #define BT_COEX_3__RFSAT_BT_SRCH_RX__VERIFY(src) \ argument
29324 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__READ(src) \ argument
29327 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__WRITE(src) \ argument
29330 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__MODIFY(dst, src) \ argument
29334 #define BT_COEX_3__RFSAT_WLAN_SRCH_SRCH__VERIFY(src) \ argument
29342 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__READ(src) \ argument
29345 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__WRITE(src) \ argument
29348 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__MODIFY(dst, src) \ argument
29352 #define BT_COEX_3__RFSAT_WLAN_RX_SRCH__VERIFY(src) \ argument
29360 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__READ(src) \ argument
29363 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__WRITE(src) \ argument
29366 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__MODIFY(dst, src) \ argument
29370 #define BT_COEX_3__RFSAT_WLAN_SRCH_RX__VERIFY(src) \ argument
29378 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__READ(src) \ argument
29381 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__WRITE(src) \ argument
29384 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__MODIFY(dst, src) \ argument
29388 #define BT_COEX_3__RFSAT_EQ_SRCH_SRCH__VERIFY(src) \ argument
29396 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__READ(src) \ argument
29399 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__WRITE(src) \ argument
29402 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__MODIFY(dst, src) \ argument
29406 #define BT_COEX_3__RFSAT_EQ_RX_SRCH__VERIFY(src) \ argument
29414 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__READ(src) \ argument
29417 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__WRITE(src) \ argument
29420 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__MODIFY(dst, src) \ argument
29424 #define BT_COEX_3__RFSAT_EQ_SRCH_RX__VERIFY(src) \ argument
29432 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__READ(src) \ argument
29435 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__WRITE(src) \ argument
29438 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__MODIFY(dst, src) \ argument
29442 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_1__VERIFY(src) \ argument
29450 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__READ(src) \ argument
29453 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__WRITE(src) \ argument
29456 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__MODIFY(dst, src) \ argument
29460 #define BT_COEX_3__RF_GAIN_DROP_DB_NON_2__VERIFY(src) \ argument
29468 #define BT_COEX_3__BT_RX_FIRPWR_INCR__READ(src) \ argument
29471 #define BT_COEX_3__BT_RX_FIRPWR_INCR__WRITE(src) \ argument
29474 #define BT_COEX_3__BT_RX_FIRPWR_INCR__MODIFY(dst, src) \ argument
29478 #define BT_COEX_3__BT_RX_FIRPWR_INCR__VERIFY(src) \ argument
29499 #define BT_COEX_4__RFGAIN_EQV_LNA_0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
29500 #define BT_COEX_4__RFGAIN_EQV_LNA_0__WRITE(src) \ argument
29503 #define BT_COEX_4__RFGAIN_EQV_LNA_0__MODIFY(dst, src) \ argument
29507 #define BT_COEX_4__RFGAIN_EQV_LNA_0__VERIFY(src) \ argument
29515 #define BT_COEX_4__RFGAIN_EQV_LNA_1__READ(src) \ argument
29518 #define BT_COEX_4__RFGAIN_EQV_LNA_1__WRITE(src) \ argument
29521 #define BT_COEX_4__RFGAIN_EQV_LNA_1__MODIFY(dst, src) \ argument
29525 #define BT_COEX_4__RFGAIN_EQV_LNA_1__VERIFY(src) \ argument
29533 #define BT_COEX_4__RFGAIN_EQV_LNA_2__READ(src) \ argument
29536 #define BT_COEX_4__RFGAIN_EQV_LNA_2__WRITE(src) \ argument
29539 #define BT_COEX_4__RFGAIN_EQV_LNA_2__MODIFY(dst, src) \ argument
29543 #define BT_COEX_4__RFGAIN_EQV_LNA_2__VERIFY(src) \ argument
29551 #define BT_COEX_4__RFGAIN_EQV_LNA_3__READ(src) \ argument
29554 #define BT_COEX_4__RFGAIN_EQV_LNA_3__WRITE(src) \ argument
29557 #define BT_COEX_4__RFGAIN_EQV_LNA_3__MODIFY(dst, src) \ argument
29561 #define BT_COEX_4__RFGAIN_EQV_LNA_3__VERIFY(src) \ argument
29582 #define BT_COEX_5__RFGAIN_EQV_LNA_4__READ(src) (u_int32_t)(src) & 0x000000ffU argument
29583 #define BT_COEX_5__RFGAIN_EQV_LNA_4__WRITE(src) \ argument
29586 #define BT_COEX_5__RFGAIN_EQV_LNA_4__MODIFY(dst, src) \ argument
29590 #define BT_COEX_5__RFGAIN_EQV_LNA_4__VERIFY(src) \ argument
29598 #define BT_COEX_5__RFGAIN_EQV_LNA_5__READ(src) \ argument
29601 #define BT_COEX_5__RFGAIN_EQV_LNA_5__WRITE(src) \ argument
29604 #define BT_COEX_5__RFGAIN_EQV_LNA_5__MODIFY(dst, src) \ argument
29608 #define BT_COEX_5__RFGAIN_EQV_LNA_5__VERIFY(src) \ argument
29616 #define BT_COEX_5__RFGAIN_EQV_LNA_6__READ(src) \ argument
29619 #define BT_COEX_5__RFGAIN_EQV_LNA_6__WRITE(src) \ argument
29622 #define BT_COEX_5__RFGAIN_EQV_LNA_6__MODIFY(dst, src) \ argument
29626 #define BT_COEX_5__RFGAIN_EQV_LNA_6__VERIFY(src) \ argument
29634 #define BT_COEX_5__RFGAIN_EQV_LNA_7__READ(src) \ argument
29637 #define BT_COEX_5__RFGAIN_EQV_LNA_7__WRITE(src) \ argument
29640 #define BT_COEX_5__RFGAIN_EQV_LNA_7__MODIFY(dst, src) \ argument
29644 #define BT_COEX_5__RFGAIN_EQV_LNA_7__VERIFY(src) \ argument
29665 #define REDPWR_CTRL_1__REDPWR_MODE__READ(src) (u_int32_t)(src) & 0x00000003U argument
29666 #define REDPWR_CTRL_1__REDPWR_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
29667 #define REDPWR_CTRL_1__REDPWR_MODE__MODIFY(dst, src) \ argument
29671 #define REDPWR_CTRL_1__REDPWR_MODE__VERIFY(src) \ argument
29679 #define REDPWR_CTRL_1__REDPWR_MODE_CLR__READ(src) \ argument
29682 #define REDPWR_CTRL_1__REDPWR_MODE_CLR__WRITE(src) \ argument
29685 #define REDPWR_CTRL_1__REDPWR_MODE_CLR__MODIFY(dst, src) \ argument
29689 #define REDPWR_CTRL_1__REDPWR_MODE_CLR__VERIFY(src) \ argument
29703 #define REDPWR_CTRL_1__REDPWR_MODE_SET__READ(src) \ argument
29706 #define REDPWR_CTRL_1__REDPWR_MODE_SET__WRITE(src) \ argument
29709 #define REDPWR_CTRL_1__REDPWR_MODE_SET__MODIFY(dst, src) \ argument
29713 #define REDPWR_CTRL_1__REDPWR_MODE_SET__VERIFY(src) \ argument
29727 #define REDPWR_CTRL_1__GAIN_CORR_DB2__READ(src) \ argument
29730 #define REDPWR_CTRL_1__GAIN_CORR_DB2__WRITE(src) \ argument
29733 #define REDPWR_CTRL_1__GAIN_CORR_DB2__MODIFY(dst, src) \ argument
29737 #define REDPWR_CTRL_1__GAIN_CORR_DB2__VERIFY(src) \ argument
29745 #define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__READ(src) \ argument
29748 #define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__WRITE(src) \ argument
29751 #define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__MODIFY(dst, src) \ argument
29755 #define REDPWR_CTRL_1__SCFIR_ADJ_GAIN__VERIFY(src) \ argument
29763 #define REDPWR_CTRL_1__QUICKDROP_RF__READ(src) \ argument
29766 #define REDPWR_CTRL_1__QUICKDROP_RF__WRITE(src) \ argument
29769 #define REDPWR_CTRL_1__QUICKDROP_RF__MODIFY(dst, src) \ argument
29773 #define REDPWR_CTRL_1__QUICKDROP_RF__VERIFY(src) \ argument
29781 #define REDPWR_CTRL_1__BYPASS_FIR_F__READ(src) \ argument
29784 #define REDPWR_CTRL_1__BYPASS_FIR_F__WRITE(src) \ argument
29787 #define REDPWR_CTRL_1__BYPASS_FIR_F__MODIFY(dst, src) \ argument
29791 #define REDPWR_CTRL_1__BYPASS_FIR_F__VERIFY(src) \ argument
29805 #define REDPWR_CTRL_1__ADC_HALF_REF_F__READ(src) \ argument
29808 #define REDPWR_CTRL_1__ADC_HALF_REF_F__WRITE(src) \ argument
29811 #define REDPWR_CTRL_1__ADC_HALF_REF_F__MODIFY(dst, src) \ argument
29815 #define REDPWR_CTRL_1__ADC_HALF_REF_F__VERIFY(src) \ argument
29842 #define REDPWR_CTRL_2__SC01_SW_INDEX__READ(src) (u_int32_t)(src) & 0x0000007fU argument
29843 #define REDPWR_CTRL_2__SC01_SW_INDEX__WRITE(src) \ argument
29846 #define REDPWR_CTRL_2__SC01_SW_INDEX__MODIFY(dst, src) \ argument
29850 #define REDPWR_CTRL_2__SC01_SW_INDEX__VERIFY(src) \ argument
29858 #define REDPWR_CTRL_2__SC10_SW_INDEX__READ(src) \ argument
29861 #define REDPWR_CTRL_2__SC10_SW_INDEX__WRITE(src) \ argument
29864 #define REDPWR_CTRL_2__SC10_SW_INDEX__MODIFY(dst, src) \ argument
29868 #define REDPWR_CTRL_2__SC10_SW_INDEX__VERIFY(src) \ argument
29876 #define REDPWR_CTRL_2__LAST_SC0_INDEX__READ(src) \ argument
29879 #define REDPWR_CTRL_2__LAST_SC0_INDEX__WRITE(src) \ argument
29882 #define REDPWR_CTRL_2__LAST_SC0_INDEX__MODIFY(dst, src) \ argument
29886 #define REDPWR_CTRL_2__LAST_SC0_INDEX__VERIFY(src) \ argument
29907 #define RSSI_B0__RSSI_0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
29913 #define RSSI_B0__RSSI_EXT_0__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
29931 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \ argument
29939 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \ argument
29947 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \ argument
29955 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \ argument
29975 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \ argument
29983 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \ argument
29991 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \ argument
30011 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \ argument
30019 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \ argument
30027 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \ argument
30047 #define DC_CAL_STATUS_B0__OFFSETC1I_0__READ(src) (u_int32_t)(src) & 0x0000001fU argument
30053 #define DC_CAL_STATUS_B0__OFFSETC1Q_0__READ(src) \ argument
30061 #define DC_CAL_STATUS_B0__OFFSETC2I_0__READ(src) \ argument
30069 #define DC_CAL_STATUS_B0__OFFSETC2Q_0__READ(src) \ argument
30077 #define DC_CAL_STATUS_B0__OFFSETC3I_0__READ(src) \ argument
30085 #define DC_CAL_STATUS_B0__OFFSETC3Q_0__READ(src) \ argument
30105 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \ argument
30108 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \ argument
30111 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \ argument
30115 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \ argument
30123 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \ argument
30126 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \ argument
30129 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \ argument
30133 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \ argument
30141 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \ argument
30144 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \ argument
30147 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \ argument
30151 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \ argument
30165 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \ argument
30168 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \ argument
30171 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \ argument
30175 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \ argument
30189 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \ argument
30192 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \ argument
30195 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \ argument
30199 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \ argument
30213 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \ argument
30216 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \ argument
30219 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \ argument
30223 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \ argument
30237 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \ argument
30240 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \ argument
30243 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \ argument
30247 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \ argument
30261 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \ argument
30264 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \ argument
30267 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \ argument
30271 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \ argument
30285 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \ argument
30288 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \ argument
30291 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \ argument
30295 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \ argument
30309 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \ argument
30312 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \ argument
30315 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \ argument
30319 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \ argument
30333 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \ argument
30336 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \ argument
30339 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \ argument
30343 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \ argument
30357 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \ argument
30360 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \ argument
30363 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \ argument
30367 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \ argument
30381 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__READ(src) \ argument
30384 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__WRITE(src) \ argument
30387 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__MODIFY(dst, src) \ argument
30391 #define BBB_SIG_DETECT__BBB_MRC_OFF_NO_SWAP__VERIFY(src) \ argument
30405 #define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__READ(src) \ argument
30408 #define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__WRITE(src) \ argument
30411 #define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__MODIFY(dst, src) \ argument
30415 #define BBB_SIG_DETECT__SWAP_DEFAULT_CHAIN_CCK__VERIFY(src) \ argument
30429 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \ argument
30432 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \ argument
30435 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \ argument
30439 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \ argument
30466 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \ argument
30469 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \ argument
30472 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \ argument
30476 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \ argument
30490 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \ argument
30493 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \ argument
30496 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \ argument
30500 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \ argument
30508 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \ argument
30511 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \ argument
30514 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \ argument
30518 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \ argument
30532 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \ argument
30535 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \ argument
30538 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \ argument
30542 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \ argument
30550 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \ argument
30553 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \ argument
30556 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \ argument
30560 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \ argument
30574 #define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \ argument
30577 #define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \ argument
30580 #define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \ argument
30584 #define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \ argument
30592 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \ argument
30595 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \ argument
30598 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \ argument
30602 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \ argument
30610 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \ argument
30613 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \ argument
30616 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \ argument
30620 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \ argument
30628 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \ argument
30631 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \ argument
30634 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \ argument
30638 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \ argument
30659 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \ argument
30662 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \ argument
30665 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \ argument
30669 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \ argument
30677 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \ argument
30680 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \ argument
30683 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \ argument
30687 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \ argument
30695 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \ argument
30698 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \ argument
30701 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \ argument
30705 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \ argument
30719 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \ argument
30722 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \ argument
30725 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ argument
30729 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \ argument
30737 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \ argument
30740 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \ argument
30743 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \ argument
30747 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \ argument
30755 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \ argument
30758 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \ argument
30761 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \ argument
30765 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \ argument
30786 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \ argument
30789 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \ argument
30792 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \ argument
30796 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \ argument
30810 #define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \ argument
30813 #define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \ argument
30816 #define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \ argument
30820 #define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \ argument
30828 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \ argument
30831 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \ argument
30834 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \ argument
30838 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \ argument
30846 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \ argument
30849 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \ argument
30852 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \ argument
30856 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \ argument
30877 #define MRC_CCK_CTRL__BBB_MRC_EN__READ(src) (u_int32_t)(src) & 0x00000001U argument
30878 #define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
30879 #define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \ argument
30883 #define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \ argument
30897 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \ argument
30900 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \ argument
30903 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \ argument
30907 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \ argument
30921 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \ argument
30924 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \ argument
30927 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \ argument
30931 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \ argument
30939 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \ argument
30942 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \ argument
30945 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \ argument
30949 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \ argument
30957 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \ argument
30960 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \ argument
30963 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \ argument
30967 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \ argument
30975 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \ argument
30978 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \ argument
30981 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \ argument
30985 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \ argument
30993 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \ argument
30996 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \ argument
30999 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \ argument
31003 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \ argument
31011 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \ argument
31014 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \ argument
31017 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \ argument
31021 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \ argument
31042 #define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__READ(src) \ argument
31045 #define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__WRITE(src) \ argument
31048 #define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__MODIFY(dst, src) \ argument
31052 #define CCK_BLOCKER_DET__CCK_FREQ_SHIFT_BLOCKER_DETECTION__VERIFY(src) \ argument
31066 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__READ(src) \ argument
31069 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__WRITE(src) \ argument
31072 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__MODIFY(dst, src) \ argument
31076 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_RESTART_WEAK_SIG__VERIFY(src) \ argument
31090 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__READ(src) \ argument
31093 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__WRITE(src) \ argument
31096 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__MODIFY(dst, src) \ argument
31100 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_BKSUM_NUM__VERIFY(src) \ argument
31108 #define CCK_BLOCKER_DET__BK_VALID_DELAY__READ(src) \ argument
31111 #define CCK_BLOCKER_DET__BK_VALID_DELAY__WRITE(src) \ argument
31114 #define CCK_BLOCKER_DET__BK_VALID_DELAY__MODIFY(dst, src) \ argument
31118 #define CCK_BLOCKER_DET__BK_VALID_DELAY__VERIFY(src) \ argument
31126 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__READ(src) \ argument
31129 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__WRITE(src) \ argument
31132 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__MODIFY(dst, src) \ argument
31136 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_THR__VERIFY(src) \ argument
31144 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__READ(src) \ argument
31147 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__WRITE(src) \ argument
31150 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__MODIFY(dst, src) \ argument
31154 #define CCK_BLOCKER_DET__CCK_BLOCKER_DET_DELAY_THR__VERIFY(src) \ argument
31162 #define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__READ(src) \ argument
31165 #define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__WRITE(src) \ argument
31168 #define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__MODIFY(dst, src) \ argument
31172 #define CCK_BLOCKER_DET__CCK_BLOCKER_MONITOR_TIME__VERIFY(src) \ argument
31180 #define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__READ(src) \ argument
31183 #define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__WRITE(src) \ argument
31186 #define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__MODIFY(dst, src) \ argument
31190 #define CCK_BLOCKER_DET__SKIP_RAMP_ENABLE__VERIFY(src) \ argument
31204 #define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__READ(src) \ argument
31207 #define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__WRITE(src) \ argument
31210 #define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__MODIFY(dst, src) \ argument
31214 #define CCK_BLOCKER_DET__CCK_DET_RAMP_THR__VERIFY(src) \ argument
31235 #define RX_OCGAIN__GAIN_ENTRY__READ(src) (u_int32_t)(src) & 0xffffffffU argument
31236 #define RX_OCGAIN__GAIN_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
31237 #define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \ argument
31241 #define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \ argument
31262 #define D2_CHIP_ID__OLD_ID__READ(src) (u_int32_t)(src) & 0x000000ffU argument
31268 #define D2_CHIP_ID__ID__READ(src) (((u_int32_t)(src) & 0xffffff00U) >> 8) argument
31286 #define GEN_CONTROLS__TURBO__READ(src) (u_int32_t)(src) & 0x00000001U argument
31287 #define GEN_CONTROLS__TURBO__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
31288 #define GEN_CONTROLS__TURBO__MODIFY(dst, src) \ argument
31292 #define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
31304 #define GEN_CONTROLS__CF_SHORT20__READ(src) \ argument
31307 #define GEN_CONTROLS__CF_SHORT20__WRITE(src) \ argument
31310 #define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \ argument
31314 #define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \ argument
31328 #define GEN_CONTROLS__DYN_20_40__READ(src) \ argument
31331 #define GEN_CONTROLS__DYN_20_40__WRITE(src) \ argument
31334 #define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \ argument
31338 #define GEN_CONTROLS__DYN_20_40__VERIFY(src) \ argument
31352 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \ argument
31355 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \ argument
31358 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \ argument
31362 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \ argument
31376 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \ argument
31379 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \ argument
31382 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \ argument
31386 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \ argument
31400 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \ argument
31403 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \ argument
31406 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \ argument
31410 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \ argument
31424 #define GEN_CONTROLS__HT_ENABLE__READ(src) \ argument
31427 #define GEN_CONTROLS__HT_ENABLE__WRITE(src) \ argument
31430 #define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \ argument
31434 #define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \ argument
31448 #define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \ argument
31451 #define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \ argument
31454 #define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \ argument
31458 #define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \ argument
31472 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \ argument
31475 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \ argument
31478 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \ argument
31482 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \ argument
31496 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \ argument
31499 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \ argument
31502 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \ argument
31506 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \ argument
31520 #define GEN_CONTROLS__GF_ENABLE__READ(src) \ argument
31523 #define GEN_CONTROLS__GF_ENABLE__WRITE(src) \ argument
31526 #define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \ argument
31530 #define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \ argument
31544 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__READ(src) \ argument
31547 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__WRITE(src) \ argument
31550 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__MODIFY(dst, src) \ argument
31554 #define GEN_CONTROLS__ENABLE_DAC_ASYNC_FIFO__VERIFY(src) \ argument
31568 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \ argument
31571 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \ argument
31574 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \ argument
31578 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \ argument
31592 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__READ(src) \ argument
31595 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__WRITE(src) \ argument
31598 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__MODIFY(dst, src) \ argument
31602 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_HANDLING__VERIFY(src) \ argument
31616 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__READ(src) \ argument
31619 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__WRITE(src) \ argument
31622 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__MODIFY(dst, src) \ argument
31626 #define GEN_CONTROLS__STATIC20_MODE_HT40_PACKET_ERROR_RPT__VERIFY(src) \ argument
31640 #define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__READ(src) \ argument
31643 #define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__WRITE(src) \ argument
31646 #define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__MODIFY(dst, src) \ argument
31650 #define GEN_CONTROLS__ENABLE_CSD_PHASE_DITHERING__VERIFY(src) \ argument
31664 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__READ(src) \ argument
31667 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__WRITE(src) \ argument
31670 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__MODIFY(dst, src) \ argument
31674 #define GEN_CONTROLS__UNSUPP_HT_RATE_THRESHOLD__VERIFY(src) \ argument
31682 #define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__READ(src) \ argument
31685 #define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__WRITE(src) \ argument
31688 #define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__MODIFY(dst, src) \ argument
31692 #define GEN_CONTROLS__EN_ERR_TX_CHAIN_MASK_ZERO__VERIFY(src) \ argument
31719 #define MODES_SELECT__CCK_MODE__READ(src) (u_int32_t)(src) & 0x00000001U argument
31720 #define MODES_SELECT__CCK_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
31721 #define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \ argument
31725 #define MODES_SELECT__CCK_MODE__VERIFY(src) \ argument
31739 #define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \ argument
31742 #define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \ argument
31745 #define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \ argument
31749 #define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \ argument
31763 #define MODES_SELECT__HALF_RATE_MODE__READ(src) \ argument
31766 #define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \ argument
31769 #define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \ argument
31773 #define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \ argument
31787 #define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \ argument
31790 #define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \ argument
31793 #define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \ argument
31797 #define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \ argument
31811 #define MODES_SELECT__MAC_CLK_MODE__READ(src) \ argument
31814 #define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \ argument
31817 #define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \ argument
31821 #define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \ argument
31835 #define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \ argument
31838 #define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \ argument
31841 #define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \ argument
31845 #define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \ argument
31859 #define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \ argument
31862 #define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \ argument
31865 #define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \ argument
31869 #define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \ argument
31896 #define ACTIVE__CF_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U argument
31897 #define ACTIVE__CF_ACTIVE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
31898 #define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \ argument
31902 #define ACTIVE__CF_ACTIVE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
31927 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \ argument
31930 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \ argument
31933 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \ argument
31937 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \ argument
31945 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \ argument
31948 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \ argument
31951 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \ argument
31955 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \ argument
31976 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \ argument
31979 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \ argument
31982 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \ argument
31986 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \ argument
31994 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \ argument
31997 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \ argument
32000 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \ argument
32004 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \ argument
32025 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \ argument
32028 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \ argument
32031 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \ argument
32035 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \ argument
32049 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \ argument
32052 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \ argument
32055 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \ argument
32059 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \ argument
32073 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \ argument
32076 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \ argument
32079 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \ argument
32083 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \ argument
32097 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \ argument
32100 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \ argument
32103 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \ argument
32107 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \ argument
32121 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \ argument
32124 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \ argument
32127 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \ argument
32131 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \ argument
32139 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \ argument
32142 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \ argument
32145 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \ argument
32149 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \ argument
32157 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \ argument
32160 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \ argument
32163 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \ argument
32167 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \ argument
32175 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \ argument
32178 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \ argument
32181 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \ argument
32185 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \ argument
32199 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \ argument
32202 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \ argument
32205 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \ argument
32209 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \ argument
32223 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \ argument
32226 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \ argument
32229 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \ argument
32233 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \ argument
32247 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__READ(src) \ argument
32250 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__WRITE(src) \ argument
32253 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__MODIFY(dst, src) \ argument
32257 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COMPRESSED_RPT__VERIFY(src) \ argument
32284 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \ argument
32287 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \ argument
32290 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \ argument
32294 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \ argument
32308 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \ argument
32311 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \ argument
32314 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \ argument
32318 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \ argument
32332 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \ argument
32335 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \ argument
32338 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \ argument
32342 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \ argument
32350 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \ argument
32353 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \ argument
32356 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \ argument
32360 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \ argument
32368 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \ argument
32371 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \ argument
32374 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \ argument
32378 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \ argument
32386 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \ argument
32389 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \ argument
32392 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \ argument
32396 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \ argument
32404 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \ argument
32407 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \ argument
32410 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \ argument
32414 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \ argument
32435 #define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \ argument
32438 #define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \ argument
32441 #define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \ argument
32445 #define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \ argument
32453 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \ argument
32456 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \ argument
32459 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \ argument
32463 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \ argument
32477 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \ argument
32480 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \ argument
32483 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \ argument
32487 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \ argument
32501 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__READ(src) \ argument
32504 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__WRITE(src) \ argument
32507 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__MODIFY(dst, src) \ argument
32511 #define SEARCH_START_DELAY__RX_SOUNDING_ENABLE__VERIFY(src) \ argument
32525 #define SEARCH_START_DELAY__RM_HCSD4SVD__READ(src) \ argument
32528 #define SEARCH_START_DELAY__RM_HCSD4SVD__WRITE(src) \ argument
32531 #define SEARCH_START_DELAY__RM_HCSD4SVD__MODIFY(dst, src) \ argument
32535 #define SEARCH_START_DELAY__RM_HCSD4SVD__VERIFY(src) \ argument
32562 #define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src) (u_int32_t)(src) & 0x00000fffU argument
32563 #define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \ argument
32566 #define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \ argument
32570 #define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \ argument
32578 #define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \ argument
32581 #define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \ argument
32584 #define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \ argument
32588 #define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \ argument
32609 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \ argument
32612 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \ argument
32615 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \ argument
32619 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \ argument
32627 #define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \ argument
32630 #define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \ argument
32633 #define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \ argument
32637 #define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \ argument
32651 #define FRAME_CONTROL__CF_TX_CLIP__READ(src) \ argument
32654 #define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \ argument
32657 #define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \ argument
32661 #define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \ argument
32669 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \ argument
32672 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \ argument
32675 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \ argument
32679 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \ argument
32687 #define FRAME_CONTROL__TX_END_ADJUST__READ(src) \ argument
32690 #define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \ argument
32693 #define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \ argument
32697 #define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \ argument
32705 #define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \ argument
32708 #define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \ argument
32711 #define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \ argument
32715 #define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \ argument
32729 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \ argument
32732 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \ argument
32735 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \ argument
32739 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \ argument
32753 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \ argument
32756 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \ argument
32759 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \ argument
32763 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \ argument
32777 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__READ(src) \ argument
32780 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__WRITE(src) \ argument
32783 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__MODIFY(dst, src) \ argument
32787 #define FRAME_CONTROL__EN_ERR_STATIC20_MODE_HT40_PACKET__VERIFY(src) \ argument
32801 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \ argument
32804 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \ argument
32807 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \ argument
32811 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \ argument
32825 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \ argument
32828 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \ argument
32831 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \ argument
32835 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \ argument
32849 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \ argument
32852 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \ argument
32855 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \ argument
32859 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \ argument
32873 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \ argument
32876 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \ argument
32879 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \ argument
32883 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \ argument
32897 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \ argument
32900 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \ argument
32903 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \ argument
32907 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \ argument
32921 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \ argument
32924 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \ argument
32927 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \ argument
32931 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \ argument
32945 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \ argument
32948 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \ argument
32951 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \ argument
32955 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \ argument
32969 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \ argument
32972 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \ argument
32975 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \ argument
32979 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \ argument
32993 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \ argument
32996 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \ argument
32999 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \ argument
33003 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \ argument
33017 #define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \ argument
33020 #define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \ argument
33023 #define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \ argument
33027 #define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \ argument
33041 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \ argument
33044 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \ argument
33047 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \ argument
33051 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \ argument
33065 #define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \ argument
33068 #define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \ argument
33071 #define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \ argument
33075 #define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \ argument
33102 #define RFBUS_REQUEST__RFBUS_REQUEST__READ(src) (u_int32_t)(src) & 0x00000001U argument
33103 #define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \ argument
33106 #define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \ argument
33110 #define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \ argument
33137 #define RFBUS_GRANT__RFBUS_GRANT__READ(src) (u_int32_t)(src) & 0x00000001U argument
33149 #define RFBUS_GRANT__BT_ANT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
33173 #define RIFS__DISABLE_FCC_FIX__READ(src) \ argument
33176 #define RIFS__DISABLE_FCC_FIX__WRITE(src) \ argument
33179 #define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \ argument
33183 #define RIFS__DISABLE_FCC_FIX__VERIFY(src) \ argument
33197 #define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \ argument
33200 #define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \ argument
33203 #define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \ argument
33207 #define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \ argument
33221 #define RIFS__DISABLE_FCC_FIX2__READ(src) \ argument
33224 #define RIFS__DISABLE_FCC_FIX2__WRITE(src) \ argument
33227 #define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \ argument
33231 #define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \ argument
33245 #define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \ argument
33248 #define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \ argument
33251 #define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \ argument
33255 #define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \ argument
33269 #define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \ argument
33272 #define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \ argument
33275 #define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \ argument
33279 #define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \ argument
33293 #define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \ argument
33296 #define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \ argument
33299 #define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \ argument
33303 #define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \ argument
33330 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__READ(src) \ argument
33333 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__WRITE(src) \ argument
33336 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__MODIFY(dst, src) \ argument
33340 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_RPT_MODE__VERIFY(src) \ argument
33354 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__READ(src) \ argument
33357 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__WRITE(src) \ argument
33360 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__MODIFY(dst, src) \ argument
33364 #define SPECTRAL_SCAN_2__SPECTRAL_SCAN_NOISE_FLOOR_REF__VERIFY(src) \ argument
33385 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \ argument
33388 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \ argument
33391 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \ argument
33395 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \ argument
33416 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \ argument
33419 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \ argument
33422 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \ argument
33426 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \ argument
33447 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \ argument
33450 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \ argument
33453 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \ argument
33457 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \ argument
33465 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \ argument
33468 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \ argument
33471 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \ argument
33475 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \ argument
33483 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \ argument
33486 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \ argument
33489 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \ argument
33493 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \ argument
33501 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \ argument
33504 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \ argument
33507 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \ argument
33511 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \ argument
33532 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \ argument
33535 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \ argument
33538 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \ argument
33542 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \ argument
33550 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \ argument
33553 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \ argument
33556 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \ argument
33560 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \ argument
33568 #define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \ argument
33571 #define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \ argument
33574 #define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \ argument
33578 #define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \ argument
33586 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \ argument
33589 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \ argument
33592 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \ argument
33596 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \ argument
33617 #define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \ argument
33620 #define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \ argument
33623 #define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \ argument
33627 #define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \ argument
33635 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \ argument
33638 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \ argument
33641 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \ argument
33645 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \ argument
33653 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \ argument
33656 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \ argument
33659 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \ argument
33663 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \ argument
33671 #define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \ argument
33674 #define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \ argument
33677 #define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \ argument
33681 #define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \ argument
33702 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \ argument
33705 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \ argument
33708 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \ argument
33712 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \ argument
33720 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \ argument
33723 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \ argument
33726 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \ argument
33730 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \ argument
33738 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \ argument
33741 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \ argument
33744 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \ argument
33748 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \ argument
33756 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \ argument
33759 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \ argument
33762 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \ argument
33766 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \ argument
33787 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \ argument
33790 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \ argument
33793 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \ argument
33797 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \ argument
33811 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \ argument
33814 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \ argument
33817 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \ argument
33821 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \ argument
33835 #define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \ argument
33838 #define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \ argument
33841 #define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \ argument
33845 #define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \ argument
33859 #define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \ argument
33862 #define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \ argument
33865 #define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \ argument
33869 #define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \ argument
33896 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \ argument
33899 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \ argument
33902 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \ argument
33906 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \ argument
33914 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \ argument
33917 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \ argument
33920 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \ argument
33924 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \ argument
33932 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \ argument
33935 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \ argument
33938 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \ argument
33942 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \ argument
33950 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \ argument
33953 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \ argument
33956 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \ argument
33960 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \ argument
33968 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \ argument
33971 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \ argument
33974 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \ argument
33978 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \ argument
33986 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \ argument
33989 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \ argument
33992 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \ argument
33996 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \ argument
34017 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \ argument
34020 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \ argument
34023 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \ argument
34027 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \ argument
34035 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \ argument
34038 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \ argument
34041 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \ argument
34045 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \ argument
34053 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \ argument
34056 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \ argument
34059 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \ argument
34063 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \ argument
34071 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \ argument
34074 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \ argument
34077 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \ argument
34081 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \ argument
34089 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \ argument
34092 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \ argument
34095 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \ argument
34099 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \ argument
34107 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__READ(src) \ argument
34110 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__WRITE(src) \ argument
34113 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__MODIFY(dst, src) \ argument
34117 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_TX_1CHN__VERIFY(src) \ argument
34138 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \ argument
34141 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \ argument
34144 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \ argument
34148 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \ argument
34156 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \ argument
34159 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \ argument
34162 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \ argument
34166 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \ argument
34174 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \ argument
34177 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \ argument
34180 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \ argument
34184 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \ argument
34192 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \ argument
34195 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \ argument
34198 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \ argument
34202 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \ argument
34210 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \ argument
34213 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \ argument
34216 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \ argument
34220 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \ argument
34241 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \ argument
34244 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \ argument
34247 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \ argument
34251 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \ argument
34272 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \ argument
34275 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \ argument
34278 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \ argument
34282 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \ argument
34303 #define AGC_CONTROL__DO_CALIBRATE__READ(src) (u_int32_t)(src) & 0x00000001U argument
34304 #define AGC_CONTROL__DO_CALIBRATE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
34305 #define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \ argument
34309 #define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \ argument
34323 #define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \ argument
34326 #define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \ argument
34329 #define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \ argument
34333 #define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \ argument
34347 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \ argument
34350 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \ argument
34353 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \ argument
34357 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \ argument
34365 #define AGC_CONTROL__YCOK_MAX__READ(src) \ argument
34368 #define AGC_CONTROL__YCOK_MAX__WRITE(src) \ argument
34371 #define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \ argument
34375 #define AGC_CONTROL__YCOK_MAX__VERIFY(src) \ argument
34383 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \ argument
34386 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \ argument
34389 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \ argument
34393 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \ argument
34407 #define AGC_CONTROL__CAL_ENABLE__READ(src) \ argument
34410 #define AGC_CONTROL__CAL_ENABLE__WRITE(src) \ argument
34413 #define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \ argument
34417 #define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \ argument
34431 #define AGC_CONTROL__USE_TABLE_SEED__READ(src) \ argument
34434 #define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \ argument
34437 #define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \ argument
34441 #define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \ argument
34455 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \ argument
34458 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \ argument
34461 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \ argument
34465 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \ argument
34479 #define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \ argument
34482 #define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \ argument
34485 #define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \ argument
34489 #define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \ argument
34503 #define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \ argument
34506 #define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \ argument
34509 #define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \ argument
34513 #define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \ argument
34527 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \ argument
34530 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \ argument
34533 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \ argument
34537 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \ argument
34551 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \ argument
34554 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \ argument
34557 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \ argument
34561 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \ argument
34575 #define AGC_CONTROL__CLC_SUCCESS__READ(src) \ argument
34589 #define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \ argument
34592 #define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \ argument
34595 #define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \ argument
34599 #define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \ argument
34626 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \ argument
34629 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \ argument
34632 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \ argument
34636 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \ argument
34644 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \ argument
34647 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \ argument
34650 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \ argument
34654 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \ argument
34681 #define FCAL_1__FLC_PB_FSTEP__READ(src) (u_int32_t)(src) & 0x000003ffU argument
34682 #define FCAL_1__FLC_PB_FSTEP__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
34683 #define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \ argument
34687 #define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \ argument
34695 #define FCAL_1__FLC_SB_FSTEP__READ(src) \ argument
34698 #define FCAL_1__FLC_SB_FSTEP__WRITE(src) \ argument
34701 #define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \ argument
34705 #define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \ argument
34713 #define FCAL_1__FLC_PB_ATTEN__READ(src) \ argument
34716 #define FCAL_1__FLC_PB_ATTEN__WRITE(src) \ argument
34719 #define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \ argument
34723 #define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \ argument
34731 #define FCAL_1__FLC_SB_ATTEN__READ(src) \ argument
34734 #define FCAL_1__FLC_SB_ATTEN__WRITE(src) \ argument
34737 #define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \ argument
34741 #define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \ argument
34762 #define FCAL_2_B0__FLC_PWR_THRESH__READ(src) (u_int32_t)(src) & 0x00000007U argument
34763 #define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
34764 #define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \ argument
34768 #define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \ argument
34776 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \ argument
34779 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \ argument
34782 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \ argument
34786 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \ argument
34794 #define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \ argument
34797 #define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \ argument
34800 #define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \ argument
34804 #define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \ argument
34812 #define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \ argument
34815 #define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \ argument
34818 #define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \ argument
34822 #define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \ argument
34830 #define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \ argument
34833 #define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \ argument
34836 #define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \ argument
34840 #define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \ argument
34848 #define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \ argument
34851 #define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \ argument
34854 #define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \ argument
34858 #define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \ argument
34872 #define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \ argument
34875 #define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \ argument
34878 #define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \ argument
34882 #define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \ argument
34890 #define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \ argument
34911 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \ argument
34914 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \ argument
34917 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \ argument
34921 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \ argument
34935 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \ argument
34938 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \ argument
34941 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \ argument
34945 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \ argument
34953 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \ argument
34956 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \ argument
34959 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \ argument
34963 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \ argument
34984 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \ argument
34987 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \ argument
34990 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \ argument
34994 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \ argument
35008 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \ argument
35011 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \ argument
35014 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \ argument
35018 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \ argument
35032 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \ argument
35035 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \ argument
35038 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \ argument
35042 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \ argument
35050 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \ argument
35053 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \ argument
35056 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \ argument
35060 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \ argument
35068 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \ argument
35071 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \ argument
35074 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \ argument
35078 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \ argument
35086 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \ argument
35089 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \ argument
35092 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \ argument
35096 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \ argument
35104 #define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \ argument
35107 #define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \ argument
35110 #define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \ argument
35114 #define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \ argument
35122 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \ argument
35125 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \ argument
35128 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \ argument
35132 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \ argument
35146 #define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \ argument
35149 #define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \ argument
35152 #define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \ argument
35156 #define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \ argument
35183 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35184 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35185 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ argument
35189 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
35208 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35209 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35210 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ argument
35214 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
35233 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35234 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35235 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ argument
35239 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
35258 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35259 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35260 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ argument
35264 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
35283 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35284 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35285 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ argument
35289 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ argument
35310 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35311 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35312 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ argument
35316 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ argument
35337 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35338 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35339 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ argument
35343 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ argument
35364 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
35365 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
35366 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ argument
35370 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ argument
35391 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU argument
35392 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
35393 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ argument
35397 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
35403 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ argument
35406 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ argument
35409 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ argument
35413 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ argument
35421 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ argument
35424 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ argument
35427 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ argument
35431 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ argument
35439 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
35440 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
35441 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \ argument
35445 #define CL_TAB__BB_GAIN__VERIFY(src) \ argument
35466 #define SYNTH_CONTROL__RFCHANFRAC__READ(src) (u_int32_t)(src) & 0x0001ffffU argument
35467 #define SYNTH_CONTROL__RFCHANFRAC__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU) argument
35468 #define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \ argument
35472 #define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \ argument
35480 #define SYNTH_CONTROL__RFCHANNEL__READ(src) \ argument
35483 #define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \ argument
35486 #define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \ argument
35490 #define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \ argument
35498 #define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \ argument
35501 #define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \ argument
35504 #define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \ argument
35508 #define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \ argument
35516 #define SYNTH_CONTROL__RFFRACMODE__READ(src) \ argument
35519 #define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \ argument
35522 #define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \ argument
35526 #define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \ argument
35540 #define SYNTH_CONTROL__RFBMODE__READ(src) \ argument
35543 #define SYNTH_CONTROL__RFBMODE__WRITE(src) \ argument
35546 #define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \ argument
35550 #define SYNTH_CONTROL__RFBMODE__VERIFY(src) \ argument
35564 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \ argument
35567 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \ argument
35570 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \ argument
35574 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \ argument
35601 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \ argument
35604 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \ argument
35607 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \ argument
35611 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \ argument
35619 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \ argument
35622 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \ argument
35625 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \ argument
35629 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \ argument
35650 #define PLL_CNTL__BB_PLL_DIV__READ(src) (u_int32_t)(src) & 0x000003ffU argument
35651 #define PLL_CNTL__BB_PLL_DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
35652 #define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \ argument
35656 #define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \ argument
35664 #define PLL_CNTL__BB_PLL_REFDIV__READ(src) \ argument
35667 #define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \ argument
35670 #define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \ argument
35674 #define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \ argument
35682 #define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \ argument
35685 #define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \ argument
35688 #define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \ argument
35692 #define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \ argument
35700 #define PLL_CNTL__BB_PLLBYPASS__READ(src) \ argument
35703 #define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \ argument
35706 #define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \ argument
35710 #define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \ argument
35724 #define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \ argument
35727 #define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \ argument
35730 #define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \ argument
35734 #define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \ argument
35755 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \ argument
35758 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \ argument
35761 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \ argument
35765 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \ argument
35773 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \ argument
35776 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \ argument
35779 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \ argument
35783 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \ argument
35791 #define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \ argument
35794 #define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \ argument
35797 #define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \ argument
35801 #define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \ argument
35815 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \ argument
35818 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \ argument
35821 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \ argument
35825 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \ argument
35839 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \ argument
35842 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \ argument
35845 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \ argument
35849 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \ argument
35876 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \ argument
35879 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \ argument
35882 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \ argument
35886 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \ argument
35900 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \ argument
35903 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \ argument
35906 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \ argument
35910 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \ argument
35924 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \ argument
35927 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \ argument
35930 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \ argument
35934 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \ argument
35948 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \ argument
35951 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \ argument
35954 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \ argument
35958 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \ argument
35972 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \ argument
35975 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \ argument
35978 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \ argument
35982 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \ argument
35996 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \ argument
35999 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \ argument
36002 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \ argument
36006 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \ argument
36033 #define FORCE_ANALOG__FORCE_XPAON__READ(src) (u_int32_t)(src) & 0x00000001U argument
36034 #define FORCE_ANALOG__FORCE_XPAON__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
36035 #define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \ argument
36039 #define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \ argument
36053 #define FORCE_ANALOG__FORCED_XPAON__READ(src) \ argument
36056 #define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \ argument
36059 #define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \ argument
36063 #define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \ argument
36071 #define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \ argument
36074 #define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \ argument
36077 #define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \ argument
36081 #define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \ argument
36095 #define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \ argument
36098 #define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \ argument
36101 #define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \ argument
36105 #define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \ argument
36126 #define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU argument
36127 #define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \ argument
36130 #define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \ argument
36134 #define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \ argument
36142 #define TEST_CONTROLS__CF_TSTTRIG__READ(src) \ argument
36145 #define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \ argument
36148 #define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \ argument
36152 #define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \ argument
36166 #define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \ argument
36169 #define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \ argument
36172 #define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \ argument
36176 #define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \ argument
36184 #define TEST_CONTROLS__CARDBUS_MODE__READ(src) \ argument
36187 #define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \ argument
36190 #define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \ argument
36194 #define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \ argument
36202 #define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \ argument
36205 #define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \ argument
36208 #define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \ argument
36212 #define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \ argument
36226 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \ argument
36229 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \ argument
36232 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \ argument
36236 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \ argument
36250 #define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \ argument
36253 #define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \ argument
36256 #define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \ argument
36260 #define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \ argument
36274 #define TEST_CONTROLS__SLOW_CLK160__READ(src) \ argument
36277 #define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \ argument
36280 #define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \ argument
36284 #define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \ argument
36298 #define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \ argument
36301 #define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \ argument
36304 #define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \ argument
36308 #define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \ argument
36322 #define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \ argument
36325 #define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \ argument
36328 #define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \ argument
36332 #define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \ argument
36340 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \ argument
36343 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \ argument
36346 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \ argument
36350 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \ argument
36364 #define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \ argument
36367 #define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \ argument
36370 #define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \ argument
36374 #define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \ argument
36388 #define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \ argument
36391 #define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \ argument
36394 #define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \ argument
36398 #define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \ argument
36412 #define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \ argument
36415 #define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \ argument
36418 #define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \ argument
36422 #define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \ argument
36443 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \ argument
36446 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \ argument
36449 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \ argument
36453 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \ argument
36467 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \ argument
36470 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \ argument
36473 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \ argument
36477 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \ argument
36491 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \ argument
36494 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \ argument
36497 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \ argument
36501 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \ argument
36509 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \ argument
36512 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \ argument
36515 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \ argument
36519 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \ argument
36527 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \ argument
36530 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \ argument
36533 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \ argument
36537 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \ argument
36551 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \ argument
36554 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \ argument
36557 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \ argument
36561 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \ argument
36575 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \ argument
36578 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \ argument
36581 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \ argument
36585 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \ argument
36599 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \ argument
36602 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \ argument
36605 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \ argument
36609 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \ argument
36617 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \ argument
36620 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \ argument
36623 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \ argument
36627 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \ argument
36641 #define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \ argument
36644 #define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \ argument
36647 #define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \ argument
36651 #define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \ argument
36665 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \ argument
36668 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \ argument
36671 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \ argument
36675 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \ argument
36683 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \ argument
36686 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \ argument
36689 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \ argument
36693 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \ argument
36707 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \ argument
36710 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \ argument
36713 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \ argument
36717 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \ argument
36731 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \ argument
36734 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \ argument
36737 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \ argument
36741 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \ argument
36755 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \ argument
36758 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \ argument
36761 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \ argument
36765 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \ argument
36779 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \ argument
36782 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \ argument
36785 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \ argument
36789 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \ argument
36810 #define TSTDAC__TSTDAC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU argument
36816 #define TSTDAC__TSTDAC_OUT_I__READ(src) \ argument
36836 #define CHANNEL_STATUS__BT_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U argument
36848 #define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \ argument
36862 #define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \ argument
36876 #define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \ argument
36890 #define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \ argument
36898 #define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \ argument
36906 #define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \ argument
36914 #define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \ argument
36922 #define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \ argument
36942 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \ argument
36945 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \ argument
36948 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \ argument
36952 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \ argument
36966 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \ argument
36969 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \ argument
36972 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \ argument
36976 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \ argument
36990 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \ argument
36993 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \ argument
36996 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \ argument
37000 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \ argument
37014 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \ argument
37017 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \ argument
37020 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \ argument
37024 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \ argument
37051 #define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \ argument
37071 #define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU argument
37077 #define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \ argument
37085 #define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \ argument
37105 #define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \ argument
37113 #define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \ argument
37133 #define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \ argument
37141 #define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \ argument
37149 #define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \ argument
37157 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \ argument
37171 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \ argument
37197 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \ argument
37200 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \ argument
37203 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \ argument
37207 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \ argument
37228 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \ argument
37231 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \ argument
37234 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \ argument
37238 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \ argument
37252 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \ argument
37255 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \ argument
37258 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \ argument
37262 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \ argument
37276 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \ argument
37279 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \ argument
37282 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \ argument
37286 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \ argument
37294 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \ argument
37297 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \ argument
37300 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \ argument
37304 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \ argument
37318 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \ argument
37321 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \ argument
37324 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \ argument
37328 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \ argument
37342 #define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \ argument
37345 #define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \ argument
37348 #define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \ argument
37352 #define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \ argument
37360 #define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \ argument
37363 #define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \ argument
37366 #define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \ argument
37370 #define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \ argument
37391 #define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src) (u_int32_t)(src) & 0x0000000fU argument
37392 #define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \ argument
37395 #define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \ argument
37399 #define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \ argument
37407 #define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \ argument
37410 #define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \ argument
37413 #define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \ argument
37417 #define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \ argument
37425 #define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \ argument
37428 #define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \ argument
37431 #define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \ argument
37435 #define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \ argument
37443 #define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \ argument
37446 #define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \ argument
37449 #define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \ argument
37453 #define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \ argument
37474 #define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src) (u_int32_t)(src) & 0x0000003fU argument
37475 #define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \ argument
37478 #define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \ argument
37482 #define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \ argument
37490 #define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \ argument
37493 #define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \ argument
37496 #define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \ argument
37500 #define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \ argument
37508 #define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \ argument
37511 #define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \ argument
37514 #define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \ argument
37518 #define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \ argument
37526 #define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \ argument
37529 #define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \ argument
37532 #define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \ argument
37536 #define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \ argument
37557 #define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src) (u_int32_t)(src) & 0x000000ffU argument
37558 #define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \ argument
37561 #define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \ argument
37565 #define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \ argument
37573 #define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \ argument
37576 #define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \ argument
37579 #define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \ argument
37583 #define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \ argument
37591 #define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \ argument
37594 #define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \ argument
37597 #define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \ argument
37601 #define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \ argument
37609 #define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \ argument
37612 #define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \ argument
37615 #define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \ argument
37619 #define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \ argument
37640 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \ argument
37643 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \ argument
37646 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \ argument
37650 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \ argument
37658 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \ argument
37661 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \ argument
37664 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \ argument
37668 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \ argument
37682 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \ argument
37685 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \ argument
37688 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \ argument
37692 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \ argument
37713 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \ argument
37716 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \ argument
37719 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \ argument
37723 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \ argument
37731 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \ argument
37734 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \ argument
37737 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \ argument
37741 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \ argument
37749 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \ argument
37752 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \ argument
37755 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \ argument
37759 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \ argument
37767 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \ argument
37770 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \ argument
37773 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \ argument
37777 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \ argument
37798 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \ argument
37801 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \ argument
37804 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \ argument
37808 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \ argument
37816 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \ argument
37819 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \ argument
37822 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \ argument
37826 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \ argument
37834 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \ argument
37837 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \ argument
37840 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \ argument
37844 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \ argument
37852 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \ argument
37855 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \ argument
37858 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \ argument
37862 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \ argument
37883 #define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \ argument
37909 #define POWERTX_RATE1__POWERTX_0__READ(src) (u_int32_t)(src) & 0x0000003fU argument
37910 #define POWERTX_RATE1__POWERTX_0__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
37911 #define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \ argument
37915 #define POWERTX_RATE1__POWERTX_0__VERIFY(src) \ argument
37923 #define POWERTX_RATE1__POWERTX_1__READ(src) \ argument
37926 #define POWERTX_RATE1__POWERTX_1__WRITE(src) \ argument
37929 #define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \ argument
37933 #define POWERTX_RATE1__POWERTX_1__VERIFY(src) \ argument
37941 #define POWERTX_RATE1__POWERTX_2__READ(src) \ argument
37944 #define POWERTX_RATE1__POWERTX_2__WRITE(src) \ argument
37947 #define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \ argument
37951 #define POWERTX_RATE1__POWERTX_2__VERIFY(src) \ argument
37959 #define POWERTX_RATE1__POWERTX_3__READ(src) \ argument
37962 #define POWERTX_RATE1__POWERTX_3__WRITE(src) \ argument
37965 #define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \ argument
37969 #define POWERTX_RATE1__POWERTX_3__VERIFY(src) \ argument
37990 #define POWERTX_RATE2__POWERTX_4__READ(src) (u_int32_t)(src) & 0x0000003fU argument
37991 #define POWERTX_RATE2__POWERTX_4__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
37992 #define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \ argument
37996 #define POWERTX_RATE2__POWERTX_4__VERIFY(src) \ argument
38004 #define POWERTX_RATE2__POWERTX_5__READ(src) \ argument
38007 #define POWERTX_RATE2__POWERTX_5__WRITE(src) \ argument
38010 #define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \ argument
38014 #define POWERTX_RATE2__POWERTX_5__VERIFY(src) \ argument
38022 #define POWERTX_RATE2__POWERTX_6__READ(src) \ argument
38025 #define POWERTX_RATE2__POWERTX_6__WRITE(src) \ argument
38028 #define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \ argument
38032 #define POWERTX_RATE2__POWERTX_6__VERIFY(src) \ argument
38040 #define POWERTX_RATE2__POWERTX_7__READ(src) \ argument
38043 #define POWERTX_RATE2__POWERTX_7__WRITE(src) \ argument
38046 #define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \ argument
38050 #define POWERTX_RATE2__POWERTX_7__VERIFY(src) \ argument
38071 #define POWERTX_RATE3__POWERTX_1L__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38072 #define POWERTX_RATE3__POWERTX_1L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
38073 #define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \ argument
38077 #define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \ argument
38085 #define POWERTX_RATE3__POWERTX_2L__READ(src) \ argument
38088 #define POWERTX_RATE3__POWERTX_2L__WRITE(src) \ argument
38091 #define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \ argument
38095 #define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \ argument
38103 #define POWERTX_RATE3__POWERTX_2S__READ(src) \ argument
38106 #define POWERTX_RATE3__POWERTX_2S__WRITE(src) \ argument
38109 #define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \ argument
38113 #define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \ argument
38134 #define POWERTX_RATE4__POWERTX_55L__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38135 #define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
38136 #define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \ argument
38140 #define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \ argument
38148 #define POWERTX_RATE4__POWERTX_55S__READ(src) \ argument
38151 #define POWERTX_RATE4__POWERTX_55S__WRITE(src) \ argument
38154 #define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \ argument
38158 #define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \ argument
38166 #define POWERTX_RATE4__POWERTX_11L__READ(src) \ argument
38169 #define POWERTX_RATE4__POWERTX_11L__WRITE(src) \ argument
38172 #define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \ argument
38176 #define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \ argument
38184 #define POWERTX_RATE4__POWERTX_11S__READ(src) \ argument
38187 #define POWERTX_RATE4__POWERTX_11S__WRITE(src) \ argument
38190 #define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \ argument
38194 #define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \ argument
38215 #define POWERTX_RATE5__POWERTXHT20_0__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38216 #define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \ argument
38219 #define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \ argument
38223 #define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \ argument
38231 #define POWERTX_RATE5__POWERTXHT20_1__READ(src) \ argument
38234 #define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \ argument
38237 #define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \ argument
38241 #define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \ argument
38249 #define POWERTX_RATE5__POWERTXHT20_2__READ(src) \ argument
38252 #define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \ argument
38255 #define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \ argument
38259 #define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \ argument
38267 #define POWERTX_RATE5__POWERTXHT20_3__READ(src) \ argument
38270 #define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \ argument
38273 #define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \ argument
38277 #define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \ argument
38298 #define POWERTX_RATE6__POWERTXHT20_4__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38299 #define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \ argument
38302 #define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \ argument
38306 #define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \ argument
38314 #define POWERTX_RATE6__POWERTXHT20_5__READ(src) \ argument
38317 #define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \ argument
38320 #define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \ argument
38324 #define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \ argument
38332 #define POWERTX_RATE6__POWERTXHT20_6__READ(src) \ argument
38335 #define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \ argument
38338 #define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \ argument
38342 #define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \ argument
38350 #define POWERTX_RATE6__POWERTXHT20_7__READ(src) \ argument
38353 #define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \ argument
38356 #define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \ argument
38360 #define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \ argument
38381 #define POWERTX_RATE7__POWERTXHT40_0__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38382 #define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \ argument
38385 #define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \ argument
38389 #define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \ argument
38397 #define POWERTX_RATE7__POWERTXHT40_1__READ(src) \ argument
38400 #define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \ argument
38403 #define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \ argument
38407 #define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \ argument
38415 #define POWERTX_RATE7__POWERTXHT40_2__READ(src) \ argument
38418 #define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \ argument
38421 #define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \ argument
38425 #define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \ argument
38433 #define POWERTX_RATE7__POWERTXHT40_3__READ(src) \ argument
38436 #define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \ argument
38439 #define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \ argument
38443 #define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \ argument
38464 #define POWERTX_RATE8__POWERTXHT40_4__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38465 #define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \ argument
38468 #define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \ argument
38472 #define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \ argument
38480 #define POWERTX_RATE8__POWERTXHT40_5__READ(src) \ argument
38483 #define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \ argument
38486 #define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \ argument
38490 #define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \ argument
38498 #define POWERTX_RATE8__POWERTXHT40_6__READ(src) \ argument
38501 #define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \ argument
38504 #define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \ argument
38508 #define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \ argument
38516 #define POWERTX_RATE8__POWERTXHT40_7__READ(src) \ argument
38519 #define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \ argument
38522 #define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \ argument
38526 #define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \ argument
38547 #define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \ argument
38550 #define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \ argument
38553 #define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \ argument
38557 #define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \ argument
38565 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \ argument
38568 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \ argument
38571 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \ argument
38575 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \ argument
38583 #define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \ argument
38586 #define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \ argument
38589 #define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \ argument
38593 #define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \ argument
38601 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \ argument
38604 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \ argument
38607 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \ argument
38611 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \ argument
38632 #define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38633 #define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \ argument
38636 #define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \ argument
38640 #define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \ argument
38648 #define POWERTX_RATE10__POWERTXHT20_9__READ(src) \ argument
38651 #define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \ argument
38654 #define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \ argument
38658 #define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \ argument
38666 #define POWERTX_RATE10__POWERTXHT20_10__READ(src) \ argument
38669 #define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \ argument
38672 #define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \ argument
38676 #define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \ argument
38684 #define POWERTX_RATE10__POWERTXHT20_11__READ(src) \ argument
38687 #define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \ argument
38690 #define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \ argument
38694 #define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \ argument
38715 #define POWERTX_RATE11__POWERTXHT20_12__READ(src) \ argument
38718 #define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \ argument
38721 #define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \ argument
38725 #define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \ argument
38733 #define POWERTX_RATE11__POWERTXHT20_13__READ(src) \ argument
38736 #define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \ argument
38739 #define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \ argument
38743 #define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \ argument
38751 #define POWERTX_RATE11__POWERTXHT40_12__READ(src) \ argument
38754 #define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \ argument
38757 #define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \ argument
38761 #define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \ argument
38769 #define POWERTX_RATE11__POWERTXHT40_13__READ(src) \ argument
38772 #define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \ argument
38775 #define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \ argument
38779 #define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \ argument
38800 #define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU argument
38801 #define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \ argument
38804 #define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \ argument
38808 #define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \ argument
38816 #define POWERTX_RATE12__POWERTXHT40_9__READ(src) \ argument
38819 #define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \ argument
38822 #define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \ argument
38826 #define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \ argument
38834 #define POWERTX_RATE12__POWERTXHT40_10__READ(src) \ argument
38837 #define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \ argument
38840 #define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \ argument
38844 #define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \ argument
38852 #define POWERTX_RATE12__POWERTXHT40_11__READ(src) \ argument
38855 #define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \ argument
38858 #define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \ argument
38862 #define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \ argument
38883 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \ argument
38886 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \ argument
38889 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \ argument
38893 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \ argument
38907 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__READ(src) \ argument
38910 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__WRITE(src) \ argument
38913 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__MODIFY(dst, src) \ argument
38917 #define POWERTX_MAX__USE_PER_PACKET_OLPC_GAIN_DELTA_ADJ__VERIFY(src) \ argument
38944 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \ argument
38947 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \ argument
38950 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \ argument
38954 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \ argument
38962 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \ argument
38965 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \ argument
38968 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \ argument
38972 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \ argument
38993 #define TPC_1__FORCE_DAC_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U argument
38994 #define TPC_1__FORCE_DAC_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
38995 #define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \ argument
38999 #define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \ argument
39013 #define TPC_1__FORCED_DAC_GAIN__READ(src) \ argument
39016 #define TPC_1__FORCED_DAC_GAIN__WRITE(src) \ argument
39019 #define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \ argument
39023 #define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \ argument
39031 #define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \ argument
39034 #define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \ argument
39037 #define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \ argument
39041 #define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \ argument
39049 #define TPC_1__NUM_PD_GAIN__READ(src) (((u_int32_t)(src) & 0x0000c000U) >> 14) argument
39050 #define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U) argument
39051 #define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \ argument
39055 #define TPC_1__NUM_PD_GAIN__VERIFY(src) \ argument
39063 #define TPC_1__PD_GAIN_SETTING1__READ(src) \ argument
39066 #define TPC_1__PD_GAIN_SETTING1__WRITE(src) \ argument
39069 #define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \ argument
39073 #define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \ argument
39081 #define TPC_1__PD_GAIN_SETTING2__READ(src) \ argument
39084 #define TPC_1__PD_GAIN_SETTING2__WRITE(src) \ argument
39087 #define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \ argument
39091 #define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \ argument
39099 #define TPC_1__PD_GAIN_SETTING3__READ(src) \ argument
39102 #define TPC_1__PD_GAIN_SETTING3__WRITE(src) \ argument
39105 #define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \ argument
39109 #define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \ argument
39117 #define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \ argument
39120 #define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \ argument
39123 #define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \ argument
39127 #define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \ argument
39141 #define TPC_1__PD_CALIBRATE_WAIT__READ(src) \ argument
39144 #define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \ argument
39147 #define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \ argument
39151 #define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \ argument
39159 #define TPC_1__FORCE_PDADC_GAIN__READ(src) \ argument
39162 #define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \ argument
39165 #define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \ argument
39169 #define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \ argument
39183 #define TPC_1__FORCED_PDADC_GAIN__READ(src) \ argument
39186 #define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \ argument
39189 #define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \ argument
39193 #define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \ argument
39214 #define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU argument
39215 #define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \ argument
39218 #define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \ argument
39222 #define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \ argument
39230 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \ argument
39233 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \ argument
39236 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \ argument
39240 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \ argument
39248 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \ argument
39251 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \ argument
39254 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \ argument
39258 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \ argument
39279 #define TPC_3__TX_END_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU argument
39280 #define TPC_3__TX_END_TO_PDADC_ON__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
39281 #define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \ argument
39285 #define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \ argument
39293 #define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \ argument
39296 #define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \ argument
39299 #define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \ argument
39303 #define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \ argument
39311 #define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \ argument
39314 #define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \ argument
39317 #define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \ argument
39321 #define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \ argument
39329 #define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \ argument
39332 #define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \ argument
39335 #define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \ argument
39339 #define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \ argument
39347 #define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \ argument
39350 #define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \ argument
39353 #define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \ argument
39357 #define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \ argument
39365 #define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \ argument
39368 #define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \ argument
39371 #define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \ argument
39375 #define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \ argument
39383 #define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \ argument
39386 #define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \ argument
39389 #define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \ argument
39393 #define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \ argument
39420 #define TPC_4_B0__PD_AVG_VALID_0__READ(src) (u_int32_t)(src) & 0x00000001U argument
39432 #define TPC_4_B0__PD_AVG_OUT_0__READ(src) \ argument
39440 #define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) argument
39446 #define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \ argument
39454 #define TPC_4_B0__RATE_SENT_0__READ(src) \ argument
39462 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \ argument
39465 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \ argument
39468 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \ argument
39472 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \ argument
39493 #define TPC_5_B0__PD_GAIN_OVERLAP__READ(src) (u_int32_t)(src) & 0x0000000fU argument
39494 #define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
39495 #define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \ argument
39499 #define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \ argument
39507 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \ argument
39510 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \ argument
39513 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \ argument
39517 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \ argument
39525 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \ argument
39528 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \ argument
39531 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \ argument
39535 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \ argument
39543 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \ argument
39546 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \ argument
39549 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \ argument
39553 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \ argument
39561 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \ argument
39564 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \ argument
39567 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \ argument
39571 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \ argument
39592 #define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src) (u_int32_t)(src) & 0x0000003fU argument
39593 #define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \ argument
39596 #define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \ argument
39600 #define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \ argument
39608 #define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \ argument
39611 #define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \ argument
39614 #define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \ argument
39618 #define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \ argument
39626 #define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \ argument
39629 #define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \ argument
39632 #define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \ argument
39636 #define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \ argument
39644 #define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \ argument
39647 #define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \ argument
39650 #define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \ argument
39654 #define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \ argument
39662 #define TPC_6_B0__ERROR_EST_MODE__READ(src) \ argument
39665 #define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \ argument
39668 #define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \ argument
39672 #define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \ argument
39680 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \ argument
39683 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \ argument
39686 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ argument
39690 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \ argument
39711 #define TPC_7__TX_GAIN_TABLE_MAX__READ(src) (u_int32_t)(src) & 0x0000003fU argument
39712 #define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
39713 #define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \ argument
39717 #define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \ argument
39725 #define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \ argument
39728 #define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \ argument
39731 #define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \ argument
39735 #define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \ argument
39743 #define TPC_7__EN_CL_GAIN_MOD__READ(src) \ argument
39746 #define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \ argument
39749 #define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \ argument
39753 #define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \ argument
39767 #define TPC_7__USE_TX_PD_IN_XPA__READ(src) \ argument
39770 #define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \ argument
39773 #define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \ argument
39777 #define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \ argument
39791 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \ argument
39794 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \ argument
39797 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \ argument
39801 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \ argument
39815 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \ argument
39818 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \ argument
39821 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \ argument
39825 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \ argument
39852 #define TPC_8__DESIRED_SCALE_0__READ(src) (u_int32_t)(src) & 0x0000001fU argument
39853 #define TPC_8__DESIRED_SCALE_0__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
39854 #define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \ argument
39858 #define TPC_8__DESIRED_SCALE_0__VERIFY(src) \ argument
39866 #define TPC_8__DESIRED_SCALE_1__READ(src) \ argument
39869 #define TPC_8__DESIRED_SCALE_1__WRITE(src) \ argument
39872 #define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \ argument
39876 #define TPC_8__DESIRED_SCALE_1__VERIFY(src) \ argument
39884 #define TPC_8__DESIRED_SCALE_2__READ(src) \ argument
39887 #define TPC_8__DESIRED_SCALE_2__WRITE(src) \ argument
39890 #define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \ argument
39894 #define TPC_8__DESIRED_SCALE_2__VERIFY(src) \ argument
39902 #define TPC_8__DESIRED_SCALE_3__READ(src) \ argument
39905 #define TPC_8__DESIRED_SCALE_3__WRITE(src) \ argument
39908 #define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \ argument
39912 #define TPC_8__DESIRED_SCALE_3__VERIFY(src) \ argument
39920 #define TPC_8__DESIRED_SCALE_4__READ(src) \ argument
39923 #define TPC_8__DESIRED_SCALE_4__WRITE(src) \ argument
39926 #define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \ argument
39930 #define TPC_8__DESIRED_SCALE_4__VERIFY(src) \ argument
39938 #define TPC_8__DESIRED_SCALE_5__READ(src) \ argument
39941 #define TPC_8__DESIRED_SCALE_5__WRITE(src) \ argument
39944 #define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \ argument
39948 #define TPC_8__DESIRED_SCALE_5__VERIFY(src) \ argument
39969 #define TPC_9__DESIRED_SCALE_6__READ(src) (u_int32_t)(src) & 0x0000001fU argument
39970 #define TPC_9__DESIRED_SCALE_6__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
39971 #define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \ argument
39975 #define TPC_9__DESIRED_SCALE_6__VERIFY(src) \ argument
39983 #define TPC_9__DESIRED_SCALE_7__READ(src) \ argument
39986 #define TPC_9__DESIRED_SCALE_7__WRITE(src) \ argument
39989 #define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \ argument
39993 #define TPC_9__DESIRED_SCALE_7__VERIFY(src) \ argument
40001 #define TPC_9__DESIRED_SCALE_CCK__READ(src) \ argument
40004 #define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \ argument
40007 #define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \ argument
40011 #define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \ argument
40019 #define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \ argument
40022 #define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \ argument
40025 #define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \ argument
40029 #define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \ argument
40043 #define TPC_9__PD_DC_OFFSET_THR__READ(src) \ argument
40046 #define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \ argument
40049 #define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \ argument
40053 #define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \ argument
40061 #define TPC_9__WAIT_CALTX_SETTLE__READ(src) \ argument
40064 #define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \ argument
40067 #define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \ argument
40071 #define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \ argument
40079 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \ argument
40082 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \ argument
40085 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \ argument
40089 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \ argument
40116 #define TPC_10__DESIRED_SCALE_HT20_0__READ(src) (u_int32_t)(src) & 0x0000001fU argument
40117 #define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \ argument
40120 #define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \ argument
40124 #define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \ argument
40132 #define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \ argument
40135 #define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \ argument
40138 #define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \ argument
40142 #define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \ argument
40150 #define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \ argument
40153 #define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \ argument
40156 #define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \ argument
40160 #define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \ argument
40168 #define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \ argument
40171 #define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \ argument
40174 #define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \ argument
40178 #define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \ argument
40186 #define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \ argument
40189 #define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \ argument
40192 #define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \ argument
40196 #define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \ argument
40204 #define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \ argument
40207 #define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \ argument
40210 #define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \ argument
40214 #define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \ argument
40235 #define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \ argument
40238 #define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \ argument
40241 #define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \ argument
40245 #define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \ argument
40253 #define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \ argument
40256 #define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \ argument
40259 #define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \ argument
40263 #define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \ argument
40271 #define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \ argument
40274 #define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \ argument
40277 #define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \ argument
40281 #define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \ argument
40289 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \ argument
40292 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \ argument
40295 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \ argument
40299 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \ argument
40320 #define TPC_12__DESIRED_SCALE_HT40_0__READ(src) (u_int32_t)(src) & 0x0000001fU argument
40321 #define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \ argument
40324 #define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \ argument
40328 #define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \ argument
40336 #define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \ argument
40339 #define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \ argument
40342 #define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \ argument
40346 #define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \ argument
40354 #define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \ argument
40357 #define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \ argument
40360 #define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \ argument
40364 #define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \ argument
40372 #define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \ argument
40375 #define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \ argument
40378 #define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \ argument
40382 #define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \ argument
40390 #define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \ argument
40393 #define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \ argument
40396 #define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \ argument
40400 #define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \ argument
40408 #define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \ argument
40411 #define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \ argument
40414 #define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \ argument
40418 #define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \ argument
40439 #define TPC_13__DESIRED_SCALE_HT40_6__READ(src) (u_int32_t)(src) & 0x0000001fU argument
40440 #define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \ argument
40443 #define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \ argument
40447 #define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \ argument
40455 #define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \ argument
40458 #define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \ argument
40461 #define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \ argument
40465 #define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \ argument
40486 #define TPC_14__DESIRED_SCALE_HT20_8__READ(src) (u_int32_t)(src) & 0x0000001fU argument
40487 #define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \ argument
40490 #define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \ argument
40494 #define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \ argument
40502 #define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \ argument
40505 #define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \ argument
40508 #define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \ argument
40512 #define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \ argument
40520 #define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \ argument
40523 #define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \ argument
40526 #define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \ argument
40530 #define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \ argument
40538 #define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \ argument
40541 #define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \ argument
40544 #define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \ argument
40548 #define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \ argument
40556 #define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \ argument
40559 #define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \ argument
40562 #define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \ argument
40566 #define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \ argument
40574 #define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \ argument
40577 #define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \ argument
40580 #define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \ argument
40584 #define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \ argument
40605 #define TPC_15__DESIRED_SCALE_HT40_8__READ(src) (u_int32_t)(src) & 0x0000001fU argument
40606 #define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \ argument
40609 #define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \ argument
40613 #define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \ argument
40621 #define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \ argument
40624 #define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \ argument
40627 #define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \ argument
40631 #define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \ argument
40639 #define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \ argument
40642 #define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \ argument
40645 #define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \ argument
40649 #define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \ argument
40657 #define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \ argument
40660 #define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \ argument
40663 #define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \ argument
40667 #define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \ argument
40675 #define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \ argument
40678 #define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \ argument
40681 #define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \ argument
40685 #define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \ argument
40693 #define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \ argument
40696 #define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \ argument
40699 #define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \ argument
40703 #define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \ argument
40724 #define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \ argument
40727 #define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \ argument
40730 #define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \ argument
40734 #define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \ argument
40742 #define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \ argument
40745 #define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \ argument
40748 #define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \ argument
40752 #define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \ argument
40760 #define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \ argument
40763 #define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \ argument
40766 #define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \ argument
40770 #define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \ argument
40791 #define TPC_17__ENABLE_PAL__READ(src) (u_int32_t)(src) & 0x00000001U argument
40792 #define TPC_17__ENABLE_PAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
40793 #define TPC_17__ENABLE_PAL__MODIFY(dst, src) \ argument
40797 #define TPC_17__ENABLE_PAL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
40809 #define TPC_17__ENABLE_PAL_CCK__READ(src) \ argument
40812 #define TPC_17__ENABLE_PAL_CCK__WRITE(src) \ argument
40815 #define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \ argument
40819 #define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \ argument
40833 #define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \ argument
40836 #define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \ argument
40839 #define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \ argument
40843 #define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \ argument
40857 #define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \ argument
40860 #define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \ argument
40863 #define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \ argument
40867 #define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \ argument
40881 #define TPC_17__PAL_POWER_THRESHOLD__READ(src) \ argument
40884 #define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \ argument
40887 #define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \ argument
40891 #define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \ argument
40899 #define TPC_17__FORCE_PAL_LOCKED__READ(src) \ argument
40902 #define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \ argument
40905 #define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \ argument
40909 #define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \ argument
40923 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \ argument
40926 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \ argument
40929 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \ argument
40933 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \ argument
40954 #define TPC_18__THERM_CAL_VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU argument
40955 #define TPC_18__THERM_CAL_VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
40956 #define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \ argument
40960 #define TPC_18__THERM_CAL_VALUE__VERIFY(src) \ argument
40968 #define TPC_18__VOLT_CAL_VALUE__READ(src) \ argument
40971 #define TPC_18__VOLT_CAL_VALUE__WRITE(src) \ argument
40974 #define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \ argument
40978 #define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \ argument
40986 #define TPC_18__USE_LEGACY_TPC__READ(src) \ argument
40989 #define TPC_18__USE_LEGACY_TPC__WRITE(src) \ argument
40992 #define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \ argument
40996 #define TPC_18__USE_LEGACY_TPC__VERIFY(src) \ argument
41010 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \ argument
41013 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \ argument
41016 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \ argument
41020 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \ argument
41041 #define TPC_19_B0__ALPHA_THERM_0__READ(src) (u_int32_t)(src) & 0x000000ffU argument
41042 #define TPC_19_B0__ALPHA_THERM_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
41043 #define TPC_19_B0__ALPHA_THERM_0__MODIFY(dst, src) \ argument
41047 #define TPC_19_B0__ALPHA_THERM_0__VERIFY(src) \ argument
41055 #define TPC_19_B0__ALPHA_THERM_PAL_ON_0__READ(src) \ argument
41058 #define TPC_19_B0__ALPHA_THERM_PAL_ON_0__WRITE(src) \ argument
41061 #define TPC_19_B0__ALPHA_THERM_PAL_ON_0__MODIFY(dst, src) \ argument
41065 #define TPC_19_B0__ALPHA_THERM_PAL_ON_0__VERIFY(src) \ argument
41073 #define TPC_19_B0__ALPHA_VOLT_0__READ(src) \ argument
41076 #define TPC_19_B0__ALPHA_VOLT_0__WRITE(src) \ argument
41079 #define TPC_19_B0__ALPHA_VOLT_0__MODIFY(dst, src) \ argument
41083 #define TPC_19_B0__ALPHA_VOLT_0__VERIFY(src) \ argument
41091 #define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__READ(src) \ argument
41094 #define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__WRITE(src) \ argument
41097 #define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__MODIFY(dst, src) \ argument
41101 #define TPC_19_B0__ALPHA_VOLT_PAL_ON_0__VERIFY(src) \ argument
41122 #define TPC_20__ENABLE_PAL_MCS_0__READ(src) (u_int32_t)(src) & 0x00000001U argument
41123 #define TPC_20__ENABLE_PAL_MCS_0__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
41124 #define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \ argument
41128 #define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \ argument
41142 #define TPC_20__ENABLE_PAL_MCS_1__READ(src) \ argument
41145 #define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \ argument
41148 #define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \ argument
41152 #define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \ argument
41166 #define TPC_20__ENABLE_PAL_MCS_2__READ(src) \ argument
41169 #define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \ argument
41172 #define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \ argument
41176 #define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \ argument
41190 #define TPC_20__ENABLE_PAL_MCS_3__READ(src) \ argument
41193 #define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \ argument
41196 #define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \ argument
41200 #define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \ argument
41214 #define TPC_20__ENABLE_PAL_MCS_4__READ(src) \ argument
41217 #define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \ argument
41220 #define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \ argument
41224 #define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \ argument
41238 #define TPC_20__ENABLE_PAL_MCS_5__READ(src) \ argument
41241 #define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \ argument
41244 #define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \ argument
41248 #define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \ argument
41262 #define TPC_20__ENABLE_PAL_MCS_6__READ(src) \ argument
41265 #define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \ argument
41268 #define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \ argument
41272 #define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \ argument
41286 #define TPC_20__ENABLE_PAL_MCS_7__READ(src) \ argument
41289 #define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \ argument
41292 #define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \ argument
41296 #define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \ argument
41310 #define TPC_20__ENABLE_PAL_MCS_8__READ(src) \ argument
41313 #define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \ argument
41316 #define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \ argument
41320 #define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \ argument
41334 #define TPC_20__ENABLE_PAL_MCS_9__READ(src) \ argument
41337 #define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \ argument
41340 #define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \ argument
41344 #define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \ argument
41358 #define TPC_20__ENABLE_PAL_MCS_10__READ(src) \ argument
41361 #define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \ argument
41364 #define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \ argument
41368 #define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \ argument
41382 #define TPC_20__ENABLE_PAL_MCS_11__READ(src) \ argument
41385 #define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \ argument
41388 #define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \ argument
41392 #define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \ argument
41406 #define TPC_20__ENABLE_PAL_MCS_12__READ(src) \ argument
41409 #define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \ argument
41412 #define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \ argument
41416 #define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \ argument
41430 #define TPC_20__ENABLE_PAL_MCS_13__READ(src) \ argument
41433 #define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \ argument
41436 #define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \ argument
41440 #define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \ argument
41454 #define TPC_20__ENABLE_PAL_MCS_14__READ(src) \ argument
41457 #define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \ argument
41460 #define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \ argument
41464 #define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \ argument
41478 #define TPC_20__ENABLE_PAL_MCS_15__READ(src) \ argument
41481 #define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \ argument
41484 #define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \ argument
41488 #define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \ argument
41502 #define TPC_20__ENABLE_PAL_MCS_16__READ(src) \ argument
41505 #define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \ argument
41508 #define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \ argument
41512 #define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \ argument
41526 #define TPC_20__ENABLE_PAL_MCS_17__READ(src) \ argument
41529 #define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \ argument
41532 #define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \ argument
41536 #define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \ argument
41550 #define TPC_20__ENABLE_PAL_MCS_18__READ(src) \ argument
41553 #define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \ argument
41556 #define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \ argument
41560 #define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \ argument
41574 #define TPC_20__ENABLE_PAL_MCS_19__READ(src) \ argument
41577 #define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \ argument
41580 #define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \ argument
41584 #define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \ argument
41598 #define TPC_20__ENABLE_PAL_MCS_20__READ(src) \ argument
41601 #define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \ argument
41604 #define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \ argument
41608 #define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \ argument
41622 #define TPC_20__ENABLE_PAL_MCS_21__READ(src) \ argument
41625 #define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \ argument
41628 #define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \ argument
41632 #define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \ argument
41646 #define TPC_20__ENABLE_PAL_MCS_22__READ(src) \ argument
41649 #define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \ argument
41652 #define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \ argument
41656 #define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \ argument
41670 #define TPC_20__ENABLE_PAL_MCS_23__READ(src) \ argument
41673 #define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \ argument
41676 #define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \ argument
41680 #define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \ argument
41707 #define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \ argument
41710 #define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \ argument
41713 #define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \ argument
41717 #define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \ argument
41725 #define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \ argument
41728 #define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \ argument
41731 #define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \ argument
41735 #define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \ argument
41743 #define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \ argument
41746 #define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \ argument
41749 #define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \ argument
41753 #define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \ argument
41761 #define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \ argument
41764 #define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \ argument
41767 #define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \ argument
41771 #define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \ argument
41779 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \ argument
41782 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \ argument
41785 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \ argument
41789 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \ argument
41803 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \ argument
41806 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \ argument
41809 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \ argument
41813 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \ argument
41828 #define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__READ(src) \ argument
41831 #define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__WRITE(src) \ argument
41834 #define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__MODIFY(dst, src) \ argument
41838 #define THERM_ADC_1__CHECK_DONE_FOR_1ST_ADC_MEAS_OF_EACH_FRAME__VERIFY(src) \ argument
41852 #define THERM_ADC_1__THERM_MEASURE_RESET__READ(src) \ argument
41855 #define THERM_ADC_1__THERM_MEASURE_RESET__WRITE(src) \ argument
41858 #define THERM_ADC_1__THERM_MEASURE_RESET__MODIFY(dst, src) \ argument
41862 #define THERM_ADC_1__THERM_MEASURE_RESET__VERIFY(src) \ argument
41889 #define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \ argument
41892 #define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \ argument
41895 #define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \ argument
41899 #define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \ argument
41907 #define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \ argument
41910 #define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \ argument
41913 #define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \ argument
41917 #define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \ argument
41925 #define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \ argument
41928 #define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \ argument
41931 #define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \ argument
41935 #define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \ argument
41956 #define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU argument
41957 #define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \ argument
41960 #define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \ argument
41964 #define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \ argument
41972 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \ argument
41975 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \ argument
41978 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \ argument
41982 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \ argument
41990 #define THERM_ADC_3__ADC_INTERVAL__READ(src) \ argument
41993 #define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \ argument
41996 #define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \ argument
42000 #define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \ argument
42021 #define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \ argument
42029 #define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \ argument
42037 #define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \ argument
42045 #define THERM_ADC_4__FORCE_THERM_CHAIN__READ(src) \ argument
42048 #define THERM_ADC_4__FORCE_THERM_CHAIN__WRITE(src) \ argument
42051 #define THERM_ADC_4__FORCE_THERM_CHAIN__MODIFY(dst, src) \ argument
42055 #define THERM_ADC_4__FORCE_THERM_CHAIN__VERIFY(src) \ argument
42069 #define THERM_ADC_4__PREFERRED_THERM_CHAIN__READ(src) \ argument
42072 #define THERM_ADC_4__PREFERRED_THERM_CHAIN__WRITE(src) \ argument
42075 #define THERM_ADC_4__PREFERRED_THERM_CHAIN__MODIFY(dst, src) \ argument
42079 #define THERM_ADC_4__PREFERRED_THERM_CHAIN__VERIFY(src) \ argument
42100 #define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U argument
42101 #define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \ argument
42104 #define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \ argument
42108 #define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \ argument
42122 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \ argument
42125 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \ argument
42128 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \ argument
42132 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \ argument
42140 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \ argument
42143 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \ argument
42146 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \ argument
42150 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \ argument
42158 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \ argument
42161 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \ argument
42164 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \ argument
42168 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \ argument
42176 #define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \ argument
42179 #define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \ argument
42182 #define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \ argument
42186 #define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \ argument
42194 #define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \ argument
42197 #define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \ argument
42200 #define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \ argument
42204 #define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \ argument
42212 #define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \ argument
42215 #define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \ argument
42218 #define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \ argument
42222 #define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \ argument
42230 #define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \ argument
42233 #define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \ argument
42236 #define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \ argument
42240 #define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \ argument
42248 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \ argument
42251 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \ argument
42254 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \ argument
42258 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \ argument
42272 #define TX_FORCED_GAIN__FORCED_OB__READ(src) \ argument
42275 #define TX_FORCED_GAIN__FORCED_OB__WRITE(src) \ argument
42278 #define TX_FORCED_GAIN__FORCED_OB__MODIFY(dst, src) \ argument
42282 #define TX_FORCED_GAIN__FORCED_OB__VERIFY(src) \ argument
42290 #define TX_FORCED_GAIN__FORCED_DB__READ(src) \ argument
42293 #define TX_FORCED_GAIN__FORCED_DB__WRITE(src) \ argument
42296 #define TX_FORCED_GAIN__FORCED_DB__MODIFY(dst, src) \ argument
42300 #define TX_FORCED_GAIN__FORCED_DB__VERIFY(src) \ argument
42308 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__READ(src) \ argument
42311 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__WRITE(src) \ argument
42314 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__MODIFY(dst, src) \ argument
42318 #define TX_FORCED_GAIN__FORCED_GREEN_PAPRD_ENABLE__VERIFY(src) \ argument
42345 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42346 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ argument
42350 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ argument
42370 #define TX_GAIN_TAB_1__TG_TABLE1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42371 #define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42372 #define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \ argument
42376 #define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \ argument
42397 #define TX_GAIN_TAB_2__TG_TABLE2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42398 #define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42399 #define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \ argument
42403 #define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \ argument
42424 #define TX_GAIN_TAB_3__TG_TABLE3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42425 #define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42426 #define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \ argument
42430 #define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \ argument
42451 #define TX_GAIN_TAB_4__TG_TABLE4__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42452 #define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42453 #define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \ argument
42457 #define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \ argument
42478 #define TX_GAIN_TAB_5__TG_TABLE5__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42479 #define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42480 #define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \ argument
42484 #define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \ argument
42505 #define TX_GAIN_TAB_6__TG_TABLE6__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42506 #define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42507 #define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \ argument
42511 #define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \ argument
42532 #define TX_GAIN_TAB_7__TG_TABLE7__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42533 #define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42534 #define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \ argument
42538 #define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \ argument
42559 #define TX_GAIN_TAB_8__TG_TABLE8__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42560 #define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42561 #define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \ argument
42565 #define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \ argument
42586 #define TX_GAIN_TAB_9__TG_TABLE9__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42587 #define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42588 #define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \ argument
42592 #define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \ argument
42613 #define TX_GAIN_TAB_10__TG_TABLE10__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42614 #define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42615 #define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \ argument
42619 #define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \ argument
42640 #define TX_GAIN_TAB_11__TG_TABLE11__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42641 #define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42642 #define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \ argument
42646 #define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \ argument
42667 #define TX_GAIN_TAB_12__TG_TABLE12__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42668 #define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42669 #define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \ argument
42673 #define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \ argument
42694 #define TX_GAIN_TAB_13__TG_TABLE13__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42695 #define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42696 #define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \ argument
42700 #define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \ argument
42721 #define TX_GAIN_TAB_14__TG_TABLE14__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42722 #define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42723 #define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \ argument
42727 #define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \ argument
42748 #define TX_GAIN_TAB_15__TG_TABLE15__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42749 #define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42750 #define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \ argument
42754 #define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \ argument
42775 #define TX_GAIN_TAB_16__TG_TABLE16__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42776 #define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42777 #define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \ argument
42781 #define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \ argument
42802 #define TX_GAIN_TAB_17__TG_TABLE17__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42803 #define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42804 #define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \ argument
42808 #define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \ argument
42829 #define TX_GAIN_TAB_18__TG_TABLE18__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42830 #define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42831 #define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \ argument
42835 #define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \ argument
42856 #define TX_GAIN_TAB_19__TG_TABLE19__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42857 #define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42858 #define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \ argument
42862 #define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \ argument
42883 #define TX_GAIN_TAB_20__TG_TABLE20__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42884 #define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42885 #define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \ argument
42889 #define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \ argument
42910 #define TX_GAIN_TAB_21__TG_TABLE21__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42911 #define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42912 #define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \ argument
42916 #define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \ argument
42937 #define TX_GAIN_TAB_22__TG_TABLE22__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42938 #define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42939 #define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \ argument
42943 #define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \ argument
42964 #define TX_GAIN_TAB_23__TG_TABLE23__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42965 #define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42966 #define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \ argument
42970 #define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \ argument
42991 #define TX_GAIN_TAB_24__TG_TABLE24__READ(src) (u_int32_t)(src) & 0xffffffffU argument
42992 #define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
42993 #define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \ argument
42997 #define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \ argument
43018 #define TX_GAIN_TAB_25__TG_TABLE25__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43019 #define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43020 #define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \ argument
43024 #define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \ argument
43045 #define TX_GAIN_TAB_26__TG_TABLE26__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43046 #define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43047 #define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \ argument
43051 #define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \ argument
43072 #define TX_GAIN_TAB_27__TG_TABLE27__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43073 #define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43074 #define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \ argument
43078 #define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \ argument
43099 #define TX_GAIN_TAB_28__TG_TABLE28__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43100 #define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43101 #define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \ argument
43105 #define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \ argument
43126 #define TX_GAIN_TAB_29__TG_TABLE29__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43127 #define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43128 #define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \ argument
43132 #define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \ argument
43153 #define TX_GAIN_TAB_30__TG_TABLE30__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43154 #define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43155 #define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \ argument
43159 #define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \ argument
43180 #define TX_GAIN_TAB_31__TG_TABLE31__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43181 #define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43182 #define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \ argument
43186 #define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \ argument
43207 #define TX_GAIN_TAB_32__TG_TABLE32__READ(src) (u_int32_t)(src) & 0xffffffffU argument
43208 #define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
43209 #define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \ argument
43213 #define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \ argument
43234 #define RTT_CTRL__ENA_RADIO_RETENTION__READ(src) (u_int32_t)(src) & 0x00000001U argument
43235 #define RTT_CTRL__ENA_RADIO_RETENTION__WRITE(src) \ argument
43238 #define RTT_CTRL__ENA_RADIO_RETENTION__MODIFY(dst, src) \ argument
43242 #define RTT_CTRL__ENA_RADIO_RETENTION__VERIFY(src) \ argument
43256 #define RTT_CTRL__RESTORE_MASK__READ(src) \ argument
43259 #define RTT_CTRL__RESTORE_MASK__WRITE(src) \ argument
43262 #define RTT_CTRL__RESTORE_MASK__MODIFY(dst, src) \ argument
43266 #define RTT_CTRL__RESTORE_MASK__VERIFY(src) \ argument
43274 #define RTT_CTRL__FORCE_RADIO_RESTORE__READ(src) \ argument
43277 #define RTT_CTRL__FORCE_RADIO_RESTORE__WRITE(src) \ argument
43280 #define RTT_CTRL__FORCE_RADIO_RESTORE__MODIFY(dst, src) \ argument
43284 #define RTT_CTRL__FORCE_RADIO_RESTORE__VERIFY(src) \ argument
43311 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__READ(src) \ argument
43314 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__WRITE(src) \ argument
43317 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__MODIFY(dst, src) \ argument
43321 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ACCESS_0__VERIFY(src) \ argument
43335 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__READ(src) \ argument
43338 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__WRITE(src) \ argument
43341 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__MODIFY(dst, src) \ argument
43345 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_WRITE_0__VERIFY(src) \ argument
43359 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__READ(src) \ argument
43362 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__WRITE(src) \ argument
43365 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__MODIFY(dst, src) \ argument
43369 #define RTT_TABLE_SW_INTF_B0__SW_RTT_TABLE_ADDR_0__VERIFY(src) \ argument
43390 #define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__READ(src) \ argument
43393 #define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__WRITE(src) \ argument
43396 #define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__MODIFY(dst, src) \ argument
43400 #define RTT_TABLE_SW_INTF_1_B0__SW_RTT_TABLE_DATA_0__VERIFY(src) \ argument
43421 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \ argument
43424 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \ argument
43427 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \ argument
43431 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \ argument
43439 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \ argument
43442 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \ argument
43445 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \ argument
43449 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \ argument
43470 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \ argument
43473 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \ argument
43476 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \ argument
43480 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \ argument
43488 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \ argument
43491 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \ argument
43494 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \ argument
43498 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \ argument
43519 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \ argument
43522 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \ argument
43525 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \ argument
43529 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \ argument
43537 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \ argument
43540 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \ argument
43543 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \ argument
43547 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \ argument
43568 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \ argument
43571 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \ argument
43574 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \ argument
43578 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \ argument
43586 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \ argument
43589 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \ argument
43592 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \ argument
43596 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \ argument
43617 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \ argument
43620 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \ argument
43623 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \ argument
43627 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \ argument
43635 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \ argument
43638 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \ argument
43641 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \ argument
43645 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \ argument
43666 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \ argument
43669 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \ argument
43672 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \ argument
43676 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \ argument
43684 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \ argument
43687 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \ argument
43690 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \ argument
43694 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \ argument
43715 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \ argument
43718 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \ argument
43721 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \ argument
43725 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \ argument
43733 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \ argument
43736 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \ argument
43739 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \ argument
43743 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \ argument
43764 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \ argument
43767 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \ argument
43770 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \ argument
43774 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \ argument
43782 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \ argument
43785 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \ argument
43788 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \ argument
43792 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \ argument
43813 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \ argument
43816 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \ argument
43819 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \ argument
43823 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \ argument
43831 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \ argument
43834 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \ argument
43837 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \ argument
43841 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \ argument
43862 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \ argument
43865 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \ argument
43868 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \ argument
43872 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \ argument
43880 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \ argument
43883 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \ argument
43886 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \ argument
43890 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \ argument
43911 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \ argument
43914 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \ argument
43917 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \ argument
43921 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \ argument
43929 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \ argument
43932 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \ argument
43935 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \ argument
43939 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \ argument
43960 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \ argument
43963 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \ argument
43966 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \ argument
43970 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \ argument
43978 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \ argument
43981 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \ argument
43984 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \ argument
43988 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \ argument
44009 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \ argument
44012 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \ argument
44015 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \ argument
44019 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \ argument
44027 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \ argument
44030 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \ argument
44033 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \ argument
44037 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \ argument
44058 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \ argument
44061 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \ argument
44064 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \ argument
44068 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \ argument
44076 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \ argument
44079 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \ argument
44082 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \ argument
44086 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \ argument
44107 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \ argument
44110 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \ argument
44113 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \ argument
44117 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \ argument
44125 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \ argument
44128 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \ argument
44131 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \ argument
44135 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \ argument
44156 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \ argument
44159 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \ argument
44162 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \ argument
44166 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \ argument
44174 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \ argument
44177 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \ argument
44180 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \ argument
44184 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \ argument
44205 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \ argument
44208 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \ argument
44211 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \ argument
44215 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \ argument
44229 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \ argument
44232 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \ argument
44235 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \ argument
44239 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \ argument
44247 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \ argument
44250 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \ argument
44253 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \ argument
44257 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \ argument
44265 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \ argument
44268 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \ argument
44271 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \ argument
44275 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \ argument
44283 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \ argument
44286 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \ argument
44289 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \ argument
44293 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \ argument
44301 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \ argument
44304 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \ argument
44307 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \ argument
44311 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \ argument
44319 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \ argument
44322 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \ argument
44325 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \ argument
44329 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \ argument
44343 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__READ(src) \ argument
44346 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__WRITE(src) \ argument
44349 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__MODIFY(dst, src) \ argument
44353 #define TXIQCAL_CONTROL_0__ENABLE_TXIQ_CALIBRATE__VERIFY(src) \ argument
44380 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \ argument
44383 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \ argument
44386 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \ argument
44390 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \ argument
44398 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \ argument
44401 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \ argument
44404 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \ argument
44408 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \ argument
44416 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \ argument
44419 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \ argument
44422 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \ argument
44426 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \ argument
44434 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \ argument
44437 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \ argument
44440 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \ argument
44444 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \ argument
44465 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \ argument
44468 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \ argument
44471 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \ argument
44475 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \ argument
44483 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \ argument
44486 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \ argument
44489 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \ argument
44493 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \ argument
44501 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \ argument
44504 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \ argument
44507 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \ argument
44511 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \ argument
44532 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \ argument
44535 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \ argument
44538 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \ argument
44542 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \ argument
44550 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \ argument
44553 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \ argument
44556 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \ argument
44560 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \ argument
44581 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \ argument
44584 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \ argument
44587 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \ argument
44591 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \ argument
44599 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \ argument
44602 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \ argument
44605 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \ argument
44609 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \ argument
44630 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \ argument
44633 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \ argument
44636 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \ argument
44640 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \ argument
44648 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \ argument
44651 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \ argument
44654 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \ argument
44658 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \ argument
44679 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \ argument
44682 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \ argument
44685 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \ argument
44689 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \ argument
44697 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \ argument
44700 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \ argument
44703 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \ argument
44707 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \ argument
44728 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \ argument
44731 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \ argument
44734 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \ argument
44738 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \ argument
44746 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \ argument
44749 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \ argument
44752 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \ argument
44756 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \ argument
44777 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \ argument
44780 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \ argument
44783 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \ argument
44787 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \ argument
44795 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \ argument
44798 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \ argument
44801 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \ argument
44805 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \ argument
44826 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \ argument
44829 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \ argument
44832 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \ argument
44836 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \ argument
44844 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \ argument
44847 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \ argument
44850 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \ argument
44854 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \ argument
44875 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \ argument
44878 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \ argument
44881 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \ argument
44885 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \ argument
44893 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \ argument
44896 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \ argument
44899 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \ argument
44903 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \ argument
44924 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \ argument
44927 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \ argument
44930 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \ argument
44934 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \ argument
44942 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \ argument
44945 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \ argument
44948 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \ argument
44952 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \ argument
44960 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \ argument
44963 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \ argument
44966 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \ argument
44970 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \ argument
44978 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \ argument
44981 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \ argument
44984 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \ argument
44988 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \ argument
45009 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \ argument
45012 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \ argument
45015 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \ argument
45019 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \ argument
45027 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \ argument
45030 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \ argument
45033 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \ argument
45037 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \ argument
45045 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \ argument
45048 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \ argument
45051 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \ argument
45055 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \ argument
45063 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \ argument
45066 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \ argument
45069 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \ argument
45073 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \ argument
45094 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \ argument
45097 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \ argument
45100 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \ argument
45104 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \ argument
45112 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \ argument
45115 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \ argument
45118 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \ argument
45122 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \ argument
45130 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \ argument
45133 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \ argument
45136 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \ argument
45140 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \ argument
45148 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \ argument
45151 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \ argument
45154 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \ argument
45158 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \ argument
45179 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \ argument
45182 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \ argument
45185 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \ argument
45189 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \ argument
45197 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \ argument
45200 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \ argument
45203 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \ argument
45207 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \ argument
45215 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \ argument
45218 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \ argument
45221 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \ argument
45225 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \ argument
45233 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \ argument
45236 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \ argument
45239 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \ argument
45243 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \ argument
45264 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \ argument
45267 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \ argument
45270 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \ argument
45274 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \ argument
45282 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \ argument
45285 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \ argument
45288 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \ argument
45292 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \ argument
45300 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \ argument
45303 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \ argument
45306 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \ argument
45310 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \ argument
45318 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \ argument
45321 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \ argument
45324 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \ argument
45328 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \ argument
45349 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \ argument
45352 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \ argument
45355 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \ argument
45359 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \ argument
45367 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \ argument
45370 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \ argument
45373 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \ argument
45377 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \ argument
45385 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \ argument
45388 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \ argument
45391 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \ argument
45395 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \ argument
45403 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \ argument
45406 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \ argument
45409 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \ argument
45413 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \ argument
45434 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \ argument
45437 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \ argument
45440 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \ argument
45444 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \ argument
45465 #define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \ argument
45479 #define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \ argument
45487 #define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \ argument
45495 #define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \ argument
45503 #define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \ argument
45523 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \ argument
45526 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \ argument
45529 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \ argument
45533 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \ argument
45547 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \ argument
45550 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \ argument
45553 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \ argument
45557 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \ argument
45565 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \ argument
45568 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \ argument
45571 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \ argument
45575 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \ argument
45589 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \ argument
45592 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \ argument
45595 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \ argument
45599 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \ argument
45613 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \ argument
45616 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \ argument
45619 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \ argument
45623 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \ argument
45637 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \ argument
45640 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \ argument
45643 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \ argument
45647 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \ argument
45661 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \ argument
45664 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \ argument
45667 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \ argument
45671 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \ argument
45692 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \ argument
45695 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \ argument
45698 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \ argument
45702 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \ argument
45723 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \ argument
45726 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \ argument
45729 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \ argument
45733 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \ argument
45741 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \ argument
45744 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \ argument
45747 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \ argument
45751 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \ argument
45759 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \ argument
45762 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \ argument
45765 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \ argument
45769 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \ argument
45777 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \ argument
45780 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \ argument
45783 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \ argument
45787 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \ argument
45795 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \ argument
45798 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \ argument
45801 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \ argument
45805 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \ argument
45813 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \ argument
45816 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \ argument
45819 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \ argument
45823 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \ argument
45831 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \ argument
45834 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \ argument
45837 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \ argument
45841 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \ argument
45855 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \ argument
45858 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \ argument
45861 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \ argument
45865 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \ argument
45892 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \ argument
45895 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \ argument
45898 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \ argument
45902 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \ argument
45910 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \ argument
45913 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \ argument
45916 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \ argument
45920 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \ argument
45928 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \ argument
45931 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \ argument
45934 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \ argument
45938 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \ argument
45959 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \ argument
45962 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \ argument
45965 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \ argument
45969 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \ argument
45983 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \ argument
45997 #define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \ argument
46011 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \ argument
46025 #define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \ argument
46033 #define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \ argument
46054 #define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \ argument
46062 #define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \ argument
46070 #define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \ argument
46090 #define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \ argument
46110 #define WATCHDOG_STATUS__WATCHDOG_STATUS_1__READ(src) \ argument
46113 #define WATCHDOG_STATUS__WATCHDOG_STATUS_1__WRITE(src) \ argument
46116 #define WATCHDOG_STATUS__WATCHDOG_STATUS_1__MODIFY(dst, src) \ argument
46120 #define WATCHDOG_STATUS__WATCHDOG_STATUS_1__VERIFY(src) \ argument
46128 #define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__READ(src) \ argument
46131 #define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__WRITE(src) \ argument
46134 #define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__MODIFY(dst, src) \ argument
46138 #define WATCHDOG_STATUS__WATCHDOG_TIMEOUT__VERIFY(src) \ argument
46152 #define WATCHDOG_STATUS__WATCHDOG_STATUS_2__READ(src) \ argument
46155 #define WATCHDOG_STATUS__WATCHDOG_STATUS_2__WRITE(src) \ argument
46158 #define WATCHDOG_STATUS__WATCHDOG_STATUS_2__MODIFY(dst, src) \ argument
46162 #define WATCHDOG_STATUS__WATCHDOG_STATUS_2__VERIFY(src) \ argument
46170 #define WATCHDOG_STATUS__WATCHDOG_STATUS_3__READ(src) \ argument
46173 #define WATCHDOG_STATUS__WATCHDOG_STATUS_3__WRITE(src) \ argument
46176 #define WATCHDOG_STATUS__WATCHDOG_STATUS_3__MODIFY(dst, src) \ argument
46180 #define WATCHDOG_STATUS__WATCHDOG_STATUS_3__VERIFY(src) \ argument
46188 #define WATCHDOG_STATUS__WATCHDOG_STATUS_4__READ(src) \ argument
46191 #define WATCHDOG_STATUS__WATCHDOG_STATUS_4__WRITE(src) \ argument
46194 #define WATCHDOG_STATUS__WATCHDOG_STATUS_4__MODIFY(dst, src) \ argument
46198 #define WATCHDOG_STATUS__WATCHDOG_STATUS_4__VERIFY(src) \ argument
46206 #define WATCHDOG_STATUS__WATCHDOG_STATUS_5__READ(src) \ argument
46209 #define WATCHDOG_STATUS__WATCHDOG_STATUS_5__WRITE(src) \ argument
46212 #define WATCHDOG_STATUS__WATCHDOG_STATUS_5__MODIFY(dst, src) \ argument
46216 #define WATCHDOG_STATUS__WATCHDOG_STATUS_5__VERIFY(src) \ argument
46224 #define WATCHDOG_STATUS__WATCHDOG_STATUS_6__READ(src) \ argument
46227 #define WATCHDOG_STATUS__WATCHDOG_STATUS_6__WRITE(src) \ argument
46230 #define WATCHDOG_STATUS__WATCHDOG_STATUS_6__MODIFY(dst, src) \ argument
46234 #define WATCHDOG_STATUS__WATCHDOG_STATUS_6__VERIFY(src) \ argument
46242 #define WATCHDOG_STATUS__WATCHDOG_STATUS_7__READ(src) \ argument
46245 #define WATCHDOG_STATUS__WATCHDOG_STATUS_7__WRITE(src) \ argument
46248 #define WATCHDOG_STATUS__WATCHDOG_STATUS_7__MODIFY(dst, src) \ argument
46252 #define WATCHDOG_STATUS__WATCHDOG_STATUS_7__VERIFY(src) \ argument
46260 #define WATCHDOG_STATUS__WATCHDOG_STATUS_8__READ(src) \ argument
46263 #define WATCHDOG_STATUS__WATCHDOG_STATUS_8__WRITE(src) \ argument
46266 #define WATCHDOG_STATUS__WATCHDOG_STATUS_8__MODIFY(dst, src) \ argument
46270 #define WATCHDOG_STATUS__WATCHDOG_STATUS_8__VERIFY(src) \ argument
46292 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__READ(src) \ argument
46295 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__WRITE(src) \ argument
46298 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__MODIFY(dst, src) \ argument
46302 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_NON_IDLE__VERIFY(src) \ argument
46316 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__READ(src) \ argument
46319 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__WRITE(src) \ argument
46322 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__MODIFY(dst, src) \ argument
46326 #define WATCHDOG_CTRL_1__ENABLE_WATCHDOG_TIMEOUT_RESET_IDLE__VERIFY(src) \ argument
46341 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__READ(src) \ argument
46344 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__WRITE(src) \ argument
46347 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__MODIFY(dst, src) \ argument
46351 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_NON_IDLE_LIMIT__VERIFY(src) \ argument
46359 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__READ(src) \ argument
46362 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__WRITE(src) \ argument
46365 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__MODIFY(dst, src) \ argument
46369 #define WATCHDOG_CTRL_1__WATCHDOG_TIMEOUT_RESET_IDLE_LIMIT__VERIFY(src) \ argument
46390 #define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \ argument
46393 #define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \ argument
46396 #define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \ argument
46400 #define WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \ argument
46414 #define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__READ(src) \ argument
46417 #define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__WRITE(src) \ argument
46420 #define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__MODIFY(dst, src) \ argument
46424 #define WATCHDOG_CTRL_2__WATCHDOG_TIMEOUT_RESET_ENA__VERIFY(src) \ argument
46438 #define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__READ(src) \ argument
46441 #define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__WRITE(src) \ argument
46444 #define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__MODIFY(dst, src) \ argument
46448 #define WATCHDOG_CTRL_2__WATCHDOG_IRQ_ENA__VERIFY(src) \ argument
46475 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \ argument
46478 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \ argument
46481 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \ argument
46485 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \ argument
46499 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \ argument
46502 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \ argument
46505 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \ argument
46509 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \ argument
46536 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \ argument
46539 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \ argument
46542 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \ argument
46546 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \ argument
46573 #define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \ argument
46576 #define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \ argument
46579 #define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \ argument
46583 #define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \ argument
46597 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \ argument
46600 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \ argument
46603 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \ argument
46607 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \ argument
46621 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \ argument
46624 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \ argument
46627 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \ argument
46631 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \ argument
46645 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \ argument
46648 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \ argument
46651 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \ argument
46655 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \ argument
46669 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \ argument
46672 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \ argument
46675 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \ argument
46679 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \ argument
46693 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \ argument
46696 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \ argument
46699 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \ argument
46703 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \ argument
46717 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \ argument
46720 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \ argument
46723 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \ argument
46727 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \ argument
46741 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \ argument
46744 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \ argument
46747 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \ argument
46751 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \ argument
46778 #define ECO_CTRL__ECO_CTRL__READ(src) (u_int32_t)(src) & 0x000000ffU argument
46779 #define ECO_CTRL__ECO_CTRL__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
46780 #define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \ argument
46784 #define ECO_CTRL__ECO_CTRL__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
46803 #define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__READ(src) \ argument
46806 #define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__WRITE(src) \ argument
46809 #define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__MODIFY(dst, src) \ argument
46813 #define TABLES_INTF_ADDR_B0__TABLES_ADDR_0__VERIFY(src) \ argument
46821 #define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__READ(src) \ argument
46824 #define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__WRITE(src) \ argument
46827 #define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__MODIFY(dst, src) \ argument
46831 #define TABLES_INTF_ADDR_B0__ADDR_AUTO_INCR_0__VERIFY(src) \ argument
46858 #define TABLES_INTF_DATA_B0__TABLES_DATA_0__READ(src) \ argument
46861 #define TABLES_INTF_DATA_B0__TABLES_DATA_0__WRITE(src) \ argument
46864 #define TABLES_INTF_DATA_B0__TABLES_DATA_0__MODIFY(dst, src) \ argument
46868 #define TABLES_INTF_DATA_B0__TABLES_DATA_0__VERIFY(src) \ argument
46889 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \ argument
46892 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \ argument
46895 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \ argument
46899 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \ argument
46907 #define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \ argument
46928 #define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src) (u_int32_t)(src) & 0x000000ffU argument
46934 #define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \ argument
46942 #define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \ argument
46962 #define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \ argument
46982 #define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \ argument
47002 #define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \ argument
47022 #define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \ argument
47042 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \ argument
47045 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \ argument
47048 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \ argument
47052 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \ argument
47066 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \ argument
47069 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \ argument
47072 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \ argument
47076 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \ argument
47084 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \ argument
47087 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \ argument
47090 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \ argument
47094 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \ argument
47102 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \ argument
47105 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \ argument
47108 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \ argument
47112 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \ argument
47133 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \ argument
47136 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \ argument
47139 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \ argument
47143 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \ argument
47151 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \ argument
47154 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \ argument
47157 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \ argument
47161 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \ argument
47169 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \ argument
47172 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \ argument
47175 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \ argument
47179 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \ argument
47187 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \ argument
47190 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \ argument
47193 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \ argument
47197 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \ argument
47218 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \ argument
47221 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \ argument
47224 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ argument
47228 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \ argument
47236 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \ argument
47239 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \ argument
47242 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ argument
47246 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \ argument
47254 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \ argument
47257 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \ argument
47260 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \ argument
47264 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \ argument
47272 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \ argument
47275 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \ argument
47278 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \ argument
47282 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \ argument
47303 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \ argument
47306 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \ argument
47309 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \ argument
47313 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \ argument
47327 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \ argument
47330 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \ argument
47333 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \ argument
47337 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \ argument
47351 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \ argument
47354 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \ argument
47357 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \ argument
47361 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \ argument
47369 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \ argument
47372 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \ argument
47375 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \ argument
47379 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \ argument
47400 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \ argument
47403 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \ argument
47406 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \ argument
47410 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \ argument
47424 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \ argument
47427 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \ argument
47430 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \ argument
47434 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \ argument
47448 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \ argument
47451 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \ argument
47454 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \ argument
47458 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \ argument
47472 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \ argument
47475 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \ argument
47478 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \ argument
47482 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \ argument
47490 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \ argument
47493 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \ argument
47496 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \ argument
47500 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \ argument
47508 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \ argument
47511 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \ argument
47514 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \ argument
47518 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \ argument
47526 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \ argument
47529 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \ argument
47532 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \ argument
47536 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \ argument
47563 #define PA_GAIN123_B1__PA_GAIN1_1__READ(src) (u_int32_t)(src) & 0x000003ffU argument
47564 #define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
47565 #define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \ argument
47569 #define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \ argument
47577 #define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \ argument
47580 #define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \ argument
47583 #define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \ argument
47587 #define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \ argument
47595 #define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \ argument
47598 #define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \ argument
47601 #define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \ argument
47605 #define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \ argument
47626 #define PA_GAIN45_B1__PA_GAIN4_1__READ(src) (u_int32_t)(src) & 0x000003ffU argument
47627 #define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
47628 #define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \ argument
47632 #define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \ argument
47640 #define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \ argument
47643 #define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \ argument
47646 #define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \ argument
47650 #define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \ argument
47658 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \ argument
47661 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \ argument
47664 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \ argument
47668 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \ argument
47689 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \ argument
47692 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \ argument
47695 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \ argument
47699 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \ argument
47720 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \ argument
47723 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \ argument
47726 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \ argument
47730 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \ argument
47751 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \ argument
47754 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \ argument
47757 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \ argument
47761 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \ argument
47782 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \ argument
47785 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \ argument
47788 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \ argument
47792 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \ argument
47813 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \ argument
47816 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \ argument
47819 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \ argument
47823 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \ argument
47844 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \ argument
47847 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \ argument
47850 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \ argument
47854 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \ argument
47875 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \ argument
47878 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \ argument
47881 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \ argument
47885 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \ argument
47906 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \ argument
47909 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \ argument
47912 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \ argument
47916 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \ argument
47937 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU argument
47938 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) argument
47939 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ argument
47943 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ argument
47964 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ argument
47984 #define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__READ(src) \ argument
47987 #define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__WRITE(src) \ argument
47990 #define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__MODIFY(dst, src) \ argument
47994 #define CHN1_TABLES_INTF_ADDR__CHN1_TABLES_ADDR__VERIFY(src) \ argument
48002 #define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__READ(src) \ argument
48005 #define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__WRITE(src) \ argument
48008 #define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__MODIFY(dst, src) \ argument
48012 #define CHN1_TABLES_INTF_ADDR__CHN1_ADDR_AUTO_INCR__VERIFY(src) \ argument
48039 #define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__READ(src) \ argument
48042 #define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__WRITE(src) \ argument
48045 #define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__MODIFY(dst, src) \ argument
48049 #define CHN1_TABLES_INTF_DATA__CHN1_TABLES_DATA__VERIFY(src) \ argument
48070 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \ argument
48073 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \ argument
48076 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \ argument
48080 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \ argument
48088 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \ argument
48091 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \ argument
48094 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \ argument
48098 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \ argument
48106 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \ argument
48109 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \ argument
48112 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \ argument
48116 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \ argument
48130 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \ argument
48133 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \ argument
48136 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \ argument
48140 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \ argument
48154 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \ argument
48157 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \ argument
48160 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \ argument
48164 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \ argument
48172 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \ argument
48175 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \ argument
48178 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \ argument
48182 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \ argument
48203 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \ argument
48206 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \ argument
48209 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \ argument
48213 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \ argument
48221 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \ argument
48224 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \ argument
48227 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \ argument
48231 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \ argument
48239 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \ argument
48242 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \ argument
48245 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \ argument
48249 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \ argument
48257 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \ argument
48260 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \ argument
48263 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \ argument
48267 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \ argument
48275 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \ argument
48278 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \ argument
48281 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \ argument
48285 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \ argument
48306 #define CCA_B1__CF_MAXCCAPWR_1__READ(src) (u_int32_t)(src) & 0x000001ffU argument
48307 #define CCA_B1__CF_MAXCCAPWR_1__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) argument
48308 #define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \ argument
48312 #define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \ argument
48320 #define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) argument
48339 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \ argument
48342 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \ argument
48345 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \ argument
48349 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \ argument
48357 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \ argument
48360 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \ argument
48363 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \ argument
48367 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \ argument
48388 #define RSSI_B1__RSSI_1__READ(src) (u_int32_t)(src) & 0x000000ffU argument
48394 #define RSSI_B1__RSSI_EXT_1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
48412 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \ argument
48420 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \ argument
48428 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \ argument
48436 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \ argument
48456 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \ argument
48464 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \ argument
48472 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \ argument
48492 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \ argument
48500 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \ argument
48508 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \ argument
48528 #define DC_CAL_STATUS_B1__OFFSETC1I_1__READ(src) (u_int32_t)(src) & 0x0000001fU argument
48534 #define DC_CAL_STATUS_B1__OFFSETC1Q_1__READ(src) \ argument
48542 #define DC_CAL_STATUS_B1__OFFSETC2I_1__READ(src) \ argument
48550 #define DC_CAL_STATUS_B1__OFFSETC2Q_1__READ(src) \ argument
48558 #define DC_CAL_STATUS_B1__OFFSETC3I_1__READ(src) \ argument
48566 #define DC_CAL_STATUS_B1__OFFSETC3Q_1__READ(src) \ argument
48586 #define RX_OCGAIN2__GAIN_ENTRY2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48587 #define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48588 #define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \ argument
48592 #define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \ argument
48613 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \ argument
48616 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \ argument
48619 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \ argument
48623 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \ argument
48631 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \ argument
48634 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \ argument
48637 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \ argument
48641 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \ argument
48649 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \ argument
48652 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \ argument
48655 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \ argument
48659 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \ argument
48667 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \ argument
48670 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \ argument
48673 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \ argument
48677 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \ argument
48685 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \ argument
48688 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \ argument
48691 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \ argument
48695 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \ argument
48703 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \ argument
48706 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \ argument
48709 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \ argument
48713 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \ argument
48734 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \ argument
48737 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \ argument
48740 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \ argument
48744 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \ argument
48752 #define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \ argument
48773 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \ argument
48776 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \ argument
48779 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \ argument
48783 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \ argument
48797 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \ argument
48800 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \ argument
48803 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \ argument
48807 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \ argument
48815 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \ argument
48818 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \ argument
48821 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \ argument
48825 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \ argument
48846 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48847 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48848 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ argument
48852 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
48871 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48872 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48873 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ argument
48877 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
48896 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48897 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48898 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ argument
48902 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
48921 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48922 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48923 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ argument
48927 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
48946 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48947 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48948 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ argument
48952 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ argument
48973 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
48974 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
48975 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ argument
48979 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ argument
49000 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
49001 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
49002 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ argument
49006 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ argument
49027 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
49028 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
49029 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ argument
49033 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ argument
49054 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU argument
49055 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
49056 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ argument
49060 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
49066 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ argument
49069 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ argument
49072 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ argument
49076 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ argument
49084 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ argument
49087 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ argument
49090 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ argument
49094 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ argument
49102 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
49103 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
49104 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \ argument
49108 #define CL_TAB__BB_GAIN__VERIFY(src) \ argument
49129 #define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \ argument
49137 #define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \ argument
49145 #define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \ argument
49153 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \ argument
49167 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \ argument
49193 #define TPC_4_B1__PD_AVG_VALID_1__READ(src) (u_int32_t)(src) & 0x00000001U argument
49205 #define TPC_4_B1__PD_AVG_OUT_1__READ(src) \ argument
49213 #define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) argument
49219 #define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \ argument
49227 #define TPC_4_B1__RATE_SENT_1__READ(src) \ argument
49247 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \ argument
49250 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \ argument
49253 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \ argument
49257 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \ argument
49265 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \ argument
49268 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \ argument
49271 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \ argument
49275 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \ argument
49283 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \ argument
49286 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \ argument
49289 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \ argument
49293 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \ argument
49301 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \ argument
49304 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \ argument
49307 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \ argument
49311 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \ argument
49332 #define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src) (u_int32_t)(src) & 0x0000003fU argument
49333 #define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \ argument
49336 #define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \ argument
49340 #define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \ argument
49348 #define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \ argument
49351 #define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \ argument
49354 #define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \ argument
49358 #define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \ argument
49366 #define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \ argument
49369 #define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \ argument
49372 #define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \ argument
49376 #define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \ argument
49384 #define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \ argument
49387 #define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \ argument
49390 #define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \ argument
49394 #define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \ argument
49402 #define TPC_6_B1__ERROR_EST_MODE__READ(src) \ argument
49405 #define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \ argument
49408 #define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \ argument
49412 #define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \ argument
49420 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \ argument
49423 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \ argument
49426 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ argument
49430 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \ argument
49451 #define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \ argument
49454 #define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \ argument
49457 #define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \ argument
49461 #define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \ argument
49469 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \ argument
49472 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \ argument
49475 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \ argument
49479 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \ argument
49500 #define TPC_19_B1__ALPHA_THERM_1__READ(src) (u_int32_t)(src) & 0x000000ffU argument
49501 #define TPC_19_B1__ALPHA_THERM_1__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
49502 #define TPC_19_B1__ALPHA_THERM_1__MODIFY(dst, src) \ argument
49506 #define TPC_19_B1__ALPHA_THERM_1__VERIFY(src) \ argument
49514 #define TPC_19_B1__ALPHA_THERM_PAL_ON_1__READ(src) \ argument
49517 #define TPC_19_B1__ALPHA_THERM_PAL_ON_1__WRITE(src) \ argument
49520 #define TPC_19_B1__ALPHA_THERM_PAL_ON_1__MODIFY(dst, src) \ argument
49524 #define TPC_19_B1__ALPHA_THERM_PAL_ON_1__VERIFY(src) \ argument
49532 #define TPC_19_B1__ALPHA_VOLT_1__READ(src) \ argument
49535 #define TPC_19_B1__ALPHA_VOLT_1__WRITE(src) \ argument
49538 #define TPC_19_B1__ALPHA_VOLT_1__MODIFY(dst, src) \ argument
49542 #define TPC_19_B1__ALPHA_VOLT_1__VERIFY(src) \ argument
49550 #define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__READ(src) \ argument
49553 #define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__WRITE(src) \ argument
49556 #define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__MODIFY(dst, src) \ argument
49560 #define TPC_19_B1__ALPHA_VOLT_PAL_ON_1__VERIFY(src) \ argument
49581 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
49582 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ argument
49586 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ argument
49606 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__READ(src) \ argument
49609 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__WRITE(src) \ argument
49612 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__MODIFY(dst, src) \ argument
49616 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ACCESS_1__VERIFY(src) \ argument
49630 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__READ(src) \ argument
49633 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__WRITE(src) \ argument
49636 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__MODIFY(dst, src) \ argument
49640 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_WRITE_1__VERIFY(src) \ argument
49654 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__READ(src) \ argument
49657 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__WRITE(src) \ argument
49660 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__MODIFY(dst, src) \ argument
49664 #define RTT_TABLE_SW_INTF_B1__SW_RTT_TABLE_ADDR_1__VERIFY(src) \ argument
49685 #define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__READ(src) \ argument
49688 #define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__WRITE(src) \ argument
49691 #define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__MODIFY(dst, src) \ argument
49695 #define RTT_TABLE_SW_INTF_1_B1__SW_RTT_TABLE_DATA_1__VERIFY(src) \ argument
49716 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \ argument
49719 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \ argument
49722 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \ argument
49726 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \ argument
49734 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \ argument
49737 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \ argument
49740 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \ argument
49744 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \ argument
49765 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \ argument
49768 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \ argument
49771 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \ argument
49775 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \ argument
49783 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \ argument
49786 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \ argument
49789 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \ argument
49793 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \ argument
49814 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \ argument
49817 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \ argument
49820 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \ argument
49824 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \ argument
49832 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \ argument
49835 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \ argument
49838 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \ argument
49842 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \ argument
49863 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \ argument
49866 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \ argument
49869 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \ argument
49873 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \ argument
49881 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \ argument
49884 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \ argument
49887 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \ argument
49891 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \ argument
49912 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \ argument
49915 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \ argument
49918 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \ argument
49922 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \ argument
49930 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \ argument
49933 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \ argument
49936 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \ argument
49940 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \ argument
49961 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \ argument
49964 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \ argument
49967 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \ argument
49971 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \ argument
49979 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \ argument
49982 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \ argument
49985 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \ argument
49989 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \ argument
50010 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \ argument
50013 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \ argument
50016 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \ argument
50020 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \ argument
50028 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \ argument
50031 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \ argument
50034 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \ argument
50038 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \ argument
50059 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \ argument
50062 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \ argument
50065 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \ argument
50069 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \ argument
50077 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \ argument
50080 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \ argument
50083 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \ argument
50087 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \ argument
50108 #define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \ argument
50122 #define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \ argument
50130 #define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \ argument
50138 #define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \ argument
50146 #define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \ argument
50166 #define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__READ(src) \ argument
50169 #define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__WRITE(src) \ argument
50172 #define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__MODIFY(dst, src) \ argument
50176 #define TABLES_INTF_ADDR_B1__TABLES_ADDR_1__VERIFY(src) \ argument
50184 #define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__READ(src) \ argument
50187 #define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__WRITE(src) \ argument
50190 #define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__MODIFY(dst, src) \ argument
50194 #define TABLES_INTF_ADDR_B1__ADDR_AUTO_INCR_1__VERIFY(src) \ argument
50221 #define TABLES_INTF_DATA_B1__TABLES_DATA_1__READ(src) \ argument
50224 #define TABLES_INTF_DATA_B1__TABLES_DATA_1__WRITE(src) \ argument
50227 #define TABLES_INTF_DATA_B1__TABLES_DATA_1__MODIFY(dst, src) \ argument
50231 #define TABLES_INTF_DATA_B1__TABLES_DATA_1__VERIFY(src) \ argument
50252 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \ argument
50255 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \ argument
50258 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \ argument
50262 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \ argument
50270 #define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \ argument
50291 #define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src) (u_int32_t)(src) & 0x000000ffU argument
50297 #define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \ argument
50305 #define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \ argument
50325 #define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \ argument
50345 #define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \ argument
50365 #define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \ argument
50385 #define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \ argument
50405 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \ argument
50408 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \ argument
50411 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \ argument
50415 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \ argument
50429 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \ argument
50432 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \ argument
50435 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \ argument
50439 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \ argument
50447 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \ argument
50450 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \ argument
50453 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \ argument
50457 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \ argument
50465 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \ argument
50468 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \ argument
50471 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \ argument
50475 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \ argument
50496 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \ argument
50499 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \ argument
50502 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \ argument
50506 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \ argument
50514 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \ argument
50517 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \ argument
50520 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \ argument
50524 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \ argument
50532 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \ argument
50535 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \ argument
50538 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \ argument
50542 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \ argument
50550 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \ argument
50553 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \ argument
50556 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \ argument
50560 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \ argument
50581 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \ argument
50584 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \ argument
50587 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ argument
50591 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \ argument
50599 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \ argument
50602 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \ argument
50605 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ argument
50609 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \ argument
50617 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \ argument
50620 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \ argument
50623 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \ argument
50627 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \ argument
50635 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \ argument
50638 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \ argument
50641 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \ argument
50645 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \ argument
50666 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \ argument
50669 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \ argument
50672 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \ argument
50676 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \ argument
50690 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \ argument
50693 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \ argument
50696 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \ argument
50700 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \ argument
50714 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \ argument
50717 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \ argument
50720 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \ argument
50724 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \ argument
50732 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \ argument
50735 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \ argument
50738 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \ argument
50742 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \ argument
50763 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \ argument
50766 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \ argument
50769 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \ argument
50773 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \ argument
50787 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \ argument
50790 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \ argument
50793 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \ argument
50797 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \ argument
50811 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \ argument
50814 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \ argument
50817 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \ argument
50821 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \ argument
50835 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \ argument
50838 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \ argument
50841 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \ argument
50845 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \ argument
50853 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \ argument
50856 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \ argument
50859 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \ argument
50863 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \ argument
50871 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \ argument
50874 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \ argument
50877 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \ argument
50881 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \ argument
50889 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \ argument
50892 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \ argument
50895 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \ argument
50899 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \ argument
50926 #define PA_GAIN123_B2__PA_GAIN1_2__READ(src) (u_int32_t)(src) & 0x000003ffU argument
50927 #define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
50928 #define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \ argument
50932 #define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \ argument
50940 #define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \ argument
50943 #define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \ argument
50946 #define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \ argument
50950 #define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \ argument
50958 #define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \ argument
50961 #define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \ argument
50964 #define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \ argument
50968 #define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \ argument
50989 #define PA_GAIN45_B2__PA_GAIN4_2__READ(src) (u_int32_t)(src) & 0x000003ffU argument
50990 #define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
50991 #define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \ argument
50995 #define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \ argument
51003 #define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \ argument
51006 #define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \ argument
51009 #define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \ argument
51013 #define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \ argument
51021 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \ argument
51024 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \ argument
51027 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \ argument
51031 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \ argument
51052 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \ argument
51055 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \ argument
51058 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \ argument
51062 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \ argument
51083 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \ argument
51086 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \ argument
51089 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \ argument
51093 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \ argument
51114 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \ argument
51117 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \ argument
51120 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \ argument
51124 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \ argument
51145 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \ argument
51148 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \ argument
51151 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \ argument
51155 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \ argument
51176 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \ argument
51179 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \ argument
51182 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \ argument
51186 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \ argument
51207 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \ argument
51210 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \ argument
51213 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \ argument
51217 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \ argument
51238 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \ argument
51241 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \ argument
51244 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \ argument
51248 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \ argument
51269 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \ argument
51272 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \ argument
51275 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \ argument
51279 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \ argument
51300 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU argument
51301 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU) argument
51302 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \ argument
51306 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \ argument
51327 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \ argument
51347 #define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__READ(src) \ argument
51350 #define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__WRITE(src) \ argument
51353 #define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__MODIFY(dst, src) \ argument
51357 #define CHN2_TABLES_INTF_ADDR__CHN2_TABLES_ADDR__VERIFY(src) \ argument
51365 #define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__READ(src) \ argument
51368 #define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__WRITE(src) \ argument
51371 #define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__MODIFY(dst, src) \ argument
51375 #define CHN2_TABLES_INTF_ADDR__CHN2_ADDR_AUTO_INCR__VERIFY(src) \ argument
51402 #define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__READ(src) \ argument
51405 #define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__WRITE(src) \ argument
51408 #define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__MODIFY(dst, src) \ argument
51412 #define CHN2_TABLES_INTF_DATA__CHN2_TABLES_DATA__VERIFY(src) \ argument
51433 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \ argument
51436 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \ argument
51439 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \ argument
51443 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \ argument
51451 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \ argument
51454 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \ argument
51457 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \ argument
51461 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \ argument
51469 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \ argument
51472 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \ argument
51475 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \ argument
51479 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \ argument
51493 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \ argument
51496 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \ argument
51499 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \ argument
51503 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \ argument
51517 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \ argument
51520 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \ argument
51523 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \ argument
51527 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \ argument
51535 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \ argument
51538 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \ argument
51541 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \ argument
51545 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \ argument
51566 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \ argument
51569 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \ argument
51572 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \ argument
51576 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \ argument
51584 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \ argument
51587 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \ argument
51590 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \ argument
51594 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \ argument
51602 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \ argument
51605 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \ argument
51608 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \ argument
51612 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \ argument
51620 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \ argument
51623 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \ argument
51626 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \ argument
51630 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \ argument
51638 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \ argument
51641 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \ argument
51644 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \ argument
51648 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \ argument
51669 #define CCA_B2__CF_MAXCCAPWR_2__READ(src) (u_int32_t)(src) & 0x000001ffU argument
51670 #define CCA_B2__CF_MAXCCAPWR_2__WRITE(src) ((u_int32_t)(src) & 0x000001ffU) argument
51671 #define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \ argument
51675 #define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \ argument
51683 #define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20) argument
51702 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \ argument
51705 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \ argument
51708 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \ argument
51712 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \ argument
51720 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \ argument
51723 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \ argument
51726 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \ argument
51730 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \ argument
51751 #define RSSI_B2__RSSI_2__READ(src) (u_int32_t)(src) & 0x000000ffU argument
51757 #define RSSI_B2__RSSI_EXT_2__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
51775 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \ argument
51783 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \ argument
51791 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \ argument
51811 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \ argument
51819 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \ argument
51827 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \ argument
51847 #define DC_CAL_STATUS_B2__OFFSETC1I_2__READ(src) (u_int32_t)(src) & 0x0000001fU argument
51853 #define DC_CAL_STATUS_B2__OFFSETC1Q_2__READ(src) \ argument
51861 #define DC_CAL_STATUS_B2__OFFSETC2I_2__READ(src) \ argument
51869 #define DC_CAL_STATUS_B2__OFFSETC2Q_2__READ(src) \ argument
51877 #define DC_CAL_STATUS_B2__OFFSETC3I_2__READ(src) \ argument
51885 #define DC_CAL_STATUS_B2__OFFSETC3Q_2__READ(src) \ argument
51905 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \ argument
51908 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \ argument
51911 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \ argument
51915 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \ argument
51923 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \ argument
51926 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \ argument
51929 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \ argument
51933 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \ argument
51941 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \ argument
51944 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \ argument
51947 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \ argument
51951 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \ argument
51959 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \ argument
51962 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \ argument
51965 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \ argument
51969 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \ argument
51977 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \ argument
51980 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \ argument
51983 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \ argument
51987 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \ argument
51995 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \ argument
51998 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \ argument
52001 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \ argument
52005 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \ argument
52026 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \ argument
52029 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \ argument
52032 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \ argument
52036 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \ argument
52044 #define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \ argument
52065 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \ argument
52068 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \ argument
52071 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \ argument
52075 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \ argument
52089 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \ argument
52092 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \ argument
52095 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \ argument
52099 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \ argument
52107 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \ argument
52110 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \ argument
52113 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \ argument
52117 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \ argument
52138 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52139 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52140 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \ argument
52144 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
52163 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52164 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52165 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \ argument
52169 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
52188 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52189 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52190 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \ argument
52194 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
52213 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52214 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52215 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \ argument
52219 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
52238 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52239 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52240 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \ argument
52244 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \ argument
52265 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52266 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52267 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \ argument
52271 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \ argument
52292 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52293 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52294 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \ argument
52298 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \ argument
52319 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU argument
52320 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52321 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \ argument
52325 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \ argument
52346 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU argument
52347 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
52348 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \ argument
52352 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
52358 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \ argument
52361 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \ argument
52364 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \ argument
52368 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \ argument
52376 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \ argument
52379 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \ argument
52382 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \ argument
52386 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \ argument
52394 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
52395 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
52396 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \ argument
52400 #define CL_TAB__BB_GAIN__VERIFY(src) \ argument
52421 #define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \ argument
52429 #define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \ argument
52437 #define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \ argument
52445 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \ argument
52459 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \ argument
52485 #define TPC_4_B2__PD_AVG_VALID_2__READ(src) (u_int32_t)(src) & 0x00000001U argument
52497 #define TPC_4_B2__PD_AVG_OUT_2__READ(src) \ argument
52505 #define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9) argument
52511 #define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \ argument
52519 #define TPC_4_B2__RATE_SENT_2__READ(src) \ argument
52539 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \ argument
52542 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \ argument
52545 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \ argument
52549 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \ argument
52557 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \ argument
52560 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \ argument
52563 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \ argument
52567 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \ argument
52575 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \ argument
52578 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \ argument
52581 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \ argument
52585 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \ argument
52593 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \ argument
52596 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \ argument
52599 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \ argument
52603 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \ argument
52624 #define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src) (u_int32_t)(src) & 0x0000003fU argument
52625 #define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \ argument
52628 #define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \ argument
52632 #define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \ argument
52640 #define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \ argument
52643 #define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \ argument
52646 #define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \ argument
52650 #define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \ argument
52658 #define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \ argument
52661 #define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \ argument
52664 #define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \ argument
52668 #define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \ argument
52676 #define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \ argument
52679 #define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \ argument
52682 #define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \ argument
52686 #define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \ argument
52694 #define TPC_6_B2__ERROR_EST_MODE__READ(src) \ argument
52697 #define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \ argument
52700 #define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \ argument
52704 #define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \ argument
52712 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \ argument
52715 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \ argument
52718 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \ argument
52722 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \ argument
52743 #define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \ argument
52746 #define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \ argument
52749 #define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \ argument
52753 #define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \ argument
52761 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \ argument
52764 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \ argument
52767 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \ argument
52771 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \ argument
52792 #define TPC_19_B2__ALPHA_THERM_2__READ(src) (u_int32_t)(src) & 0x000000ffU argument
52793 #define TPC_19_B2__ALPHA_THERM_2__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
52794 #define TPC_19_B2__ALPHA_THERM_2__MODIFY(dst, src) \ argument
52798 #define TPC_19_B2__ALPHA_THERM_2__VERIFY(src) \ argument
52806 #define TPC_19_B2__ALPHA_THERM_PAL_ON_2__READ(src) \ argument
52809 #define TPC_19_B2__ALPHA_THERM_PAL_ON_2__WRITE(src) \ argument
52812 #define TPC_19_B2__ALPHA_THERM_PAL_ON_2__MODIFY(dst, src) \ argument
52816 #define TPC_19_B2__ALPHA_THERM_PAL_ON_2__VERIFY(src) \ argument
52824 #define TPC_19_B2__ALPHA_VOLT_2__READ(src) \ argument
52827 #define TPC_19_B2__ALPHA_VOLT_2__WRITE(src) \ argument
52830 #define TPC_19_B2__ALPHA_VOLT_2__MODIFY(dst, src) \ argument
52834 #define TPC_19_B2__ALPHA_VOLT_2__VERIFY(src) \ argument
52842 #define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__READ(src) \ argument
52845 #define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__WRITE(src) \ argument
52848 #define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__MODIFY(dst, src) \ argument
52852 #define TPC_19_B2__ALPHA_VOLT_PAL_ON_2__VERIFY(src) \ argument
52873 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
52874 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \ argument
52878 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \ argument
52898 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__READ(src) \ argument
52901 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__WRITE(src) \ argument
52904 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__MODIFY(dst, src) \ argument
52908 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ACCESS_2__VERIFY(src) \ argument
52922 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__READ(src) \ argument
52925 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__WRITE(src) \ argument
52928 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__MODIFY(dst, src) \ argument
52932 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_WRITE_2__VERIFY(src) \ argument
52946 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__READ(src) \ argument
52949 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__WRITE(src) \ argument
52952 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__MODIFY(dst, src) \ argument
52956 #define RTT_TABLE_SW_INTF_B2__SW_RTT_TABLE_ADDR_2__VERIFY(src) \ argument
52977 #define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__READ(src) \ argument
52980 #define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__WRITE(src) \ argument
52983 #define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__MODIFY(dst, src) \ argument
52987 #define RTT_TABLE_SW_INTF_1_B2__SW_RTT_TABLE_DATA_2__VERIFY(src) \ argument
53008 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \ argument
53011 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \ argument
53014 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \ argument
53018 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \ argument
53026 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \ argument
53029 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \ argument
53032 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \ argument
53036 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \ argument
53057 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \ argument
53060 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \ argument
53063 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \ argument
53067 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \ argument
53075 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \ argument
53078 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \ argument
53081 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \ argument
53085 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \ argument
53106 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \ argument
53109 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \ argument
53112 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \ argument
53116 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \ argument
53124 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \ argument
53127 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \ argument
53130 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \ argument
53134 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \ argument
53155 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \ argument
53158 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \ argument
53161 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \ argument
53165 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \ argument
53173 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \ argument
53176 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \ argument
53179 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \ argument
53183 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \ argument
53204 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \ argument
53207 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \ argument
53210 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \ argument
53214 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \ argument
53222 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \ argument
53225 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \ argument
53228 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \ argument
53232 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \ argument
53253 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \ argument
53256 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \ argument
53259 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \ argument
53263 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \ argument
53271 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \ argument
53274 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \ argument
53277 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \ argument
53281 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \ argument
53302 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \ argument
53305 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \ argument
53308 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \ argument
53312 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \ argument
53320 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \ argument
53323 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \ argument
53326 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \ argument
53330 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \ argument
53351 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \ argument
53354 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \ argument
53357 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \ argument
53361 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \ argument
53369 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \ argument
53372 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \ argument
53375 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \ argument
53379 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \ argument
53400 #define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \ argument
53414 #define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \ argument
53422 #define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \ argument
53430 #define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \ argument
53438 #define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \ argument
53458 #define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__READ(src) \ argument
53461 #define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__WRITE(src) \ argument
53464 #define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__MODIFY(dst, src) \ argument
53468 #define TABLES_INTF_ADDR_B2__TABLES_ADDR_2__VERIFY(src) \ argument
53476 #define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__READ(src) \ argument
53479 #define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__WRITE(src) \ argument
53482 #define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__MODIFY(dst, src) \ argument
53486 #define TABLES_INTF_ADDR_B2__ADDR_AUTO_INCR_2__VERIFY(src) \ argument
53513 #define TABLES_INTF_DATA_B2__TABLES_DATA_2__READ(src) \ argument
53516 #define TABLES_INTF_DATA_B2__TABLES_DATA_2__WRITE(src) \ argument
53519 #define TABLES_INTF_DATA_B2__TABLES_DATA_2__MODIFY(dst, src) \ argument
53523 #define TABLES_INTF_DATA_B2__TABLES_DATA_2__VERIFY(src) \ argument
53544 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U argument
53564 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U argument
53584 #define RSSI_B3__RSSI_3__READ(src) (u_int32_t)(src) & 0x000000ffU argument
53590 #define RSSI_B3__RSSI_EXT_3__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
53608 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U argument
53642 #define MAC_PCU_BUF__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
53643 #define MAC_PCU_BUF__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
53644 #define MAC_PCU_BUF__DATA__MODIFY(dst, src) \ argument
53648 #define MAC_PCU_BUF__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
53667 #define TXBF_DBG__MODE__READ(src) (u_int32_t)(src) & 0x00000003U argument
53668 #define TXBF_DBG__MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
53669 #define TXBF_DBG__MODE__MODIFY(dst, src) \ argument
53673 #define TXBF_DBG__MODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
53679 #define TXBF_DBG__CLIENT_TABLE__READ(src) \ argument
53682 #define TXBF_DBG__CLIENT_TABLE__WRITE(src) \ argument
53685 #define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \ argument
53689 #define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \ argument
53697 #define TXBF_DBG__SW_WR_V_DONE__READ(src) \ argument
53700 #define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \ argument
53703 #define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \ argument
53707 #define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \ argument
53721 #define TXBF_DBG__DBG_IM__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) argument
53722 #define TXBF_DBG__DBG_IM__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) argument
53723 #define TXBF_DBG__DBG_IM__MODIFY(dst, src) \ argument
53727 #define TXBF_DBG__DBG_IM__VERIFY(src) \ argument
53741 #define TXBF_DBG__DBG_BW__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) argument
53742 #define TXBF_DBG__DBG_BW__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) argument
53743 #define TXBF_DBG__DBG_BW__MODIFY(dst, src) \ argument
53747 #define TXBF_DBG__DBG_BW__VERIFY(src) \ argument
53761 #define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) argument
53762 #define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \ argument
53766 #define TXBF_DBG__CLK_CNTL__VERIFY(src) \ argument
53780 #define TXBF_DBG__REGULAR_SOUNDING__READ(src) \ argument
53783 #define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \ argument
53786 #define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \ argument
53790 #define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \ argument
53804 #define TXBF_DBG__DBG_NO_WALSH__READ(src) \ argument
53807 #define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \ argument
53810 #define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \ argument
53814 #define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \ argument
53828 #define TXBF_DBG__DBG_NO_CSD__READ(src) \ argument
53831 #define TXBF_DBG__DBG_NO_CSD__WRITE(src) \ argument
53834 #define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \ argument
53838 #define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \ argument
53865 #define TXBF__CB_TX__READ(src) (u_int32_t)(src) & 0x00000003U argument
53866 #define TXBF__CB_TX__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
53867 #define TXBF__CB_TX__MODIFY(dst, src) \ argument
53871 #define TXBF__CB_TX__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
53877 #define TXBF__NB_TX__READ(src) (((u_int32_t)(src) & 0x0000000cU) >> 2) argument
53878 #define TXBF__NB_TX__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000000cU) argument
53879 #define TXBF__NB_TX__MODIFY(dst, src) \ argument
53883 #define TXBF__NB_TX__VERIFY(src) (!((((u_int32_t)(src) << 2) & ~0x0000000cU))) argument
53889 #define TXBF__NG_RPT_TX__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) argument
53890 #define TXBF__NG_RPT_TX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) argument
53891 #define TXBF__NG_RPT_TX__MODIFY(dst, src) \ argument
53895 #define TXBF__NG_RPT_TX__VERIFY(src) \ argument
53903 #define TXBF__NG_CVCACHE__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) argument
53904 #define TXBF__NG_CVCACHE__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) argument
53905 #define TXBF__NG_CVCACHE__MODIFY(dst, src) \ argument
53909 #define TXBF__NG_CVCACHE__VERIFY(src) \ argument
53917 #define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \ argument
53920 #define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \ argument
53923 #define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \ argument
53927 #define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \ argument
53935 #define TXBF__RLR_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
53936 #define TXBF__RLR_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
53937 #define TXBF__RLR_EN__MODIFY(dst, src) \ argument
53941 #define TXBF__RLR_EN__VERIFY(src) \ argument
53955 #define TXBF__RC_20_U_DONE__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) argument
53956 #define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) argument
53957 #define TXBF__RC_20_U_DONE__MODIFY(dst, src) \ argument
53961 #define TXBF__RC_20_U_DONE__VERIFY(src) \ argument
53975 #define TXBF__RC_20_L_DONE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) argument
53976 #define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) argument
53977 #define TXBF__RC_20_L_DONE__MODIFY(dst, src) \ argument
53981 #define TXBF__RC_20_L_DONE__VERIFY(src) \ argument
53995 #define TXBF__RC_40_DONE__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) argument
53996 #define TXBF__RC_40_DONE__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) argument
53997 #define TXBF__RC_40_DONE__MODIFY(dst, src) \ argument
54001 #define TXBF__RC_40_DONE__VERIFY(src) \ argument
54028 #define TXBF_TIMER__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000000ffU argument
54029 #define TXBF_TIMER__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
54030 #define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \ argument
54034 #define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
54040 #define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
54041 #define TXBF_TIMER__ATIMEOUT__WRITE(src) \ argument
54044 #define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \ argument
54048 #define TXBF_TIMER__ATIMEOUT__VERIFY(src) \ argument
54069 #define TXBF_SW__LRU_ACK__READ(src) (u_int32_t)(src) & 0x00000001U argument
54070 #define TXBF_SW__LRU_ACK__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
54071 #define TXBF_SW__LRU_ACK__MODIFY(dst, src) \ argument
54075 #define TXBF_SW__LRU_ACK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
54087 #define TXBF_SW__LRU_ADDR__READ(src) (((u_int32_t)(src) & 0x000003feU) >> 1) argument
54093 #define TXBF_SW__LRU_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
54094 #define TXBF_SW__LRU_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
54095 #define TXBF_SW__LRU_EN__MODIFY(dst, src) \ argument
54099 #define TXBF_SW__LRU_EN__VERIFY(src) \ argument
54113 #define TXBF_SW__DEST_IDX__READ(src) (((u_int32_t)(src) & 0x0007f000U) >> 12) argument
54114 #define TXBF_SW__DEST_IDX__WRITE(src) (((u_int32_t)(src) << 12) & 0x0007f000U) argument
54115 #define TXBF_SW__DEST_IDX__MODIFY(dst, src) \ argument
54119 #define TXBF_SW__DEST_IDX__VERIFY(src) \ argument
54127 #define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) argument
54128 #define TXBF_SW__LRU_WR_ACK__WRITE(src) \ argument
54131 #define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \ argument
54135 #define TXBF_SW__LRU_WR_ACK__VERIFY(src) \ argument
54149 #define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) argument
54150 #define TXBF_SW__LRU_RD_ACK__WRITE(src) \ argument
54153 #define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \ argument
54157 #define TXBF_SW__LRU_RD_ACK__VERIFY(src) \ argument
54171 #define TXBF_SW__WALSH_CSD_MODE__READ(src) \ argument
54174 #define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \ argument
54177 #define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \ argument
54181 #define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \ argument
54195 #define TXBF_SW__CONDITION_NUMBER__READ(src) \ argument
54198 #define TXBF_SW__CONDITION_NUMBER__WRITE(src) \ argument
54201 #define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \ argument
54205 #define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \ argument
54226 #define TXBF_SM__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54244 #define TXBF1_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54262 #define TXBF2_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54280 #define TXBF3_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54298 #define TXBF4_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54316 #define TXBF5_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54334 #define TXBF6_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54352 #define TXBF7_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54370 #define TXBF8_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54388 #define RC0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54389 #define RC0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54390 #define RC0__DATA__MODIFY(dst, src) \ argument
54394 #define RC0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54413 #define RC1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54414 #define RC1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54415 #define RC1__DATA__MODIFY(dst, src) \ argument
54419 #define RC1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54438 #define SVD_MEM0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54439 #define SVD_MEM0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54440 #define SVD_MEM0__DATA__MODIFY(dst, src) \ argument
54444 #define SVD_MEM0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54463 #define SVD_MEM1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54464 #define SVD_MEM1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54465 #define SVD_MEM1__DATA__MODIFY(dst, src) \ argument
54469 #define SVD_MEM1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54488 #define SVD_MEM2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54489 #define SVD_MEM2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54490 #define SVD_MEM2__DATA__MODIFY(dst, src) \ argument
54494 #define SVD_MEM2__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54513 #define SVD_MEM3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54514 #define SVD_MEM3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54515 #define SVD_MEM3__DATA__MODIFY(dst, src) \ argument
54519 #define SVD_MEM3__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54538 #define SVD_MEM4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54539 #define SVD_MEM4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54540 #define SVD_MEM4__DATA__MODIFY(dst, src) \ argument
54544 #define SVD_MEM4__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54563 #define CVCACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU argument
54564 #define CVCACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU) argument
54565 #define CVCACHE__DATA__MODIFY(dst, src) \ argument
54569 #define CVCACHE__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU))) argument
54588 #define RXRF_BIAS1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U argument
54589 #define RXRF_BIAS1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
54590 #define RXRF_BIAS1__SPARE__MODIFY(dst, src) \ argument
54594 #define RXRF_BIAS1__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
54606 #define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \ argument
54609 #define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \ argument
54612 #define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \ argument
54616 #define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \ argument
54624 #define RXRF_BIAS1__PWD_IR25LO18__READ(src) \ argument
54627 #define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \ argument
54630 #define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \ argument
54634 #define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \ argument
54642 #define RXRF_BIAS1__PWD_IC25LO36__READ(src) \ argument
54645 #define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \ argument
54648 #define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \ argument
54652 #define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \ argument
54660 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \ argument
54663 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \ argument
54666 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \ argument
54670 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \ argument
54678 #define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \ argument
54681 #define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \ argument
54684 #define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \ argument
54688 #define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \ argument
54696 #define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \ argument
54699 #define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \ argument
54702 #define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \ argument
54706 #define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \ argument
54714 #define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \ argument
54717 #define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \ argument
54720 #define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \ argument
54724 #define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \ argument
54732 #define RXRF_BIAS1__PWD_IR25LO24__READ(src) \ argument
54735 #define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \ argument
54738 #define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \ argument
54742 #define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \ argument
54750 #define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \ argument
54753 #define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \ argument
54756 #define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \ argument
54760 #define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \ argument
54768 #define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \ argument
54771 #define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \ argument
54774 #define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \ argument
54778 #define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \ argument
54786 #define RXRF_BIAS1__PWD_BIAS__READ(src) \ argument
54789 #define RXRF_BIAS1__PWD_BIAS__WRITE(src) \ argument
54792 #define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \ argument
54796 #define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \ argument
54823 #define RXRF_BIAS2__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U argument
54824 #define RXRF_BIAS2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
54825 #define RXRF_BIAS2__SPARE__MODIFY(dst, src) \ argument
54829 #define RXRF_BIAS2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
54841 #define RXRF_BIAS2__PKEN__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) argument
54842 #define RXRF_BIAS2__PKEN__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) argument
54843 #define RXRF_BIAS2__PKEN__MODIFY(dst, src) \ argument
54847 #define RXRF_BIAS2__PKEN__VERIFY(src) \ argument
54855 #define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4) argument
54856 #define RXRF_BIAS2__VCMVALUE__WRITE(src) \ argument
54859 #define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \ argument
54863 #define RXRF_BIAS2__VCMVALUE__VERIFY(src) \ argument
54871 #define RXRF_BIAS2__PWD_VCMBUF__READ(src) \ argument
54874 #define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \ argument
54877 #define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \ argument
54881 #define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \ argument
54895 #define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \ argument
54898 #define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \ argument
54901 #define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \ argument
54905 #define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \ argument
54913 #define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \ argument
54916 #define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \ argument
54919 #define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \ argument
54923 #define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \ argument
54931 #define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \ argument
54934 #define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \ argument
54937 #define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \ argument
54941 #define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \ argument
54949 #define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \ argument
54952 #define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \ argument
54955 #define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \ argument
54959 #define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \ argument
54967 #define RXRF_BIAS2__PWD_IR25AGC__READ(src) \ argument
54970 #define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \ argument
54973 #define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \ argument
54977 #define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \ argument
54985 #define RXRF_BIAS2__PWD_IC25AGC__READ(src) \ argument
54988 #define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \ argument
54991 #define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \ argument
54995 #define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \ argument
55003 #define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \ argument
55006 #define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \ argument
55009 #define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \ argument
55013 #define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \ argument
55021 #define RXRF_BIAS2__PWD_IR25VCM__READ(src) \ argument
55024 #define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \ argument
55027 #define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \ argument
55031 #define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \ argument
55052 #define RXRF_GAINSTAGES__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U argument
55053 #define RXRF_GAINSTAGES__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
55054 #define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \ argument
55058 #define RXRF_GAINSTAGES__SPARE__VERIFY(src) \ argument
55072 #define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \ argument
55075 #define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \ argument
55078 #define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \ argument
55082 #define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \ argument
55096 #define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \ argument
55099 #define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \ argument
55102 #define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \ argument
55106 #define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \ argument
55114 #define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \ argument
55117 #define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \ argument
55120 #define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \ argument
55124 #define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \ argument
55132 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \ argument
55135 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \ argument
55138 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \ argument
55142 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \ argument
55156 #define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \ argument
55159 #define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \ argument
55162 #define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \ argument
55166 #define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \ argument
55180 #define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \ argument
55183 #define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \ argument
55186 #define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \ argument
55190 #define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \ argument
55204 #define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \ argument
55207 #define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \ argument
55210 #define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \ argument
55214 #define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \ argument
55228 #define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \ argument
55231 #define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \ argument
55234 #define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \ argument
55238 #define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \ argument
55252 #define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \ argument
55255 #define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \ argument
55258 #define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \ argument
55262 #define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \ argument
55270 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \ argument
55273 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \ argument
55276 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \ argument
55280 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \ argument
55294 #define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \ argument
55297 #define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \ argument
55300 #define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \ argument
55304 #define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \ argument
55318 #define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \ argument
55321 #define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \ argument
55324 #define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \ argument
55328 #define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \ argument
55342 #define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \ argument
55345 #define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \ argument
55348 #define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \ argument
55352 #define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \ argument
55366 #define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \ argument
55369 #define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \ argument
55372 #define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \ argument
55376 #define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \ argument
55390 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \ argument
55393 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \ argument
55396 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \ argument
55400 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \ argument
55408 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \ argument
55411 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \ argument
55414 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \ argument
55418 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \ argument
55426 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \ argument
55429 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \ argument
55432 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \ argument
55436 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \ argument
55444 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \ argument
55447 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \ argument
55450 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \ argument
55454 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \ argument
55462 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \ argument
55465 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \ argument
55468 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \ argument
55472 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \ argument
55480 #define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \ argument
55483 #define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \ argument
55486 #define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \ argument
55490 #define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \ argument
55517 #define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \ argument
55520 #define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \ argument
55523 #define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \ argument
55527 #define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \ argument
55541 #define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \ argument
55544 #define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \ argument
55547 #define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \ argument
55551 #define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \ argument
55565 #define RXRF_AGC__AGC_OUT__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
55577 #define RXRF_AGC__LNABUFGAIN2X__READ(src) \ argument
55580 #define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \ argument
55583 #define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \ argument
55587 #define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \ argument
55601 #define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \ argument
55604 #define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \ argument
55607 #define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \ argument
55611 #define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \ argument
55625 #define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
55626 #define RXRF_AGC__PWD_LNABUF__WRITE(src) \ argument
55629 #define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \ argument
55633 #define RXRF_AGC__PWD_LNABUF__VERIFY(src) \ argument
55647 #define RXRF_AGC__AGC_FALL_CTRL__READ(src) \ argument
55650 #define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \ argument
55653 #define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \ argument
55657 #define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \ argument
55665 #define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \ argument
55668 #define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \ argument
55671 #define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \ argument
55675 #define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \ argument
55683 #define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \ argument
55686 #define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \ argument
55689 #define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \ argument
55693 #define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \ argument
55701 #define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \ argument
55704 #define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \ argument
55707 #define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \ argument
55711 #define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \ argument
55719 #define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \ argument
55722 #define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \ argument
55725 #define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \ argument
55729 #define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \ argument
55737 #define RXRF_AGC__AGC_CAL_OVR__READ(src) \ argument
55740 #define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \ argument
55743 #define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \ argument
55747 #define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \ argument
55761 #define RXRF_AGC__AGC_ON_OVR__READ(src) \ argument
55764 #define RXRF_AGC__AGC_ON_OVR__WRITE(src) \ argument
55767 #define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \ argument
55771 #define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \ argument
55785 #define RXRF_AGC__AGC_OVERRIDE__READ(src) \ argument
55788 #define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \ argument
55791 #define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \ argument
55795 #define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \ argument
55822 #define TXRF1__PDLOBUF5G__READ(src) (u_int32_t)(src) & 0x00000001U argument
55823 #define TXRF1__PDLOBUF5G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
55824 #define TXRF1__PDLOBUF5G__MODIFY(dst, src) \ argument
55828 #define TXRF1__PDLOBUF5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
55840 #define TXRF1__PDLODIV5G__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
55841 #define TXRF1__PDLODIV5G__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
55842 #define TXRF1__PDLODIV5G__MODIFY(dst, src) \ argument
55846 #define TXRF1__PDLODIV5G__VERIFY(src) \ argument
55860 #define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
55861 #define TXRF1__LOBUF5GFORCED__WRITE(src) \ argument
55864 #define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \ argument
55868 #define TXRF1__LOBUF5GFORCED__VERIFY(src) \ argument
55882 #define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
55883 #define TXRF1__LODIV5GFORCED__WRITE(src) \ argument
55886 #define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \ argument
55890 #define TXRF1__LODIV5GFORCED__VERIFY(src) \ argument
55904 #define TXRF1__PADRV2GN5G__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) argument
55905 #define TXRF1__PADRV2GN5G__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) argument
55906 #define TXRF1__PADRV2GN5G__MODIFY(dst, src) \ argument
55910 #define TXRF1__PADRV2GN5G__VERIFY(src) \ argument
55918 #define TXRF1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) argument
55919 #define TXRF1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) argument
55920 #define TXRF1__PADRV3GN5G__MODIFY(dst, src) \ argument
55924 #define TXRF1__PADRV3GN5G__VERIFY(src) \ argument
55932 #define TXRF1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x0000f000U) >> 12) argument
55933 #define TXRF1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 12) & 0x0000f000U) argument
55934 #define TXRF1__PADRV4GN5G__MODIFY(dst, src) \ argument
55938 #define TXRF1__PADRV4GN5G__VERIFY(src) \ argument
55946 #define TXRF1__LOCALTXGAIN5G__READ(src) \ argument
55949 #define TXRF1__LOCALTXGAIN5G__WRITE(src) \ argument
55952 #define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \ argument
55956 #define TXRF1__LOCALTXGAIN5G__VERIFY(src) \ argument
55970 #define TXRF1__PDOUT2G__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) argument
55971 #define TXRF1__PDOUT2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) argument
55972 #define TXRF1__PDOUT2G__MODIFY(dst, src) \ argument
55976 #define TXRF1__PDOUT2G__VERIFY(src) \ argument
55990 #define TXRF1__PDDR2G__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
55991 #define TXRF1__PDDR2G__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
55992 #define TXRF1__PDDR2G__MODIFY(dst, src) \ argument
55996 #define TXRF1__PDDR2G__VERIFY(src) \ argument
56010 #define TXRF1__PDMXR2G__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) argument
56011 #define TXRF1__PDMXR2G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) argument
56012 #define TXRF1__PDMXR2G__MODIFY(dst, src) \ argument
56016 #define TXRF1__PDMXR2G__VERIFY(src) \ argument
56030 #define TXRF1__PDLOBUF2G__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) argument
56031 #define TXRF1__PDLOBUF2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) argument
56032 #define TXRF1__PDLOBUF2G__MODIFY(dst, src) \ argument
56036 #define TXRF1__PDLOBUF2G__VERIFY(src) \ argument
56050 #define TXRF1__PDLODIV2G__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) argument
56051 #define TXRF1__PDLODIV2G__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) argument
56052 #define TXRF1__PDLODIV2G__MODIFY(dst, src) \ argument
56056 #define TXRF1__PDLODIV2G__VERIFY(src) \ argument
56070 #define TXRF1__LOBUF2GFORCED__READ(src) \ argument
56073 #define TXRF1__LOBUF2GFORCED__WRITE(src) \ argument
56076 #define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \ argument
56080 #define TXRF1__LOBUF2GFORCED__VERIFY(src) \ argument
56094 #define TXRF1__LODIV2GFORCED__READ(src) \ argument
56097 #define TXRF1__LODIV2GFORCED__WRITE(src) \ argument
56100 #define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \ argument
56104 #define TXRF1__LODIV2GFORCED__VERIFY(src) \ argument
56118 #define TXRF1__PADRVGN2G__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) argument
56119 #define TXRF1__PADRVGN2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U) argument
56120 #define TXRF1__PADRVGN2G__MODIFY(dst, src) \ argument
56124 #define TXRF1__PADRVGN2G__VERIFY(src) \ argument
56132 #define TXRF1__LOCALTXGAIN2G__READ(src) \ argument
56135 #define TXRF1__LOCALTXGAIN2G__WRITE(src) \ argument
56138 #define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \ argument
56142 #define TXRF1__LOCALTXGAIN2G__VERIFY(src) \ argument
56169 #define TXRF2__D3B5G__READ(src) (u_int32_t)(src) & 0x00000007U argument
56170 #define TXRF2__D3B5G__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
56171 #define TXRF2__D3B5G__MODIFY(dst, src) \ argument
56175 #define TXRF2__D3B5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) argument
56181 #define TXRF2__D4B5G__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) argument
56182 #define TXRF2__D4B5G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) argument
56183 #define TXRF2__D4B5G__MODIFY(dst, src) \ argument
56187 #define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U))) argument
56193 #define TXRF2__OCAS2G__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) argument
56194 #define TXRF2__OCAS2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) argument
56195 #define TXRF2__OCAS2G__MODIFY(dst, src) \ argument
56199 #define TXRF2__OCAS2G__VERIFY(src) \ argument
56207 #define TXRF2__DCAS2G__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) argument
56208 #define TXRF2__DCAS2G__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) argument
56209 #define TXRF2__DCAS2G__MODIFY(dst, src) \ argument
56213 #define TXRF2__DCAS2G__VERIFY(src) \ argument
56221 #define TXRF2__OB2G_PALOFF__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) argument
56222 #define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) argument
56223 #define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \ argument
56227 #define TXRF2__OB2G_PALOFF__VERIFY(src) \ argument
56235 #define TXRF2__OB2G_QAM__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) argument
56236 #define TXRF2__OB2G_QAM__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) argument
56237 #define TXRF2__OB2G_QAM__MODIFY(dst, src) \ argument
56241 #define TXRF2__OB2G_QAM__VERIFY(src) \ argument
56249 #define TXRF2__OB2G_PSK__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) argument
56250 #define TXRF2__OB2G_PSK__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) argument
56251 #define TXRF2__OB2G_PSK__MODIFY(dst, src) \ argument
56255 #define TXRF2__OB2G_PSK__VERIFY(src) \ argument
56263 #define TXRF2__OB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) argument
56264 #define TXRF2__OB2G_CCK__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) argument
56265 #define TXRF2__OB2G_CCK__MODIFY(dst, src) \ argument
56269 #define TXRF2__OB2G_CCK__VERIFY(src) \ argument
56277 #define TXRF2__DB2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) argument
56278 #define TXRF2__DB2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x07000000U) argument
56279 #define TXRF2__DB2G__MODIFY(dst, src) \ argument
56283 #define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U))) argument
56289 #define TXRF2__PDOUT5G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
56290 #define TXRF2__PDOUT5G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
56291 #define TXRF2__PDOUT5G__MODIFY(dst, src) \ argument
56295 #define TXRF2__PDOUT5G__VERIFY(src) \ argument
56303 #define TXRF2__PDMXR5G__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
56304 #define TXRF2__PDMXR5G__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
56305 #define TXRF2__PDMXR5G__MODIFY(dst, src) \ argument
56309 #define TXRF2__PDMXR5G__VERIFY(src) \ argument
56336 #define TXRF3__FILTR2G__READ(src) (u_int32_t)(src) & 0x00000003U argument
56337 #define TXRF3__FILTR2G__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
56338 #define TXRF3__FILTR2G__MODIFY(dst, src) \ argument
56342 #define TXRF3__FILTR2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
56348 #define TXRF3__PWDFB2_2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
56349 #define TXRF3__PWDFB2_2G__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
56350 #define TXRF3__PWDFB2_2G__MODIFY(dst, src) \ argument
56354 #define TXRF3__PWDFB2_2G__VERIFY(src) \ argument
56368 #define TXRF3__PWDFB1_2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
56369 #define TXRF3__PWDFB1_2G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
56370 #define TXRF3__PWDFB1_2G__MODIFY(dst, src) \ argument
56374 #define TXRF3__PWDFB1_2G__VERIFY(src) \ argument
56388 #define TXRF3__PDFB2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
56389 #define TXRF3__PDFB2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
56390 #define TXRF3__PDFB2G__MODIFY(dst, src) \ argument
56394 #define TXRF3__PDFB2G__VERIFY(src) \ argument
56408 #define TXRF3__RDIV5G__READ(src) (((u_int32_t)(src) & 0x00000060U) >> 5) argument
56409 #define TXRF3__RDIV5G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000060U) argument
56410 #define TXRF3__RDIV5G__MODIFY(dst, src) \ argument
56414 #define TXRF3__RDIV5G__VERIFY(src) \ argument
56422 #define TXRF3__CAPDIV5G__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7) argument
56423 #define TXRF3__CAPDIV5G__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U) argument
56424 #define TXRF3__CAPDIV5G__MODIFY(dst, src) \ argument
56428 #define TXRF3__CAPDIV5G__VERIFY(src) \ argument
56436 #define TXRF3__PDPREDIST5G__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
56437 #define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) argument
56438 #define TXRF3__PDPREDIST5G__MODIFY(dst, src) \ argument
56442 #define TXRF3__PDPREDIST5G__VERIFY(src) \ argument
56456 #define TXRF3__RDIV2G__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) argument
56457 #define TXRF3__RDIV2G__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) argument
56458 #define TXRF3__RDIV2G__MODIFY(dst, src) \ argument
56462 #define TXRF3__RDIV2G__VERIFY(src) \ argument
56470 #define TXRF3__PDPREDIST2G__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) argument
56471 #define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) argument
56472 #define TXRF3__PDPREDIST2G__MODIFY(dst, src) \ argument
56476 #define TXRF3__PDPREDIST2G__VERIFY(src) \ argument
56490 #define TXRF3__OCAS5G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) argument
56491 #define TXRF3__OCAS5G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) argument
56492 #define TXRF3__OCAS5G__MODIFY(dst, src) \ argument
56496 #define TXRF3__OCAS5G__VERIFY(src) \ argument
56504 #define TXRF3__D2CAS5G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) argument
56505 #define TXRF3__D2CAS5G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) argument
56506 #define TXRF3__D2CAS5G__MODIFY(dst, src) \ argument
56510 #define TXRF3__D2CAS5G__VERIFY(src) \ argument
56518 #define TXRF3__D3CAS5G__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) argument
56519 #define TXRF3__D3CAS5G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) argument
56520 #define TXRF3__D3CAS5G__MODIFY(dst, src) \ argument
56524 #define TXRF3__D3CAS5G__VERIFY(src) \ argument
56532 #define TXRF3__D4CAS5G__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) argument
56533 #define TXRF3__D4CAS5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) argument
56534 #define TXRF3__D4CAS5G__MODIFY(dst, src) \ argument
56538 #define TXRF3__D4CAS5G__VERIFY(src) \ argument
56546 #define TXRF3__OB5G__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) argument
56547 #define TXRF3__OB5G__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) argument
56548 #define TXRF3__OB5G__MODIFY(dst, src) \ argument
56552 #define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U))) argument
56558 #define TXRF3__D2B5G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
56559 #define TXRF3__D2B5G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
56560 #define TXRF3__D2B5G__MODIFY(dst, src) \ argument
56564 #define TXRF3__D2B5G__VERIFY(src) \ argument
56585 #define TXRF4__PK1B2G_CCK__READ(src) (u_int32_t)(src) & 0x00000003U argument
56586 #define TXRF4__PK1B2G_CCK__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
56587 #define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \ argument
56591 #define TXRF4__PK1B2G_CCK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
56597 #define TXRF4__MIOB2G_QAM__READ(src) (((u_int32_t)(src) & 0x0000001cU) >> 2) argument
56598 #define TXRF4__MIOB2G_QAM__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000001cU) argument
56599 #define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \ argument
56603 #define TXRF4__MIOB2G_QAM__VERIFY(src) \ argument
56611 #define TXRF4__MIOB2G_PSK__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) argument
56612 #define TXRF4__MIOB2G_PSK__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) argument
56613 #define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \ argument
56617 #define TXRF4__MIOB2G_PSK__VERIFY(src) \ argument
56625 #define TXRF4__MIOB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) argument
56626 #define TXRF4__MIOB2G_CCK__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) argument
56627 #define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \ argument
56631 #define TXRF4__MIOB2G_CCK__VERIFY(src) \ argument
56639 #define TXRF4__COMP2G_QAM__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) argument
56640 #define TXRF4__COMP2G_QAM__WRITE(src) (((u_int32_t)(src) << 11) & 0x00003800U) argument
56641 #define TXRF4__COMP2G_QAM__MODIFY(dst, src) \ argument
56645 #define TXRF4__COMP2G_QAM__VERIFY(src) \ argument
56653 #define TXRF4__COMP2G_PSK__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) argument
56654 #define TXRF4__COMP2G_PSK__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) argument
56655 #define TXRF4__COMP2G_PSK__MODIFY(dst, src) \ argument
56659 #define TXRF4__COMP2G_PSK__VERIFY(src) \ argument
56667 #define TXRF4__COMP2G_CCK__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) argument
56668 #define TXRF4__COMP2G_CCK__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) argument
56669 #define TXRF4__COMP2G_CCK__MODIFY(dst, src) \ argument
56673 #define TXRF4__COMP2G_CCK__VERIFY(src) \ argument
56681 #define TXRF4__AMP2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) argument
56682 #define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) argument
56683 #define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \ argument
56687 #define TXRF4__AMP2B2G_QAM__VERIFY(src) \ argument
56695 #define TXRF4__AMP2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) argument
56696 #define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) argument
56697 #define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \ argument
56701 #define TXRF4__AMP2B2G_PSK__VERIFY(src) \ argument
56709 #define TXRF4__AMP2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) argument
56710 #define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) argument
56711 #define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \ argument
56715 #define TXRF4__AMP2B2G_CCK__VERIFY(src) \ argument
56723 #define TXRF4__AMP2CAS2G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
56724 #define TXRF4__AMP2CAS2G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
56725 #define TXRF4__AMP2CAS2G__MODIFY(dst, src) \ argument
56729 #define TXRF4__AMP2CAS2G__VERIFY(src) \ argument
56750 #define TXRF5__TXMODPALONLY__READ(src) (u_int32_t)(src) & 0x00000001U argument
56751 #define TXRF5__TXMODPALONLY__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
56752 #define TXRF5__TXMODPALONLY__MODIFY(dst, src) \ argument
56756 #define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
56768 #define TXRF5__PAL_LOCKED__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
56780 #define TXRF5__FBHI2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
56792 #define TXRF5__FBLO2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
56804 #define TXRF5__NOPALGAIN2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
56805 #define TXRF5__NOPALGAIN2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
56806 #define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \ argument
56810 #define TXRF5__NOPALGAIN2G__VERIFY(src) \ argument
56824 #define TXRF5__ENPACAL2G__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
56825 #define TXRF5__ENPACAL2G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
56826 #define TXRF5__ENPACAL2G__MODIFY(dst, src) \ argument
56830 #define TXRF5__ENPACAL2G__VERIFY(src) \ argument
56844 #define TXRF5__OFFSET2G__READ(src) (((u_int32_t)(src) & 0x00001fc0U) >> 6) argument
56845 #define TXRF5__OFFSET2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x00001fc0U) argument
56846 #define TXRF5__OFFSET2G__MODIFY(dst, src) \ argument
56850 #define TXRF5__OFFSET2G__VERIFY(src) \ argument
56858 #define TXRF5__ENOFFSETCAL2G__READ(src) \ argument
56861 #define TXRF5__ENOFFSETCAL2G__WRITE(src) \ argument
56864 #define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \ argument
56868 #define TXRF5__ENOFFSETCAL2G__VERIFY(src) \ argument
56882 #define TXRF5__REFHI2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) argument
56883 #define TXRF5__REFHI2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U) argument
56884 #define TXRF5__REFHI2G__MODIFY(dst, src) \ argument
56888 #define TXRF5__REFHI2G__VERIFY(src) \ argument
56896 #define TXRF5__REFLO2G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) argument
56897 #define TXRF5__REFLO2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) argument
56898 #define TXRF5__REFLO2G__MODIFY(dst, src) \ argument
56902 #define TXRF5__REFLO2G__VERIFY(src) \ argument
56910 #define TXRF5__PALCLAMP2G__READ(src) (((u_int32_t)(src) & 0x00300000U) >> 20) argument
56911 #define TXRF5__PALCLAMP2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00300000U) argument
56912 #define TXRF5__PALCLAMP2G__MODIFY(dst, src) \ argument
56916 #define TXRF5__PALCLAMP2G__VERIFY(src) \ argument
56924 #define TXRF5__PK2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) argument
56925 #define TXRF5__PK2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 22) & 0x00c00000U) argument
56926 #define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \ argument
56930 #define TXRF5__PK2B2G_QAM__VERIFY(src) \ argument
56938 #define TXRF5__PK2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) argument
56939 #define TXRF5__PK2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) argument
56940 #define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \ argument
56944 #define TXRF5__PK2B2G_PSK__VERIFY(src) \ argument
56952 #define TXRF5__PK2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) argument
56953 #define TXRF5__PK2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) argument
56954 #define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \ argument
56958 #define TXRF5__PK2B2G_CCK__VERIFY(src) \ argument
56966 #define TXRF5__PK1B2G_QAM__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) argument
56967 #define TXRF5__PK1B2G_QAM__WRITE(src) (((u_int32_t)(src) << 28) & 0x30000000U) argument
56968 #define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \ argument
56972 #define TXRF5__PK1B2G_QAM__VERIFY(src) \ argument
56980 #define TXRF5__PK1B2G_PSK__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) argument
56981 #define TXRF5__PK1B2G_PSK__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) argument
56982 #define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \ argument
56986 #define TXRF5__PK1B2G_PSK__VERIFY(src) \ argument
57007 #define TXRF6__PALCLKGATE2G__READ(src) (u_int32_t)(src) & 0x00000001U argument
57008 #define TXRF6__PALCLKGATE2G__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
57009 #define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \ argument
57013 #define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
57025 #define TXRF6__PALFLUCTCOUNT2G__READ(src) \ argument
57028 #define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \ argument
57031 #define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \ argument
57035 #define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \ argument
57043 #define TXRF6__PALFLUCTGAIN2G__READ(src) \ argument
57046 #define TXRF6__PALFLUCTGAIN2G__WRITE(src) \ argument
57049 #define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \ argument
57053 #define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \ argument
57061 #define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
57062 #define TXRF6__PALNOFLUCT2G__WRITE(src) \ argument
57065 #define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \ argument
57069 #define TXRF6__PALNOFLUCT2G__VERIFY(src) \ argument
57083 #define TXRF6__GAINSTEP2G__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) argument
57084 #define TXRF6__GAINSTEP2G__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) argument
57085 #define TXRF6__GAINSTEP2G__MODIFY(dst, src) \ argument
57089 #define TXRF6__GAINSTEP2G__VERIFY(src) \ argument
57097 #define TXRF6__USE_GAIN_DELTA2G__READ(src) \ argument
57100 #define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \ argument
57103 #define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \ argument
57107 #define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \ argument
57121 #define TXRF6__CAPDIV_I2G__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) argument
57122 #define TXRF6__CAPDIV_I2G__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) argument
57123 #define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \ argument
57127 #define TXRF6__CAPDIV_I2G__VERIFY(src) \ argument
57135 #define TXRF6__PADRVGN_INDEX_I2G__READ(src) \ argument
57138 #define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \ argument
57141 #define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \ argument
57145 #define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \ argument
57153 #define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24) argument
57154 #define TXRF6__VCMONDELAY2G__WRITE(src) \ argument
57157 #define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \ argument
57161 #define TXRF6__VCMONDELAY2G__VERIFY(src) \ argument
57169 #define TXRF6__CAPDIV2G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
57170 #define TXRF6__CAPDIV2G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
57171 #define TXRF6__CAPDIV2G__MODIFY(dst, src) \ argument
57175 #define TXRF6__CAPDIV2G__VERIFY(src) \ argument
57183 #define TXRF6__CAPDIV2GOVR__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
57184 #define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
57185 #define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \ argument
57189 #define TXRF6__CAPDIV2GOVR__VERIFY(src) \ argument
57216 #define SYNTH1__SEL_VCMONABUS__READ(src) (u_int32_t)(src) & 0x00000007U argument
57217 #define SYNTH1__SEL_VCMONABUS__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
57218 #define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \ argument
57222 #define SYNTH1__SEL_VCMONABUS__VERIFY(src) \ argument
57230 #define SYNTH1__SEL_VCOABUS__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) argument
57231 #define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U) argument
57232 #define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \ argument
57236 #define SYNTH1__SEL_VCOABUS__VERIFY(src) \ argument
57244 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \ argument
57247 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \ argument
57250 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \ argument
57254 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \ argument
57268 #define SYNTH1__MONITOR_VC2LOW__READ(src) \ argument
57271 #define SYNTH1__MONITOR_VC2LOW__WRITE(src) \ argument
57274 #define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \ argument
57278 #define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \ argument
57292 #define SYNTH1__MONITOR_VC2HIGH__READ(src) \ argument
57295 #define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \ argument
57298 #define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \ argument
57302 #define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \ argument
57316 #define SYNTH1__MONITOR_FB_DIV2__READ(src) \ argument
57319 #define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \ argument
57322 #define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \ argument
57326 #define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \ argument
57340 #define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
57341 #define SYNTH1__MONITOR_REF__WRITE(src) \ argument
57344 #define SYNTH1__MONITOR_REF__MODIFY(dst, src) \ argument
57348 #define SYNTH1__MONITOR_REF__VERIFY(src) \ argument
57362 #define SYNTH1__MONITOR_FB__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
57363 #define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
57364 #define SYNTH1__MONITOR_FB__MODIFY(dst, src) \ argument
57368 #define SYNTH1__MONITOR_FB__VERIFY(src) \ argument
57382 #define SYNTH1__SEVENBITVCOCAP__READ(src) \ argument
57385 #define SYNTH1__SEVENBITVCOCAP__WRITE(src) \ argument
57388 #define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \ argument
57392 #define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \ argument
57406 #define SYNTH1__PWUP_PD__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) argument
57407 #define SYNTH1__PWUP_PD__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) argument
57408 #define SYNTH1__PWUP_PD__MODIFY(dst, src) \ argument
57412 #define SYNTH1__PWUP_PD__VERIFY(src) \ argument
57420 #define SYNTH1__PWD_VCOBUF__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) argument
57421 #define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U) argument
57422 #define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \ argument
57426 #define SYNTH1__PWD_VCOBUF__VERIFY(src) \ argument
57440 #define SYNTH1__VCOBUFGAIN__READ(src) (((u_int32_t)(src) & 0x00060000U) >> 17) argument
57441 #define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U) argument
57442 #define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \ argument
57446 #define SYNTH1__VCOBUFGAIN__VERIFY(src) \ argument
57454 #define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19) argument
57455 #define SYNTH1__VCOREGLEVEL__WRITE(src) \ argument
57458 #define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \ argument
57462 #define SYNTH1__VCOREGLEVEL__VERIFY(src) \ argument
57470 #define SYNTH1__VCOREGBYPASS__READ(src) \ argument
57473 #define SYNTH1__VCOREGBYPASS__WRITE(src) \ argument
57476 #define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \ argument
57480 #define SYNTH1__VCOREGBYPASS__VERIFY(src) \ argument
57494 #define SYNTH1__PWUP_LOREF__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) argument
57495 #define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) argument
57496 #define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \ argument
57500 #define SYNTH1__PWUP_LOREF__VERIFY(src) \ argument
57514 #define SYNTH1__PWD_LOMIX__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) argument
57515 #define SYNTH1__PWD_LOMIX__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) argument
57516 #define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \ argument
57520 #define SYNTH1__PWD_LOMIX__VERIFY(src) \ argument
57534 #define SYNTH1__PWD_LODIV__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
57535 #define SYNTH1__PWD_LODIV__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) argument
57536 #define SYNTH1__PWD_LODIV__MODIFY(dst, src) \ argument
57540 #define SYNTH1__PWD_LODIV__VERIFY(src) \ argument
57554 #define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) argument
57555 #define SYNTH1__PWD_LOBUF5G__WRITE(src) \ argument
57558 #define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \ argument
57562 #define SYNTH1__PWD_LOBUF5G__VERIFY(src) \ argument
57576 #define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) argument
57577 #define SYNTH1__PWD_LOBUF2G__WRITE(src) \ argument
57580 #define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \ argument
57584 #define SYNTH1__PWD_LOBUF2G__VERIFY(src) \ argument
57598 #define SYNTH1__PWD_PRESC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
57599 #define SYNTH1__PWD_PRESC__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) argument
57600 #define SYNTH1__PWD_PRESC__MODIFY(dst, src) \ argument
57604 #define SYNTH1__PWD_PRESC__VERIFY(src) \ argument
57618 #define SYNTH1__PWD_VCO__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
57619 #define SYNTH1__PWD_VCO__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
57620 #define SYNTH1__PWD_VCO__MODIFY(dst, src) \ argument
57624 #define SYNTH1__PWD_VCO__VERIFY(src) \ argument
57638 #define SYNTH1__PWD_VCMON__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
57639 #define SYNTH1__PWD_VCMON__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
57640 #define SYNTH1__PWD_VCMON__MODIFY(dst, src) \ argument
57644 #define SYNTH1__PWD_VCMON__VERIFY(src) \ argument
57658 #define SYNTH1__PWD_CP__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
57659 #define SYNTH1__PWD_CP__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
57660 #define SYNTH1__PWD_CP__MODIFY(dst, src) \ argument
57664 #define SYNTH1__PWD_CP__VERIFY(src) \ argument
57678 #define SYNTH1__PWD_BIAS__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
57679 #define SYNTH1__PWD_BIAS__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
57680 #define SYNTH1__PWD_BIAS__MODIFY(dst, src) \ argument
57684 #define SYNTH1__PWD_BIAS__VERIFY(src) \ argument
57711 #define SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU argument
57712 #define SYNTH2__CAPRANGE3__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
57713 #define SYNTH2__CAPRANGE3__MODIFY(dst, src) \ argument
57717 #define SYNTH2__CAPRANGE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) argument
57723 #define SYNTH2__CAPRANGE2__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) argument
57724 #define SYNTH2__CAPRANGE2__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) argument
57725 #define SYNTH2__CAPRANGE2__MODIFY(dst, src) \ argument
57729 #define SYNTH2__CAPRANGE2__VERIFY(src) \ argument
57737 #define SYNTH2__CAPRANGE1__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) argument
57738 #define SYNTH2__CAPRANGE1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) argument
57739 #define SYNTH2__CAPRANGE1__MODIFY(dst, src) \ argument
57743 #define SYNTH2__CAPRANGE1__VERIFY(src) \ argument
57751 #define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \ argument
57754 #define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \ argument
57757 #define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \ argument
57761 #define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \ argument
57769 #define SYNTH2__CPLOWLK_INTN__READ(src) \ argument
57772 #define SYNTH2__CPLOWLK_INTN__WRITE(src) \ argument
57775 #define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \ argument
57779 #define SYNTH2__CPLOWLK_INTN__VERIFY(src) \ argument
57793 #define SYNTH2__CPSTEERING_EN_INTN__READ(src) \ argument
57796 #define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \ argument
57799 #define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \ argument
57803 #define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \ argument
57817 #define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18) argument
57818 #define SYNTH2__CPBIAS_INTN__WRITE(src) \ argument
57821 #define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \ argument
57825 #define SYNTH2__CPBIAS_INTN__VERIFY(src) \ argument
57833 #define SYNTH2__VC_LOW_REF__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) argument
57834 #define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) argument
57835 #define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \ argument
57839 #define SYNTH2__VC_LOW_REF__VERIFY(src) \ argument
57847 #define SYNTH2__VC_MID_REF__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) argument
57848 #define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) argument
57849 #define SYNTH2__VC_MID_REF__MODIFY(dst, src) \ argument
57853 #define SYNTH2__VC_MID_REF__VERIFY(src) \ argument
57861 #define SYNTH2__VC_HI_REF__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) argument
57862 #define SYNTH2__VC_HI_REF__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) argument
57863 #define SYNTH2__VC_HI_REF__MODIFY(dst, src) \ argument
57867 #define SYNTH2__VC_HI_REF__VERIFY(src) \ argument
57875 #define SYNTH2__VC_CAL_REF__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
57876 #define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
57877 #define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \ argument
57881 #define SYNTH2__VC_CAL_REF__VERIFY(src) \ argument
57902 #define SYNTH3__WAIT_VC_CHECK__READ(src) (u_int32_t)(src) & 0x0000003fU argument
57903 #define SYNTH3__WAIT_VC_CHECK__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
57904 #define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \ argument
57908 #define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \ argument
57916 #define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6) argument
57917 #define SYNTH3__WAIT_CAL_LIN__WRITE(src) \ argument
57920 #define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \ argument
57924 #define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \ argument
57932 #define SYNTH3__WAIT_CAL_BIN__READ(src) \ argument
57935 #define SYNTH3__WAIT_CAL_BIN__WRITE(src) \ argument
57938 #define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \ argument
57942 #define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \ argument
57950 #define SYNTH3__WAIT_PWRUP__READ(src) (((u_int32_t)(src) & 0x00fc0000U) >> 18) argument
57951 #define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U) argument
57952 #define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \ argument
57956 #define SYNTH3__WAIT_PWRUP__VERIFY(src) \ argument
57964 #define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \ argument
57967 #define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \ argument
57970 #define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \ argument
57974 #define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \ argument
57982 #define SYNTH3__SEL_CLK_DIV2__READ(src) \ argument
57985 #define SYNTH3__SEL_CLK_DIV2__WRITE(src) \ argument
57988 #define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \ argument
57992 #define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \ argument
58006 #define SYNTH3__DIS_CLK_XTAL__READ(src) \ argument
58009 #define SYNTH3__DIS_CLK_XTAL__WRITE(src) \ argument
58012 #define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \ argument
58016 #define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \ argument
58043 #define SYNTH4__PS_SINGLE_PULSE__READ(src) (u_int32_t)(src) & 0x00000001U argument
58044 #define SYNTH4__PS_SINGLE_PULSE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
58045 #define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \ argument
58049 #define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \ argument
58063 #define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
58064 #define SYNTH4__LONGSHIFTSEL__WRITE(src) \ argument
58067 #define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \ argument
58071 #define SYNTH4__LONGSHIFTSEL__VERIFY(src) \ argument
58085 #define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \ argument
58088 #define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \ argument
58091 #define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \ argument
58095 #define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \ argument
58103 #define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \ argument
58106 #define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \ argument
58109 #define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \ argument
58113 #define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \ argument
58127 #define SYNTH4__PSCOUNT_FBSEL__READ(src) \ argument
58130 #define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \ argument
58133 #define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \ argument
58137 #define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \ argument
58151 #define SYNTH4__SDM_DITHER1__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) argument
58152 #define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) argument
58153 #define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \ argument
58157 #define SYNTH4__SDM_DITHER1__VERIFY(src) \ argument
58165 #define SYNTH4__SDM_MODE__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
58166 #define SYNTH4__SDM_MODE__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) argument
58167 #define SYNTH4__SDM_MODE__MODIFY(dst, src) \ argument
58171 #define SYNTH4__SDM_MODE__VERIFY(src) \ argument
58185 #define SYNTH4__SDM_DISABLE__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
58186 #define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) argument
58187 #define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \ argument
58191 #define SYNTH4__SDM_DISABLE__VERIFY(src) \ argument
58205 #define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
58206 #define SYNTH4__RESET_PRESC__WRITE(src) \ argument
58209 #define SYNTH4__RESET_PRESC__MODIFY(dst, src) \ argument
58213 #define SYNTH4__RESET_PRESC__VERIFY(src) \ argument
58227 #define SYNTH4__PRESCSEL__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11) argument
58228 #define SYNTH4__PRESCSEL__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U) argument
58229 #define SYNTH4__PRESCSEL__MODIFY(dst, src) \ argument
58233 #define SYNTH4__PRESCSEL__VERIFY(src) \ argument
58241 #define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) argument
58242 #define SYNTH4__PFD_DISABLE__WRITE(src) \ argument
58245 #define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \ argument
58249 #define SYNTH4__PFD_DISABLE__VERIFY(src) \ argument
58263 #define SYNTH4__PFDDELAY_FRACN__READ(src) \ argument
58266 #define SYNTH4__PFDDELAY_FRACN__WRITE(src) \ argument
58269 #define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \ argument
58273 #define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \ argument
58287 #define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) argument
58288 #define SYNTH4__FORCE_LO_ON__WRITE(src) \ argument
58291 #define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \ argument
58295 #define SYNTH4__FORCE_LO_ON__VERIFY(src) \ argument
58309 #define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \ argument
58312 #define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \ argument
58315 #define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \ argument
58319 #define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \ argument
58333 #define SYNTH4__VCOCAPPULLUP__READ(src) \ argument
58336 #define SYNTH4__VCOCAPPULLUP__WRITE(src) \ argument
58339 #define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \ argument
58343 #define SYNTH4__VCOCAPPULLUP__VERIFY(src) \ argument
58357 #define SYNTH4__VCOCAP_OVR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18) argument
58358 #define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U) argument
58359 #define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \ argument
58363 #define SYNTH4__VCOCAP_OVR__VERIFY(src) \ argument
58371 #define SYNTH4__FORCE_VCOCAP__READ(src) \ argument
58374 #define SYNTH4__FORCE_VCOCAP__WRITE(src) \ argument
58377 #define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \ argument
58381 #define SYNTH4__FORCE_VCOCAP__VERIFY(src) \ argument
58395 #define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
58396 #define SYNTH4__FORCE_PINVC__WRITE(src) \ argument
58399 #define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \ argument
58403 #define SYNTH4__FORCE_PINVC__VERIFY(src) \ argument
58417 #define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \ argument
58420 #define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \ argument
58423 #define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \ argument
58427 #define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \ argument
58441 #define SYNTH4__ALWAYS_SHORTR__READ(src) \ argument
58444 #define SYNTH4__ALWAYS_SHORTR__WRITE(src) \ argument
58447 #define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \ argument
58451 #define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \ argument
58465 #define SYNTH4__DIS_LOSTVC__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
58466 #define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
58467 #define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \ argument
58471 #define SYNTH4__DIS_LOSTVC__VERIFY(src) \ argument
58485 #define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \ argument
58488 #define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \ argument
58491 #define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \ argument
58495 #define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \ argument
58522 #define SYNTH5__VCOBIAS__READ(src) (u_int32_t)(src) & 0x00000003U argument
58523 #define SYNTH5__VCOBIAS__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
58524 #define SYNTH5__VCOBIAS__MODIFY(dst, src) \ argument
58528 #define SYNTH5__VCOBIAS__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
58534 #define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \ argument
58537 #define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \ argument
58540 #define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \ argument
58544 #define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \ argument
58552 #define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \ argument
58555 #define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \ argument
58558 #define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \ argument
58562 #define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \ argument
58570 #define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) argument
58571 #define SYNTH5__PWDB_ICVCO25__WRITE(src) \ argument
58574 #define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \ argument
58578 #define SYNTH5__PWDB_ICVCO25__VERIFY(src) \ argument
58586 #define SYNTH5__PWDB_ICVCOREG25__READ(src) \ argument
58589 #define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \ argument
58592 #define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \ argument
58596 #define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \ argument
58604 #define SYNTH5__PWDB_IRVCOREG50__READ(src) \ argument
58607 #define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \ argument
58610 #define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \ argument
58614 #define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \ argument
58628 #define SYNTH5__PWDB_ICLOMIX__READ(src) \ argument
58631 #define SYNTH5__PWDB_ICLOMIX__WRITE(src) \ argument
58634 #define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \ argument
58638 #define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \ argument
58646 #define SYNTH5__PWDB_ICLODIV50__READ(src) \ argument
58649 #define SYNTH5__PWDB_ICLODIV50__WRITE(src) \ argument
58652 #define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \ argument
58656 #define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \ argument
58664 #define SYNTH5__PWDB_ICPRESC50__READ(src) \ argument
58667 #define SYNTH5__PWDB_ICPRESC50__WRITE(src) \ argument
58670 #define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \ argument
58674 #define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \ argument
58682 #define SYNTH5__PWDB_IRVCMON25__READ(src) \ argument
58685 #define SYNTH5__PWDB_IRVCMON25__WRITE(src) \ argument
58688 #define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \ argument
58692 #define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \ argument
58700 #define SYNTH5__PWDB_IRPFDCP__READ(src) \ argument
58703 #define SYNTH5__PWDB_IRPFDCP__WRITE(src) \ argument
58706 #define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \ argument
58710 #define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \ argument
58718 #define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) argument
58719 #define SYNTH5__SDM_DITHER2__WRITE(src) \ argument
58722 #define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \ argument
58726 #define SYNTH5__SDM_DITHER2__VERIFY(src) \ argument
58747 #define SYNTH6__LOBUF5GTUNE__READ(src) (u_int32_t)(src) & 0x00000003U argument
58753 #define SYNTH6__LOOP_IP__READ(src) (((u_int32_t)(src) & 0x000001fcU) >> 2) argument
58759 #define SYNTH6__VC2LOW__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
58771 #define SYNTH6__VC2HIGH__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
58783 #define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
58795 #define SYNTH6__RESET_PSCOUNTERS__READ(src) \ argument
58809 #define SYNTH6__RESET_PFD__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) argument
58821 #define SYNTH6__RESET_RFD__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) argument
58833 #define SYNTH6__SHORT_R__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15) argument
58845 #define SYNTH6__VCO_CAP_ST__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16) argument
58851 #define SYNTH6__PIN_VC__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
58863 #define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \ argument
58877 #define SYNTH6__CAP_SEARCH__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) argument
58889 #define SYNTH6__SYNTH_SM_STATE__READ(src) \ argument
58897 #define SYNTH6__SYNTH_ON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
58921 #define SYNTH7__OVRCHANDECODER__READ(src) (u_int32_t)(src) & 0x00000001U argument
58922 #define SYNTH7__OVRCHANDECODER__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
58923 #define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \ argument
58927 #define SYNTH7__OVRCHANDECODER__VERIFY(src) \ argument
58941 #define SYNTH7__FORCE_FRACLSB__READ(src) \ argument
58944 #define SYNTH7__FORCE_FRACLSB__WRITE(src) \ argument
58947 #define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \ argument
58951 #define SYNTH7__FORCE_FRACLSB__VERIFY(src) \ argument
58965 #define SYNTH7__CHANFRAC__READ(src) (((u_int32_t)(src) & 0x0007fffcU) >> 2) argument
58966 #define SYNTH7__CHANFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0007fffcU) argument
58967 #define SYNTH7__CHANFRAC__MODIFY(dst, src) \ argument
58971 #define SYNTH7__CHANFRAC__VERIFY(src) \ argument
58979 #define SYNTH7__CHANSEL__READ(src) (((u_int32_t)(src) & 0x0ff80000U) >> 19) argument
58980 #define SYNTH7__CHANSEL__WRITE(src) (((u_int32_t)(src) << 19) & 0x0ff80000U) argument
58981 #define SYNTH7__CHANSEL__MODIFY(dst, src) \ argument
58985 #define SYNTH7__CHANSEL__VERIFY(src) \ argument
58993 #define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28) argument
58994 #define SYNTH7__AMODEREFSEL__WRITE(src) \ argument
58997 #define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \ argument
59001 #define SYNTH7__AMODEREFSEL__VERIFY(src) \ argument
59009 #define SYNTH7__FRACMODE__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
59010 #define SYNTH7__FRACMODE__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
59011 #define SYNTH7__FRACMODE__MODIFY(dst, src) \ argument
59015 #define SYNTH7__FRACMODE__VERIFY(src) \ argument
59029 #define SYNTH7__LOADSYNTHCHANNEL__READ(src) \ argument
59032 #define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \ argument
59035 #define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \ argument
59039 #define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \ argument
59066 #define SYNTH8__CPSTEERING_EN_FRACN__READ(src) (u_int32_t)(src) & 0x00000001U argument
59067 #define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \ argument
59070 #define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \ argument
59074 #define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \ argument
59088 #define SYNTH8__LOOP_ICPB__READ(src) (((u_int32_t)(src) & 0x000000feU) >> 1) argument
59089 #define SYNTH8__LOOP_ICPB__WRITE(src) (((u_int32_t)(src) << 1) & 0x000000feU) argument
59090 #define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \ argument
59094 #define SYNTH8__LOOP_ICPB__VERIFY(src) \ argument
59102 #define SYNTH8__LOOP_CSB__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) argument
59103 #define SYNTH8__LOOP_CSB__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) argument
59104 #define SYNTH8__LOOP_CSB__MODIFY(dst, src) \ argument
59108 #define SYNTH8__LOOP_CSB__VERIFY(src) \ argument
59116 #define SYNTH8__LOOP_RSB__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) argument
59117 #define SYNTH8__LOOP_RSB__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) argument
59118 #define SYNTH8__LOOP_RSB__MODIFY(dst, src) \ argument
59122 #define SYNTH8__LOOP_RSB__VERIFY(src) \ argument
59130 #define SYNTH8__LOOP_CPB__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) argument
59131 #define SYNTH8__LOOP_CPB__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) argument
59132 #define SYNTH8__LOOP_CPB__MODIFY(dst, src) \ argument
59136 #define SYNTH8__LOOP_CPB__VERIFY(src) \ argument
59144 #define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \ argument
59147 #define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \ argument
59150 #define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \ argument
59154 #define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \ argument
59162 #define SYNTH8__REFDIVB__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) argument
59163 #define SYNTH8__REFDIVB__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) argument
59164 #define SYNTH8__REFDIVB__MODIFY(dst, src) \ argument
59168 #define SYNTH8__REFDIVB__VERIFY(src) \ argument
59189 #define SYNTH9__PFDDELAY_INTN__READ(src) (u_int32_t)(src) & 0x00000001U argument
59190 #define SYNTH9__PFDDELAY_INTN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
59191 #define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \ argument
59195 #define SYNTH9__PFDDELAY_INTN__VERIFY(src) \ argument
59209 #define SYNTH9__SLOPE_ICPA0__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1) argument
59210 #define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU) argument
59211 #define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \ argument
59215 #define SYNTH9__SLOPE_ICPA0__VERIFY(src) \ argument
59223 #define SYNTH9__LOOP_ICPA0__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4) argument
59224 #define SYNTH9__LOOP_ICPA0__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U) argument
59225 #define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \ argument
59229 #define SYNTH9__LOOP_ICPA0__VERIFY(src) \ argument
59237 #define SYNTH9__LOOP_CSA0__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8) argument
59238 #define SYNTH9__LOOP_CSA0__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U) argument
59239 #define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \ argument
59243 #define SYNTH9__LOOP_CSA0__VERIFY(src) \ argument
59251 #define SYNTH9__LOOP_RSA0__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12) argument
59252 #define SYNTH9__LOOP_RSA0__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U) argument
59253 #define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \ argument
59257 #define SYNTH9__LOOP_RSA0__VERIFY(src) \ argument
59265 #define SYNTH9__LOOP_CPA0__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17) argument
59266 #define SYNTH9__LOOP_CPA0__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U) argument
59267 #define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \ argument
59271 #define SYNTH9__LOOP_CPA0__VERIFY(src) \ argument
59279 #define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \ argument
59282 #define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \ argument
59285 #define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \ argument
59289 #define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \ argument
59297 #define SYNTH9__REFDIVA__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) argument
59298 #define SYNTH9__REFDIVA__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) argument
59299 #define SYNTH9__REFDIVA__MODIFY(dst, src) \ argument
59303 #define SYNTH9__REFDIVA__VERIFY(src) \ argument
59324 #define SYNTH10__SPARE10A__READ(src) (u_int32_t)(src) & 0x00000003U argument
59325 #define SYNTH10__SPARE10A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
59326 #define SYNTH10__SPARE10A__MODIFY(dst, src) \ argument
59330 #define SYNTH10__SPARE10A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
59336 #define SYNTH10__PWDB_ICLOBIAS50__READ(src) \ argument
59339 #define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \ argument
59342 #define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \ argument
59346 #define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \ argument
59354 #define SYNTH10__PWDB_IRSPARE25__READ(src) \ argument
59357 #define SYNTH10__PWDB_IRSPARE25__WRITE(src) \ argument
59360 #define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \ argument
59364 #define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \ argument
59372 #define SYNTH10__PWDB_ICSPARE25__READ(src) \ argument
59375 #define SYNTH10__PWDB_ICSPARE25__WRITE(src) \ argument
59378 #define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \ argument
59382 #define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \ argument
59390 #define SYNTH10__SLOPE_ICPA1__READ(src) \ argument
59393 #define SYNTH10__SLOPE_ICPA1__WRITE(src) \ argument
59396 #define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \ argument
59400 #define SYNTH10__SLOPE_ICPA1__VERIFY(src) \ argument
59408 #define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) argument
59409 #define SYNTH10__LOOP_ICPA1__WRITE(src) \ argument
59412 #define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \ argument
59416 #define SYNTH10__LOOP_ICPA1__VERIFY(src) \ argument
59424 #define SYNTH10__LOOP_CSA1__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) argument
59425 #define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) argument
59426 #define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \ argument
59430 #define SYNTH10__LOOP_CSA1__VERIFY(src) \ argument
59438 #define SYNTH10__LOOP_RSA1__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) argument
59439 #define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) argument
59440 #define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \ argument
59444 #define SYNTH10__LOOP_RSA1__VERIFY(src) \ argument
59452 #define SYNTH10__LOOP_CPA1__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) argument
59453 #define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) argument
59454 #define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \ argument
59458 #define SYNTH10__LOOP_CPA1__VERIFY(src) \ argument
59479 #define SYNTH11__SPARE11A__READ(src) (u_int32_t)(src) & 0x0000001fU argument
59480 #define SYNTH11__SPARE11A__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
59481 #define SYNTH11__SPARE11A__MODIFY(dst, src) \ argument
59485 #define SYNTH11__SPARE11A__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
59491 #define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \ argument
59494 #define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \ argument
59497 #define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \ argument
59501 #define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \ argument
59515 #define SYNTH11__LOREFSEL__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6) argument
59516 #define SYNTH11__LOREFSEL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U) argument
59517 #define SYNTH11__LOREFSEL__MODIFY(dst, src) \ argument
59521 #define SYNTH11__LOREFSEL__VERIFY(src) \ argument
59529 #define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) argument
59530 #define SYNTH11__LOBUF2GTUNE__WRITE(src) \ argument
59533 #define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \ argument
59537 #define SYNTH11__LOBUF2GTUNE__VERIFY(src) \ argument
59545 #define SYNTH11__CPSTEERING_MODE__READ(src) \ argument
59548 #define SYNTH11__CPSTEERING_MODE__WRITE(src) \ argument
59551 #define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \ argument
59555 #define SYNTH11__CPSTEERING_MODE__VERIFY(src) \ argument
59569 #define SYNTH11__SLOPE_ICPA2__READ(src) \ argument
59572 #define SYNTH11__SLOPE_ICPA2__WRITE(src) \ argument
59575 #define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \ argument
59579 #define SYNTH11__SLOPE_ICPA2__VERIFY(src) \ argument
59587 #define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14) argument
59588 #define SYNTH11__LOOP_ICPA2__WRITE(src) \ argument
59591 #define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \ argument
59595 #define SYNTH11__LOOP_ICPA2__VERIFY(src) \ argument
59603 #define SYNTH11__LOOP_CSA2__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18) argument
59604 #define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U) argument
59605 #define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \ argument
59609 #define SYNTH11__LOOP_CSA2__VERIFY(src) \ argument
59617 #define SYNTH11__LOOP_RSA2__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22) argument
59618 #define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U) argument
59619 #define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \ argument
59623 #define SYNTH11__LOOP_RSA2__VERIFY(src) \ argument
59631 #define SYNTH11__LOOP_CPA2__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) argument
59632 #define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) argument
59633 #define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \ argument
59637 #define SYNTH11__LOOP_CPA2__VERIFY(src) \ argument
59658 #define SYNTH12__SPARE12A__READ(src) (u_int32_t)(src) & 0x000003ffU argument
59659 #define SYNTH12__SPARE12A__WRITE(src) ((u_int32_t)(src) & 0x000003ffU) argument
59660 #define SYNTH12__SPARE12A__MODIFY(dst, src) \ argument
59664 #define SYNTH12__SPARE12A__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU))) argument
59670 #define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \ argument
59673 #define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \ argument
59676 #define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \ argument
59680 #define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \ argument
59688 #define SYNTH12__CPLOWLK_FRACN__READ(src) \ argument
59691 #define SYNTH12__CPLOWLK_FRACN__WRITE(src) \ argument
59694 #define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \ argument
59698 #define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \ argument
59712 #define SYNTH12__CPBIAS_FRACN__READ(src) \ argument
59715 #define SYNTH12__CPBIAS_FRACN__WRITE(src) \ argument
59718 #define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \ argument
59722 #define SYNTH12__CPBIAS_FRACN__VERIFY(src) \ argument
59730 #define SYNTH12__SYNTHDIGOUTEN__READ(src) \ argument
59733 #define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \ argument
59736 #define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \ argument
59740 #define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \ argument
59754 #define SYNTH12__STRCONT__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
59755 #define SYNTH12__STRCONT__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
59756 #define SYNTH12__STRCONT__MODIFY(dst, src) \ argument
59760 #define SYNTH12__STRCONT__VERIFY(src) \ argument
59774 #define SYNTH12__VREFMUL3__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) argument
59775 #define SYNTH12__VREFMUL3__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) argument
59776 #define SYNTH12__VREFMUL3__MODIFY(dst, src) \ argument
59780 #define SYNTH12__VREFMUL3__VERIFY(src) \ argument
59788 #define SYNTH12__VREFMUL2__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) argument
59789 #define SYNTH12__VREFMUL2__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) argument
59790 #define SYNTH12__VREFMUL2__MODIFY(dst, src) \ argument
59794 #define SYNTH12__VREFMUL2__VERIFY(src) \ argument
59802 #define SYNTH12__VREFMUL1__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
59803 #define SYNTH12__VREFMUL1__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
59804 #define SYNTH12__VREFMUL1__MODIFY(dst, src) \ argument
59808 #define SYNTH12__VREFMUL1__VERIFY(src) \ argument
59816 #define SYNTH12__CLK_DOUBLER_EN__READ(src) \ argument
59819 #define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \ argument
59822 #define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \ argument
59826 #define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \ argument
59853 #define SYNTH13__SPARE13A__READ(src) (u_int32_t)(src) & 0x00000001U argument
59854 #define SYNTH13__SPARE13A__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
59855 #define SYNTH13__SPARE13A__MODIFY(dst, src) \ argument
59859 #define SYNTH13__SPARE13A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
59871 #define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \ argument
59874 #define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \ argument
59877 #define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \ argument
59881 #define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \ argument
59889 #define SYNTH13__LOOP_ICPA_FRACN__READ(src) \ argument
59892 #define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \ argument
59895 #define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \ argument
59899 #define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \ argument
59907 #define SYNTH13__LOOP_CSA_FRACN__READ(src) \ argument
59910 #define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \ argument
59913 #define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \ argument
59917 #define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \ argument
59925 #define SYNTH13__LOOP_RSA_FRACN__READ(src) \ argument
59928 #define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \ argument
59931 #define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \ argument
59935 #define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \ argument
59943 #define SYNTH13__LOOP_CPA_FRACN__READ(src) \ argument
59946 #define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \ argument
59949 #define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \ argument
59953 #define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \ argument
59961 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \ argument
59964 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \ argument
59967 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \ argument
59971 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \ argument
59979 #define SYNTH13__REFDIVA_FRACN__READ(src) \ argument
59982 #define SYNTH13__REFDIVA_FRACN__WRITE(src) \ argument
59985 #define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \ argument
59989 #define SYNTH13__REFDIVA_FRACN__VERIFY(src) \ argument
60010 #define SYNTH14__SPARE14A__READ(src) (u_int32_t)(src) & 0x00000003U argument
60011 #define SYNTH14__SPARE14A__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
60012 #define SYNTH14__SPARE14A__MODIFY(dst, src) \ argument
60016 #define SYNTH14__SPARE14A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
60022 #define SYNTH14__LOBUF5GTUNE_3__READ(src) \ argument
60025 #define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \ argument
60028 #define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \ argument
60032 #define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \ argument
60040 #define SYNTH14__LOBUF2GTUNE_3__READ(src) \ argument
60043 #define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \ argument
60046 #define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \ argument
60050 #define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \ argument
60058 #define SYNTH14__LOBUF5GTUNE_2__READ(src) \ argument
60061 #define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \ argument
60064 #define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \ argument
60068 #define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \ argument
60076 #define SYNTH14__LOBUF2GTUNE_2__READ(src) \ argument
60079 #define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \ argument
60082 #define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \ argument
60086 #define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \ argument
60094 #define SYNTH14__PWD_LOBUF5G_3__READ(src) \ argument
60097 #define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \ argument
60100 #define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \ argument
60104 #define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \ argument
60118 #define SYNTH14__PWD_LOBUF2G_3__READ(src) \ argument
60121 #define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \ argument
60124 #define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \ argument
60128 #define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \ argument
60142 #define SYNTH14__PWD_LOBUF5G_2__READ(src) \ argument
60145 #define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \ argument
60148 #define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \ argument
60152 #define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \ argument
60166 #define SYNTH14__PWD_LOBUF2G_2__READ(src) \ argument
60169 #define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \ argument
60172 #define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \ argument
60176 #define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \ argument
60190 #define SYNTH14__PWUPLO23_PD__READ(src) \ argument
60193 #define SYNTH14__PWUPLO23_PD__WRITE(src) \ argument
60196 #define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \ argument
60200 #define SYNTH14__PWUPLO23_PD__VERIFY(src) \ argument
60208 #define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \ argument
60211 #define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \ argument
60214 #define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \ argument
60218 #define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \ argument
60226 #define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \ argument
60229 #define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \ argument
60232 #define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \ argument
60236 #define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \ argument
60244 #define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \ argument
60247 #define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \ argument
60250 #define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \ argument
60254 #define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \ argument
60262 #define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \ argument
60265 #define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \ argument
60268 #define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \ argument
60272 #define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \ argument
60280 #define SYNTH14__PWDB_ICLVLSHFT__READ(src) \ argument
60283 #define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \ argument
60286 #define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \ argument
60290 #define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \ argument
60311 #define BIAS1__SPARE1__READ(src) (u_int32_t)(src) & 0x00000007U argument
60312 #define BIAS1__SPARE1__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
60313 #define BIAS1__SPARE1__MODIFY(dst, src) \ argument
60317 #define BIAS1__SPARE1__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) argument
60323 #define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3) argument
60324 #define BIAS1__PWD_IC100PCIE__WRITE(src) \ argument
60327 #define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \ argument
60331 #define BIAS1__PWD_IC100PCIE__VERIFY(src) \ argument
60339 #define BIAS1__PWD_IC25V2IQ__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6) argument
60340 #define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U) argument
60341 #define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \ argument
60345 #define BIAS1__PWD_IC25V2IQ__VERIFY(src) \ argument
60353 #define BIAS1__PWD_IC25V2II__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) argument
60354 #define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) argument
60355 #define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \ argument
60359 #define BIAS1__PWD_IC25V2II__VERIFY(src) \ argument
60367 #define BIAS1__PWD_IC25BB__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) argument
60368 #define BIAS1__PWD_IC25BB__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) argument
60369 #define BIAS1__PWD_IC25BB__MODIFY(dst, src) \ argument
60373 #define BIAS1__PWD_IC25BB__VERIFY(src) \ argument
60381 #define BIAS1__PWD_IC25DAC__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) argument
60382 #define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) argument
60383 #define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \ argument
60387 #define BIAS1__PWD_IC25DAC__VERIFY(src) \ argument
60395 #define BIAS1__PWD_IC25FIR__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) argument
60396 #define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) argument
60397 #define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \ argument
60401 #define BIAS1__PWD_IC25FIR__VERIFY(src) \ argument
60409 #define BIAS1__PWD_IC25ADC__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) argument
60410 #define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) argument
60411 #define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \ argument
60415 #define BIAS1__PWD_IC25ADC__VERIFY(src) \ argument
60423 #define BIAS1__BIAS_SEL__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24) argument
60424 #define BIAS1__BIAS_SEL__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U) argument
60425 #define BIAS1__BIAS_SEL__MODIFY(dst, src) \ argument
60429 #define BIAS1__BIAS_SEL__VERIFY(src) \ argument
60450 #define BIAS2__SPARE2__READ(src) (u_int32_t)(src) & 0x0000001fU argument
60451 #define BIAS2__SPARE2__WRITE(src) ((u_int32_t)(src) & 0x0000001fU) argument
60452 #define BIAS2__SPARE2__MODIFY(dst, src) \ argument
60456 #define BIAS2__SPARE2__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU))) argument
60462 #define BIAS2__PWD_IC25XTALREG__READ(src) \ argument
60465 #define BIAS2__PWD_IC25XTALREG__WRITE(src) \ argument
60468 #define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \ argument
60472 #define BIAS2__PWD_IC25XTALREG__VERIFY(src) \ argument
60480 #define BIAS2__PWD_IC25XTAL__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) argument
60481 #define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) argument
60482 #define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \ argument
60486 #define BIAS2__PWD_IC25XTAL__VERIFY(src) \ argument
60494 #define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11) argument
60495 #define BIAS2__PWD_IC25TXRF__WRITE(src) \ argument
60498 #define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \ argument
60502 #define BIAS2__PWD_IC25TXRF__VERIFY(src) \ argument
60510 #define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14) argument
60511 #define BIAS2__PWD_IC25RXRF__WRITE(src) \ argument
60514 #define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \ argument
60518 #define BIAS2__PWD_IC25RXRF__VERIFY(src) \ argument
60526 #define BIAS2__PWD_IC25SYNTH__READ(src) \ argument
60529 #define BIAS2__PWD_IC25SYNTH__WRITE(src) \ argument
60532 #define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \ argument
60536 #define BIAS2__PWD_IC25SYNTH__VERIFY(src) \ argument
60544 #define BIAS2__PWD_IC25PLLREG__READ(src) \ argument
60547 #define BIAS2__PWD_IC25PLLREG__WRITE(src) \ argument
60550 #define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \ argument
60554 #define BIAS2__PWD_IC25PLLREG__VERIFY(src) \ argument
60562 #define BIAS2__PWD_IC25PLLCP2__READ(src) \ argument
60565 #define BIAS2__PWD_IC25PLLCP2__WRITE(src) \ argument
60568 #define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \ argument
60572 #define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \ argument
60580 #define BIAS2__PWD_IC25PLLCP__READ(src) \ argument
60583 #define BIAS2__PWD_IC25PLLCP__WRITE(src) \ argument
60586 #define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \ argument
60590 #define BIAS2__PWD_IC25PLLCP__VERIFY(src) \ argument
60598 #define BIAS2__PWD_IC25PLLGM__READ(src) \ argument
60601 #define BIAS2__PWD_IC25PLLGM__WRITE(src) \ argument
60604 #define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \ argument
60608 #define BIAS2__PWD_IC25PLLGM__VERIFY(src) \ argument
60629 #define BIAS3__SPARE3__READ(src) (u_int32_t)(src) & 0x00000003U argument
60630 #define BIAS3__SPARE3__WRITE(src) ((u_int32_t)(src) & 0x00000003U) argument
60631 #define BIAS3__SPARE3__MODIFY(dst, src) \ argument
60635 #define BIAS3__SPARE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U))) argument
60641 #define BIAS3__PWD_IR25XTALREG__READ(src) \ argument
60644 #define BIAS3__PWD_IR25XTALREG__WRITE(src) \ argument
60647 #define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \ argument
60651 #define BIAS3__PWD_IR25XTALREG__VERIFY(src) \ argument
60659 #define BIAS3__PWD_IR25TXRF__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5) argument
60660 #define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U) argument
60661 #define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \ argument
60665 #define BIAS3__PWD_IR25TXRF__VERIFY(src) \ argument
60673 #define BIAS3__PWD_IR25RXRF__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8) argument
60674 #define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U) argument
60675 #define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \ argument
60679 #define BIAS3__PWD_IR25RXRF__VERIFY(src) \ argument
60687 #define BIAS3__PWD_IR25SYNTH__READ(src) \ argument
60690 #define BIAS3__PWD_IR25SYNTH__WRITE(src) \ argument
60693 #define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \ argument
60697 #define BIAS3__PWD_IR25SYNTH__VERIFY(src) \ argument
60705 #define BIAS3__PWD_IR25PLLREG__READ(src) \ argument
60708 #define BIAS3__PWD_IR25PLLREG__WRITE(src) \ argument
60711 #define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \ argument
60715 #define BIAS3__PWD_IR25PLLREG__VERIFY(src) \ argument
60723 #define BIAS3__PWD_IR25BB__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17) argument
60724 #define BIAS3__PWD_IR25BB__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U) argument
60725 #define BIAS3__PWD_IR25BB__MODIFY(dst, src) \ argument
60729 #define BIAS3__PWD_IR25BB__VERIFY(src) \ argument
60737 #define BIAS3__PWD_IR50DAC__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20) argument
60738 #define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U) argument
60739 #define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \ argument
60743 #define BIAS3__PWD_IR50DAC__VERIFY(src) \ argument
60751 #define BIAS3__PWD_IR25DAC__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23) argument
60752 #define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U) argument
60753 #define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \ argument
60757 #define BIAS3__PWD_IR25DAC__VERIFY(src) \ argument
60765 #define BIAS3__PWD_IR25FIR__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) argument
60766 #define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) argument
60767 #define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \ argument
60771 #define BIAS3__PWD_IR25FIR__VERIFY(src) \ argument
60779 #define BIAS3__PWD_IR50ADC__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
60780 #define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
60781 #define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \ argument
60785 #define BIAS3__PWD_IR50ADC__VERIFY(src) \ argument
60806 #define BIAS4__SPARE4__READ(src) (u_int32_t)(src) & 0x00003fffU argument
60807 #define BIAS4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x00003fffU) argument
60808 #define BIAS4__SPARE4__MODIFY(dst, src) \ argument
60812 #define BIAS4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x00003fffU))) argument
60818 #define BIAS4__PWD_IR25XPABIAS__READ(src) \ argument
60821 #define BIAS4__PWD_IR25XPABIAS__WRITE(src) \ argument
60824 #define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \ argument
60828 #define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \ argument
60836 #define BIAS4__PWD_IR25THERMADC__READ(src) \ argument
60839 #define BIAS4__PWD_IR25THERMADC__WRITE(src) \ argument
60842 #define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \ argument
60846 #define BIAS4__PWD_IR25THERMADC__VERIFY(src) \ argument
60854 #define BIAS4__PWD_IR25OTPREG__READ(src) \ argument
60857 #define BIAS4__PWD_IR25OTPREG__WRITE(src) \ argument
60860 #define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \ argument
60864 #define BIAS4__PWD_IR25OTPREG__VERIFY(src) \ argument
60872 #define BIAS4__PWD_IC25XPABIAS__READ(src) \ argument
60875 #define BIAS4__PWD_IC25XPABIAS__WRITE(src) \ argument
60878 #define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \ argument
60882 #define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \ argument
60890 #define BIAS4__PWD_IC25SPAREB__READ(src) \ argument
60893 #define BIAS4__PWD_IC25SPAREB__WRITE(src) \ argument
60896 #define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \ argument
60900 #define BIAS4__PWD_IC25SPAREB__VERIFY(src) \ argument
60908 #define BIAS4__PWD_IC25SPAREA__READ(src) \ argument
60911 #define BIAS4__PWD_IC25SPAREA__WRITE(src) \ argument
60914 #define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \ argument
60918 #define BIAS4__PWD_IC25SPAREA__VERIFY(src) \ argument
60939 #define RXTX1__SCFIR_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U argument
60940 #define RXTX1__SCFIR_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
60941 #define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \ argument
60945 #define RXTX1__SCFIR_GAIN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
60957 #define RXTX1__MANRXGAIN__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
60958 #define RXTX1__MANRXGAIN__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
60959 #define RXTX1__MANRXGAIN__MODIFY(dst, src) \ argument
60963 #define RXTX1__MANRXGAIN__VERIFY(src) \ argument
60977 #define RXTX1__AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x0000003cU) >> 2) argument
60978 #define RXTX1__AGC_DBDAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000003cU) argument
60979 #define RXTX1__AGC_DBDAC__MODIFY(dst, src) \ argument
60983 #define RXTX1__AGC_DBDAC__VERIFY(src) \ argument
60991 #define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
60992 #define RXTX1__OVR_AGC_DBDAC__WRITE(src) \ argument
60995 #define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \ argument
60999 #define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \ argument
61013 #define RXTX1__ENABLE_PAL__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
61014 #define RXTX1__ENABLE_PAL__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) argument
61015 #define RXTX1__ENABLE_PAL__MODIFY(dst, src) \ argument
61019 #define RXTX1__ENABLE_PAL__VERIFY(src) \ argument
61033 #define RXTX1__ENABLE_PAL_OVR__READ(src) \ argument
61036 #define RXTX1__ENABLE_PAL_OVR__WRITE(src) \ argument
61039 #define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \ argument
61043 #define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \ argument
61057 #define RXTX1__TX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) argument
61058 #define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U) argument
61059 #define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \ argument
61063 #define RXTX1__TX1DB_BIQUAD__VERIFY(src) \ argument
61071 #define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12) argument
61072 #define RXTX1__TX6DB_BIQUAD__WRITE(src) \ argument
61075 #define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \ argument
61079 #define RXTX1__TX6DB_BIQUAD__VERIFY(src) \ argument
61087 #define RXTX1__PADRVHALFGN2G__READ(src) \ argument
61090 #define RXTX1__PADRVHALFGN2G__WRITE(src) \ argument
61093 #define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \ argument
61097 #define RXTX1__PADRVHALFGN2G__VERIFY(src) \ argument
61111 #define RXTX1__PADRV2GN__READ(src) (((u_int32_t)(src) & 0x00078000U) >> 15) argument
61112 #define RXTX1__PADRV2GN__WRITE(src) (((u_int32_t)(src) << 15) & 0x00078000U) argument
61113 #define RXTX1__PADRV2GN__MODIFY(dst, src) \ argument
61117 #define RXTX1__PADRV2GN__VERIFY(src) \ argument
61125 #define RXTX1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19) argument
61126 #define RXTX1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U) argument
61127 #define RXTX1__PADRV3GN5G__MODIFY(dst, src) \ argument
61131 #define RXTX1__PADRV3GN5G__VERIFY(src) \ argument
61139 #define RXTX1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23) argument
61140 #define RXTX1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U) argument
61141 #define RXTX1__PADRV4GN5G__MODIFY(dst, src) \ argument
61145 #define RXTX1__PADRV4GN5G__VERIFY(src) \ argument
61153 #define RXTX1__TXBB_GC__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27) argument
61154 #define RXTX1__TXBB_GC__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U) argument
61155 #define RXTX1__TXBB_GC__MODIFY(dst, src) \ argument
61159 #define RXTX1__TXBB_GC__VERIFY(src) \ argument
61167 #define RXTX1__MANTXGAIN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
61168 #define RXTX1__MANTXGAIN__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
61169 #define RXTX1__MANTXGAIN__MODIFY(dst, src) \ argument
61173 #define RXTX1__MANTXGAIN__VERIFY(src) \ argument
61200 #define RXTX2__BMODE__READ(src) (u_int32_t)(src) & 0x00000001U argument
61201 #define RXTX2__BMODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
61202 #define RXTX2__BMODE__MODIFY(dst, src) \ argument
61206 #define RXTX2__BMODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
61214 #define RXTX2__BMODE_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
61215 #define RXTX2__BMODE_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
61216 #define RXTX2__BMODE_OVR__MODIFY(dst, src) \ argument
61220 #define RXTX2__BMODE_OVR__VERIFY(src) \ argument
61234 #define RXTX2__SYNTHON__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
61235 #define RXTX2__SYNTHON__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
61236 #define RXTX2__SYNTHON__MODIFY(dst, src) \ argument
61240 #define RXTX2__SYNTHON__VERIFY(src) \ argument
61254 #define RXTX2__SYNTHON_OVR__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
61255 #define RXTX2__SYNTHON_OVR__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
61256 #define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \ argument
61260 #define RXTX2__SYNTHON_OVR__VERIFY(src) \ argument
61274 #define RXTX2__BW_ST__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4) argument
61275 #define RXTX2__BW_ST__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U) argument
61276 #define RXTX2__BW_ST__MODIFY(dst, src) \ argument
61280 #define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U))) argument
61286 #define RXTX2__BW_ST_OVR__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
61287 #define RXTX2__BW_ST_OVR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) argument
61288 #define RXTX2__BW_ST_OVR__MODIFY(dst, src) \ argument
61292 #define RXTX2__BW_ST_OVR__VERIFY(src) \ argument
61306 #define RXTX2__TXON__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
61307 #define RXTX2__TXON__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) argument
61308 #define RXTX2__TXON__MODIFY(dst, src) \ argument
61312 #define RXTX2__TXON__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00000080U))) argument
61324 #define RXTX2__TXON_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
61325 #define RXTX2__TXON_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) argument
61326 #define RXTX2__TXON_OVR__MODIFY(dst, src) \ argument
61330 #define RXTX2__TXON_OVR__VERIFY(src) \ argument
61344 #define RXTX2__PAON__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
61345 #define RXTX2__PAON__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) argument
61346 #define RXTX2__PAON__MODIFY(dst, src) \ argument
61350 #define RXTX2__PAON__VERIFY(src) (!((((u_int32_t)(src) << 9) & ~0x00000200U))) argument
61362 #define RXTX2__PAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
61363 #define RXTX2__PAON_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) argument
61364 #define RXTX2__PAON_OVR__MODIFY(dst, src) \ argument
61368 #define RXTX2__PAON_OVR__VERIFY(src) \ argument
61382 #define RXTX2__RXON__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
61383 #define RXTX2__RXON__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
61384 #define RXTX2__RXON__MODIFY(dst, src) \ argument
61388 #define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U))) argument
61400 #define RXTX2__RXON_OVR__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) argument
61401 #define RXTX2__RXON_OVR__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) argument
61402 #define RXTX2__RXON_OVR__MODIFY(dst, src) \ argument
61406 #define RXTX2__RXON_OVR__VERIFY(src) \ argument
61420 #define RXTX2__AGCON__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13) argument
61421 #define RXTX2__AGCON__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U) argument
61422 #define RXTX2__AGCON__MODIFY(dst, src) \ argument
61426 #define RXTX2__AGCON__VERIFY(src) \ argument
61440 #define RXTX2__AGCON_OVR__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) argument
61441 #define RXTX2__AGCON_OVR__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U) argument
61442 #define RXTX2__AGCON_OVR__MODIFY(dst, src) \ argument
61446 #define RXTX2__AGCON_OVR__VERIFY(src) \ argument
61460 #define RXTX2__TXMOD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) argument
61461 #define RXTX2__TXMOD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) argument
61462 #define RXTX2__TXMOD__MODIFY(dst, src) \ argument
61466 #define RXTX2__TXMOD__VERIFY(src) \ argument
61474 #define RXTX2__TXMOD_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
61475 #define RXTX2__TXMOD_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
61476 #define RXTX2__TXMOD_OVR__MODIFY(dst, src) \ argument
61480 #define RXTX2__TXMOD_OVR__VERIFY(src) \ argument
61494 #define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19) argument
61495 #define RXTX2__RX1DB_BIQUAD__WRITE(src) \ argument
61498 #define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \ argument
61502 #define RXTX2__RX1DB_BIQUAD__VERIFY(src) \ argument
61510 #define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22) argument
61511 #define RXTX2__RX6DB_BIQUAD__WRITE(src) \ argument
61514 #define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \ argument
61518 #define RXTX2__RX6DB_BIQUAD__VERIFY(src) \ argument
61526 #define RXTX2__MXRGAIN__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24) argument
61527 #define RXTX2__MXRGAIN__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U) argument
61528 #define RXTX2__MXRGAIN__MODIFY(dst, src) \ argument
61532 #define RXTX2__MXRGAIN__VERIFY(src) \ argument
61540 #define RXTX2__VGAGAIN__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26) argument
61541 #define RXTX2__VGAGAIN__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U) argument
61542 #define RXTX2__VGAGAIN__MODIFY(dst, src) \ argument
61546 #define RXTX2__VGAGAIN__VERIFY(src) \ argument
61554 #define RXTX2__LNAGAIN__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
61555 #define RXTX2__LNAGAIN__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
61556 #define RXTX2__LNAGAIN__MODIFY(dst, src) \ argument
61560 #define RXTX2__LNAGAIN__VERIFY(src) \ argument
61581 #define RXTX3__XLNABIAS_PWD__READ(src) (u_int32_t)(src) & 0x00000001U argument
61582 #define RXTX3__XLNABIAS_PWD__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
61583 #define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \ argument
61587 #define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
61599 #define RXTX3__XLNAON__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
61600 #define RXTX3__XLNAON__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
61601 #define RXTX3__XLNAON__MODIFY(dst, src) \ argument
61605 #define RXTX3__XLNAON__VERIFY(src) \ argument
61619 #define RXTX3__XLNAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
61620 #define RXTX3__XLNAON_OVR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
61621 #define RXTX3__XLNAON_OVR__MODIFY(dst, src) \ argument
61625 #define RXTX3__XLNAON_OVR__VERIFY(src) \ argument
61639 #define RXTX3__DACFULLSCALE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
61640 #define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
61641 #define RXTX3__DACFULLSCALE__MODIFY(dst, src) \ argument
61645 #define RXTX3__DACFULLSCALE__VERIFY(src) \ argument
61659 #define RXTX3__DACRSTB__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
61660 #define RXTX3__DACRSTB__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
61661 #define RXTX3__DACRSTB__MODIFY(dst, src) \ argument
61665 #define RXTX3__DACRSTB__VERIFY(src) \ argument
61679 #define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
61680 #define RXTX3__ADDACLOOPBACK__WRITE(src) \ argument
61683 #define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \ argument
61687 #define RXTX3__ADDACLOOPBACK__VERIFY(src) \ argument
61701 #define RXTX3__ADCSHORT__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
61702 #define RXTX3__ADCSHORT__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) argument
61703 #define RXTX3__ADCSHORT__MODIFY(dst, src) \ argument
61707 #define RXTX3__ADCSHORT__VERIFY(src) \ argument
61721 #define RXTX3__DACPWD__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
61722 #define RXTX3__DACPWD__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) argument
61723 #define RXTX3__DACPWD__MODIFY(dst, src) \ argument
61727 #define RXTX3__DACPWD__VERIFY(src) \ argument
61741 #define RXTX3__DACPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
61742 #define RXTX3__DACPWD_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) argument
61743 #define RXTX3__DACPWD_OVR__MODIFY(dst, src) \ argument
61747 #define RXTX3__DACPWD_OVR__VERIFY(src) \ argument
61761 #define RXTX3__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
61762 #define RXTX3__ADCPWD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) argument
61763 #define RXTX3__ADCPWD__MODIFY(dst, src) \ argument
61767 #define RXTX3__ADCPWD__VERIFY(src) \ argument
61781 #define RXTX3__ADCPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
61782 #define RXTX3__ADCPWD_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) argument
61783 #define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \ argument
61787 #define RXTX3__ADCPWD_OVR__VERIFY(src) \ argument
61801 #define RXTX3__AGC_CALDAC__READ(src) (((u_int32_t)(src) & 0x0001f800U) >> 11) argument
61802 #define RXTX3__AGC_CALDAC__WRITE(src) (((u_int32_t)(src) << 11) & 0x0001f800U) argument
61803 #define RXTX3__AGC_CALDAC__MODIFY(dst, src) \ argument
61807 #define RXTX3__AGC_CALDAC__VERIFY(src) \ argument
61815 #define RXTX3__AGC_CAL__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) argument
61816 #define RXTX3__AGC_CAL__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) argument
61817 #define RXTX3__AGC_CAL__MODIFY(dst, src) \ argument
61821 #define RXTX3__AGC_CAL__VERIFY(src) \ argument
61835 #define RXTX3__AGC_CAL_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
61836 #define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
61837 #define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \ argument
61841 #define RXTX3__AGC_CAL_OVR__VERIFY(src) \ argument
61855 #define RXTX3__LOFORCEDON__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) argument
61856 #define RXTX3__LOFORCEDON__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) argument
61857 #define RXTX3__LOFORCEDON__MODIFY(dst, src) \ argument
61861 #define RXTX3__LOFORCEDON__VERIFY(src) \ argument
61875 #define RXTX3__CALRESIDUE__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) argument
61876 #define RXTX3__CALRESIDUE__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) argument
61877 #define RXTX3__CALRESIDUE__MODIFY(dst, src) \ argument
61881 #define RXTX3__CALRESIDUE__VERIFY(src) \ argument
61895 #define RXTX3__CALRESIDUE_OVR__READ(src) \ argument
61898 #define RXTX3__CALRESIDUE_OVR__WRITE(src) \ argument
61901 #define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \ argument
61905 #define RXTX3__CALRESIDUE_OVR__VERIFY(src) \ argument
61919 #define RXTX3__CALFC__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) argument
61920 #define RXTX3__CALFC__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) argument
61921 #define RXTX3__CALFC__MODIFY(dst, src) \ argument
61925 #define RXTX3__CALFC__VERIFY(src) \ argument
61939 #define RXTX3__CALFC_OVR__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) argument
61940 #define RXTX3__CALFC_OVR__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) argument
61941 #define RXTX3__CALFC_OVR__MODIFY(dst, src) \ argument
61945 #define RXTX3__CALFC_OVR__VERIFY(src) \ argument
61959 #define RXTX3__CALTX__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
61960 #define RXTX3__CALTX__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) argument
61961 #define RXTX3__CALTX__MODIFY(dst, src) \ argument
61965 #define RXTX3__CALTX__VERIFY(src) \ argument
61979 #define RXTX3__CALTX_OVR__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) argument
61980 #define RXTX3__CALTX_OVR__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) argument
61981 #define RXTX3__CALTX_OVR__MODIFY(dst, src) \ argument
61985 #define RXTX3__CALTX_OVR__VERIFY(src) \ argument
61999 #define RXTX3__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) argument
62000 #define RXTX3__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) argument
62001 #define RXTX3__CALTXSHIFT__MODIFY(dst, src) \ argument
62005 #define RXTX3__CALTXSHIFT__VERIFY(src) \ argument
62019 #define RXTX3__CALTXSHIFT_OVR__READ(src) \ argument
62022 #define RXTX3__CALTXSHIFT_OVR__WRITE(src) \ argument
62025 #define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \ argument
62029 #define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \ argument
62043 #define RXTX3__CALPA__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
62044 #define RXTX3__CALPA__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
62045 #define RXTX3__CALPA__MODIFY(dst, src) \ argument
62049 #define RXTX3__CALPA__VERIFY(src) \ argument
62063 #define RXTX3__CALPA_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
62064 #define RXTX3__CALPA_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
62065 #define RXTX3__CALPA_OVR__MODIFY(dst, src) \ argument
62069 #define RXTX3__CALPA_OVR__VERIFY(src) \ argument
62083 #define RXTX3__SPURON__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
62084 #define RXTX3__SPURON__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
62085 #define RXTX3__SPURON__MODIFY(dst, src) \ argument
62089 #define RXTX3__SPURON__VERIFY(src) \ argument
62103 #define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
62104 #define RXTX3__PAL_LOCKEDEN__WRITE(src) \ argument
62107 #define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \ argument
62111 #define RXTX3__PAL_LOCKEDEN__VERIFY(src) \ argument
62138 #define RXTX4__SPARE4__READ(src) (u_int32_t)(src) & 0x001fffffU argument
62139 #define RXTX4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x001fffffU) argument
62140 #define RXTX4__SPARE4__MODIFY(dst, src) \ argument
62144 #define RXTX4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x001fffffU))) argument
62150 #define RXTX4__OBDB2G_SSCTRL__READ(src) \ argument
62153 #define RXTX4__OBDB2G_SSCTRL__WRITE(src) \ argument
62156 #define RXTX4__OBDB2G_SSCTRL__MODIFY(dst, src) \ argument
62160 #define RXTX4__OBDB2G_SSCTRL__VERIFY(src) \ argument
62174 #define RXTX4__OBDB5G_SSCTRL__READ(src) \ argument
62177 #define RXTX4__OBDB5G_SSCTRL__WRITE(src) \ argument
62180 #define RXTX4__OBDB5G_SSCTRL__MODIFY(dst, src) \ argument
62184 #define RXTX4__OBDB5G_SSCTRL__VERIFY(src) \ argument
62198 #define RXTX4__TESTIQ_ON__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) argument
62199 #define RXTX4__TESTIQ_ON__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) argument
62200 #define RXTX4__TESTIQ_ON__MODIFY(dst, src) \ argument
62204 #define RXTX4__TESTIQ_ON__VERIFY(src) \ argument
62218 #define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
62219 #define RXTX4__TESTIQ_BUFEN__WRITE(src) \ argument
62222 #define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \ argument
62226 #define RXTX4__TESTIQ_BUFEN__VERIFY(src) \ argument
62240 #define RXTX4__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) argument
62241 #define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) argument
62242 #define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \ argument
62246 #define RXTX4__TESTIQ_RSEL__VERIFY(src) \ argument
62260 #define RXTX4__TURBOADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) argument
62261 #define RXTX4__TURBOADC__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U) argument
62262 #define RXTX4__TURBOADC__MODIFY(dst, src) \ argument
62266 #define RXTX4__TURBOADC__VERIFY(src) \ argument
62280 #define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
62281 #define RXTX4__TURBOADC_OVR__WRITE(src) \ argument
62284 #define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \ argument
62288 #define RXTX4__TURBOADC_OVR__VERIFY(src) \ argument
62302 #define RXTX4__THERMON__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
62303 #define RXTX4__THERMON__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
62304 #define RXTX4__THERMON__MODIFY(dst, src) \ argument
62308 #define RXTX4__THERMON__VERIFY(src) \ argument
62322 #define RXTX4__THERMON_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
62323 #define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
62324 #define RXTX4__THERMON_OVR__MODIFY(dst, src) \ argument
62328 #define RXTX4__THERMON_OVR__VERIFY(src) \ argument
62342 #define RXTX4__XLNA_STRENGTH__READ(src) \ argument
62345 #define RXTX4__XLNA_STRENGTH__WRITE(src) \ argument
62348 #define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \ argument
62352 #define RXTX4__XLNA_STRENGTH__VERIFY(src) \ argument
62373 #define BB1__I2V_CURR2X__READ(src) (u_int32_t)(src) & 0x00000001U argument
62374 #define BB1__I2V_CURR2X__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
62375 #define BB1__I2V_CURR2X__MODIFY(dst, src) \ argument
62379 #define BB1__I2V_CURR2X__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
62391 #define BB1__ENABLE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
62392 #define BB1__ENABLE_LOQ__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
62393 #define BB1__ENABLE_LOQ__MODIFY(dst, src) \ argument
62397 #define BB1__ENABLE_LOQ__VERIFY(src) \ argument
62411 #define BB1__FORCE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
62412 #define BB1__FORCE_LOQ__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
62413 #define BB1__FORCE_LOQ__MODIFY(dst, src) \ argument
62417 #define BB1__FORCE_LOQ__VERIFY(src) \ argument
62431 #define BB1__ENABLE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
62432 #define BB1__ENABLE_NOTCH__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
62433 #define BB1__ENABLE_NOTCH__MODIFY(dst, src) \ argument
62437 #define BB1__ENABLE_NOTCH__VERIFY(src) \ argument
62451 #define BB1__FORCE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
62452 #define BB1__FORCE_NOTCH__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
62453 #define BB1__FORCE_NOTCH__MODIFY(dst, src) \ argument
62457 #define BB1__FORCE_NOTCH__VERIFY(src) \ argument
62471 #define BB1__ENABLE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
62472 #define BB1__ENABLE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
62473 #define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \ argument
62477 #define BB1__ENABLE_BIQUAD__VERIFY(src) \ argument
62491 #define BB1__FORCE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
62492 #define BB1__FORCE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) argument
62493 #define BB1__FORCE_BIQUAD__MODIFY(dst, src) \ argument
62497 #define BB1__FORCE_BIQUAD__VERIFY(src) \ argument
62511 #define BB1__ENABLE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
62512 #define BB1__ENABLE_OSDAC__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) argument
62513 #define BB1__ENABLE_OSDAC__MODIFY(dst, src) \ argument
62517 #define BB1__ENABLE_OSDAC__VERIFY(src) \ argument
62531 #define BB1__FORCE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
62532 #define BB1__FORCE_OSDAC__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) argument
62533 #define BB1__FORCE_OSDAC__MODIFY(dst, src) \ argument
62537 #define BB1__FORCE_OSDAC__VERIFY(src) \ argument
62551 #define BB1__ENABLE_V2I__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
62552 #define BB1__ENABLE_V2I__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) argument
62553 #define BB1__ENABLE_V2I__MODIFY(dst, src) \ argument
62557 #define BB1__ENABLE_V2I__VERIFY(src) \ argument
62571 #define BB1__FORCE_V2I__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
62572 #define BB1__FORCE_V2I__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) argument
62573 #define BB1__FORCE_V2I__MODIFY(dst, src) \ argument
62577 #define BB1__FORCE_V2I__VERIFY(src) \ argument
62591 #define BB1__ENABLE_I2V__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
62592 #define BB1__ENABLE_I2V__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
62593 #define BB1__ENABLE_I2V__MODIFY(dst, src) \ argument
62597 #define BB1__ENABLE_I2V__VERIFY(src) \ argument
62611 #define BB1__FORCE_I2V__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) argument
62612 #define BB1__FORCE_I2V__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) argument
62613 #define BB1__FORCE_I2V__MODIFY(dst, src) \ argument
62617 #define BB1__FORCE_I2V__VERIFY(src) \ argument
62631 #define BB1__CMSEL__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) argument
62632 #define BB1__CMSEL__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) argument
62633 #define BB1__CMSEL__MODIFY(dst, src) \ argument
62637 #define BB1__CMSEL__VERIFY(src) (!((((u_int32_t)(src) << 13) & ~0x0000e000U))) argument
62643 #define BB1__ATBSEL__READ(src) (((u_int32_t)(src) & 0x00030000U) >> 16) argument
62644 #define BB1__ATBSEL__WRITE(src) (((u_int32_t)(src) << 16) & 0x00030000U) argument
62645 #define BB1__ATBSEL__MODIFY(dst, src) \ argument
62649 #define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U))) argument
62655 #define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \ argument
62658 #define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \ argument
62661 #define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \ argument
62665 #define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \ argument
62679 #define BB1__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x00f80000U) >> 19) argument
62680 #define BB1__OFSTCORRI2VQ__WRITE(src) (((u_int32_t)(src) << 19) & 0x00f80000U) argument
62681 #define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \ argument
62685 #define BB1__OFSTCORRI2VQ__VERIFY(src) \ argument
62693 #define BB1__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x1f000000U) >> 24) argument
62694 #define BB1__OFSTCORRI2VI__WRITE(src) (((u_int32_t)(src) << 24) & 0x1f000000U) argument
62695 #define BB1__OFSTCORRI2VI__MODIFY(dst, src) \ argument
62699 #define BB1__OFSTCORRI2VI__VERIFY(src) \ argument
62707 #define BB1__LOCALOFFSET__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
62708 #define BB1__LOCALOFFSET__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
62709 #define BB1__LOCALOFFSET__MODIFY(dst, src) \ argument
62713 #define BB1__LOCALOFFSET__VERIFY(src) \ argument
62727 #define BB1__RANGE_OSDAC__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) argument
62728 #define BB1__RANGE_OSDAC__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) argument
62729 #define BB1__RANGE_OSDAC__MODIFY(dst, src) \ argument
62733 #define BB1__RANGE_OSDAC__VERIFY(src) \ argument
62754 #define BB2__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU argument
62755 #define BB2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
62756 #define BB2__SPARE__MODIFY(dst, src) \ argument
62760 #define BB2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) argument
62766 #define BB2__MXR_HIGHGAINMASK__READ(src) \ argument
62769 #define BB2__MXR_HIGHGAINMASK__WRITE(src) \ argument
62772 #define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \ argument
62776 #define BB2__MXR_HIGHGAINMASK__VERIFY(src) \ argument
62784 #define BB2__SEL_TEST__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) argument
62785 #define BB2__SEL_TEST__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U) argument
62786 #define BB2__SEL_TEST__MODIFY(dst, src) \ argument
62790 #define BB2__SEL_TEST__VERIFY(src) \ argument
62798 #define BB2__RCFILTER_CAP__READ(src) (((u_int32_t)(src) & 0x00007c00U) >> 10) argument
62799 #define BB2__RCFILTER_CAP__WRITE(src) (((u_int32_t)(src) << 10) & 0x00007c00U) argument
62800 #define BB2__RCFILTER_CAP__MODIFY(dst, src) \ argument
62804 #define BB2__RCFILTER_CAP__VERIFY(src) \ argument
62812 #define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \ argument
62815 #define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \ argument
62818 #define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \ argument
62822 #define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \ argument
62836 #define BB2__FNOTCH__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16) argument
62837 #define BB2__FNOTCH__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U) argument
62838 #define BB2__FNOTCH__MODIFY(dst, src) \ argument
62842 #define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U))) argument
62848 #define BB2__OVERRIDE_FNOTCH__READ(src) \ argument
62851 #define BB2__OVERRIDE_FNOTCH__WRITE(src) \ argument
62854 #define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \ argument
62858 #define BB2__OVERRIDE_FNOTCH__VERIFY(src) \ argument
62872 #define BB2__FILTERFC__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) argument
62873 #define BB2__FILTERFC__WRITE(src) (((u_int32_t)(src) << 21) & 0x03e00000U) argument
62874 #define BB2__FILTERFC__MODIFY(dst, src) \ argument
62878 #define BB2__FILTERFC__VERIFY(src) \ argument
62886 #define BB2__OVERRIDE_FILTERFC__READ(src) \ argument
62889 #define BB2__OVERRIDE_FILTERFC__WRITE(src) \ argument
62892 #define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \ argument
62896 #define BB2__OVERRIDE_FILTERFC__VERIFY(src) \ argument
62910 #define BB2__I2V2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
62911 #define BB2__I2V2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) argument
62912 #define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \ argument
62916 #define BB2__I2V2RXOUT_EN__VERIFY(src) \ argument
62930 #define BB2__BQ2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
62931 #define BB2__BQ2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
62932 #define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \ argument
62936 #define BB2__BQ2RXOUT_EN__VERIFY(src) \ argument
62950 #define BB2__RXIN2I2V_EN__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
62951 #define BB2__RXIN2I2V_EN__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
62952 #define BB2__RXIN2I2V_EN__MODIFY(dst, src) \ argument
62956 #define BB2__RXIN2I2V_EN__VERIFY(src) \ argument
62970 #define BB2__RXIN2BQ_EN__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
62971 #define BB2__RXIN2BQ_EN__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
62972 #define BB2__RXIN2BQ_EN__MODIFY(dst, src) \ argument
62976 #define BB2__RXIN2BQ_EN__VERIFY(src) \ argument
62990 #define BB2__SWITCH_OVERRIDE__READ(src) \ argument
62993 #define BB2__SWITCH_OVERRIDE__WRITE(src) \ argument
62996 #define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \ argument
63000 #define BB2__SWITCH_OVERRIDE__VERIFY(src) \ argument
63027 #define BB3__SPARE__READ(src) (u_int32_t)(src) & 0x000000ffU argument
63028 #define BB3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU) argument
63029 #define BB3__SPARE__MODIFY(dst, src) \ argument
63033 #define BB3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU))) argument
63039 #define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8) argument
63040 #define BB3__SEL_OFST_READBK__WRITE(src) \ argument
63043 #define BB3__SEL_OFST_READBK__MODIFY(dst, src) \ argument
63047 #define BB3__SEL_OFST_READBK__VERIFY(src) \ argument
63055 #define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \ argument
63058 #define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \ argument
63061 #define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \ argument
63065 #define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \ argument
63079 #define BB3__RXONLY_FILTERFC__READ(src) \ argument
63082 #define BB3__RXONLY_FILTERFC__WRITE(src) \ argument
63085 #define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \ argument
63089 #define BB3__RXONLY_FILTERFC__VERIFY(src) \ argument
63097 #define BB3__FILTERFC__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16) argument
63103 #define BB3__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21) argument
63109 #define BB3__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x7c000000U) >> 26) argument
63115 #define BB3__EN_TXBBCONSTCUR__READ(src) \ argument
63118 #define BB3__EN_TXBBCONSTCUR__WRITE(src) \ argument
63121 #define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \ argument
63125 #define BB3__EN_TXBBCONSTCUR__VERIFY(src) \ argument
63152 #define DPLL__NFRAC__READ(src) (u_int32_t)(src) & 0x0003ffffU argument
63153 #define DPLL__NFRAC__WRITE(src) ((u_int32_t)(src) & 0x0003ffffU) argument
63154 #define DPLL__NFRAC__MODIFY(dst, src) \ argument
63158 #define DPLL__NFRAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x0003ffffU))) argument
63164 #define DPLL__NINT__READ(src) (((u_int32_t)(src) & 0x07fc0000U) >> 18) argument
63165 #define DPLL__NINT__WRITE(src) (((u_int32_t)(src) << 18) & 0x07fc0000U) argument
63166 #define DPLL__NINT__MODIFY(dst, src) \ argument
63170 #define DPLL__NINT__VERIFY(src) (!((((u_int32_t)(src) << 18) & ~0x07fc0000U))) argument
63176 #define DPLL__REFDIV__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27) argument
63177 #define DPLL__REFDIV__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U) argument
63178 #define DPLL__REFDIV__MODIFY(dst, src) \ argument
63182 #define DPLL__REFDIV__VERIFY(src) \ argument
63203 #define DPLL2__TESTINMSB__READ(src) (u_int32_t)(src) & 0x0000007fU argument
63204 #define DPLL2__TESTINMSB__WRITE(src) ((u_int32_t)(src) & 0x0000007fU) argument
63205 #define DPLL2__TESTINMSB__MODIFY(dst, src) \ argument
63209 #define DPLL2__TESTINMSB__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU))) argument
63215 #define DPLL2__DELTA__READ(src) (((u_int32_t)(src) & 0x00001f80U) >> 7) argument
63216 #define DPLL2__DELTA__WRITE(src) (((u_int32_t)(src) << 7) & 0x00001f80U) argument
63217 #define DPLL2__DELTA__MODIFY(dst, src) \ argument
63221 #define DPLL2__DELTA__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00001f80U))) argument
63227 #define DPLL2__OUTDIV__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13) argument
63228 #define DPLL2__OUTDIV__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U) argument
63229 #define DPLL2__OUTDIV__MODIFY(dst, src) \ argument
63233 #define DPLL2__OUTDIV__VERIFY(src) \ argument
63241 #define DPLL2__PLL_PWD__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16) argument
63242 #define DPLL2__PLL_PWD__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U) argument
63243 #define DPLL2__PLL_PWD__MODIFY(dst, src) \ argument
63247 #define DPLL2__PLL_PWD__VERIFY(src) \ argument
63261 #define DPLL2__SEL_1SDM__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17) argument
63262 #define DPLL2__SEL_1SDM__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U) argument
63263 #define DPLL2__SEL_1SDM__MODIFY(dst, src) \ argument
63267 #define DPLL2__SEL_1SDM__VERIFY(src) \ argument
63281 #define DPLL2__EN_NEGTRIG__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
63282 #define DPLL2__EN_NEGTRIG__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
63283 #define DPLL2__EN_NEGTRIG__MODIFY(dst, src) \ argument
63287 #define DPLL2__EN_NEGTRIG__VERIFY(src) \ argument
63301 #define DPLL2__KD__READ(src) (((u_int32_t)(src) & 0x03f80000U) >> 19) argument
63302 #define DPLL2__KD__WRITE(src) (((u_int32_t)(src) << 19) & 0x03f80000U) argument
63303 #define DPLL2__KD__MODIFY(dst, src) \ argument
63307 #define DPLL2__KD__VERIFY(src) (!((((u_int32_t)(src) << 19) & ~0x03f80000U))) argument
63313 #define DPLL2__KI__READ(src) (((u_int32_t)(src) & 0x3c000000U) >> 26) argument
63314 #define DPLL2__KI__WRITE(src) (((u_int32_t)(src) << 26) & 0x3c000000U) argument
63315 #define DPLL2__KI__MODIFY(dst, src) \ argument
63319 #define DPLL2__KI__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x3c000000U))) argument
63325 #define DPLL2__LOCAL_PLL__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
63326 #define DPLL2__LOCAL_PLL__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
63327 #define DPLL2__LOCAL_PLL__MODIFY(dst, src) \ argument
63331 #define DPLL2__LOCAL_PLL__VERIFY(src) \ argument
63345 #define DPLL2__RANGE__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
63346 #define DPLL2__RANGE__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
63347 #define DPLL2__RANGE__MODIFY(dst, src) \ argument
63351 #define DPLL2__RANGE__VERIFY(src) \ argument
63378 #define DPLL3__TESTINLSB__READ(src) (u_int32_t)(src) & 0x00000007U argument
63379 #define DPLL3__TESTINLSB__WRITE(src) ((u_int32_t)(src) & 0x00000007U) argument
63380 #define DPLL3__TESTINLSB__MODIFY(dst, src) \ argument
63384 #define DPLL3__TESTINLSB__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U))) argument
63390 #define DPLL3__SQSUM_DVC__READ(src) (((u_int32_t)(src) & 0x007ffff8U) >> 3) argument
63396 #define DPLL3__PHASE_SHIFT__READ(src) (((u_int32_t)(src) & 0x3f800000U) >> 23) argument
63397 #define DPLL3__PHASE_SHIFT__WRITE(src) (((u_int32_t)(src) << 23) & 0x3f800000U) argument
63398 #define DPLL3__PHASE_SHIFT__MODIFY(dst, src) \ argument
63402 #define DPLL3__PHASE_SHIFT__VERIFY(src) \ argument
63410 #define DPLL3__DO_MEAS__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
63411 #define DPLL3__DO_MEAS__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U) argument
63412 #define DPLL3__DO_MEAS__MODIFY(dst, src) \ argument
63416 #define DPLL3__DO_MEAS__VERIFY(src) \ argument
63430 #define DPLL3__MEAS_AT_TXON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
63431 #define DPLL3__MEAS_AT_TXON__WRITE(src) \ argument
63434 #define DPLL3__MEAS_AT_TXON__MODIFY(dst, src) \ argument
63438 #define DPLL3__MEAS_AT_TXON__VERIFY(src) \ argument
63465 #define DPLL4__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U argument
63466 #define DPLL4__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
63467 #define DPLL4__SPARE__MODIFY(dst, src) \ argument
63471 #define DPLL4__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
63479 #define DPLL4__SEL_COUNT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
63480 #define DPLL4__SEL_COUNT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
63481 #define DPLL4__SEL_COUNT__MODIFY(dst, src) \ argument
63485 #define DPLL4__SEL_COUNT__VERIFY(src) \ argument
63499 #define DPLL4__RESET_TEST__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
63500 #define DPLL4__RESET_TEST__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
63501 #define DPLL4__RESET_TEST__MODIFY(dst, src) \ argument
63505 #define DPLL4__RESET_TEST__VERIFY(src) \ argument
63519 #define DPLL4__MEAS_DONE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
63531 #define DPLL4__VC_MEAS0__READ(src) (((u_int32_t)(src) & 0x001ffff0U) >> 4) argument
63537 #define DPLL4__MEAN_DVC__READ(src) (((u_int32_t)(src) & 0xffe00000U) >> 21) argument
63592 #define TOP__SEL_TEMPSENSOR__READ(src) (u_int32_t)(src) & 0x00000001U argument
63593 #define TOP__SEL_TEMPSENSOR__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
63594 #define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \ argument
63598 #define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U))) argument
63610 #define TOP__SPARE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
63611 #define TOP__SPARE__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
63612 #define TOP__SPARE__MODIFY(dst, src) \ argument
63616 #define TOP__SPARE__VERIFY(src) (!((((u_int32_t)(src) << 1) & ~0x00000002U))) argument
63628 #define TOP__CLK107_EN__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
63629 #define TOP__CLK107_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
63630 #define TOP__CLK107_EN__MODIFY(dst, src) \ argument
63634 #define TOP__CLK107_EN__VERIFY(src) \ argument
63648 #define TOP__PWDV2I__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
63649 #define TOP__PWDV2I__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
63650 #define TOP__PWDV2I__MODIFY(dst, src) \ argument
63654 #define TOP__PWDV2I__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000008U))) argument
63666 #define TOP__PWDBIAS__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
63667 #define TOP__PWDBIAS__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
63668 #define TOP__PWDBIAS__MODIFY(dst, src) \ argument
63672 #define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000010U))) argument
63684 #define TOP__XPABIAS_BYPASS__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
63685 #define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
63686 #define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \ argument
63690 #define TOP__XPABIAS_BYPASS__VERIFY(src) \ argument
63704 #define TOP__XPABIASLVL__READ(src) (((u_int32_t)(src) & 0x000003c0U) >> 6) argument
63705 #define TOP__XPABIASLVL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000003c0U) argument
63706 #define TOP__XPABIASLVL__MODIFY(dst, src) \ argument
63710 #define TOP__XPABIASLVL__VERIFY(src) \ argument
63718 #define TOP__XPAREGULATOR_EN__READ(src) \ argument
63721 #define TOP__XPAREGULATOR_EN__WRITE(src) \ argument
63724 #define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \ argument
63728 #define TOP__XPAREGULATOR_EN__VERIFY(src) \ argument
63742 #define TOP__XPASHORT2GND__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
63743 #define TOP__XPASHORT2GND__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
63744 #define TOP__XPASHORT2GND__MODIFY(dst, src) \ argument
63748 #define TOP__XPASHORT2GND__VERIFY(src) \ argument
63762 #define TOP__XPA5ON__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12) argument
63763 #define TOP__XPA5ON__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U) argument
63764 #define TOP__XPA5ON__MODIFY(dst, src) \ argument
63768 #define TOP__XPA5ON__VERIFY(src) (!((((u_int32_t)(src) << 12) & ~0x00007000U))) argument
63774 #define TOP__XPA2ON__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) argument
63775 #define TOP__XPA2ON__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) argument
63776 #define TOP__XPA2ON__MODIFY(dst, src) \ argument
63780 #define TOP__XPA2ON__VERIFY(src) (!((((u_int32_t)(src) << 15) & ~0x00038000U))) argument
63786 #define TOP__LOCAL_XPAON__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18) argument
63787 #define TOP__LOCAL_XPAON__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U) argument
63788 #define TOP__LOCAL_XPAON__MODIFY(dst, src) \ argument
63792 #define TOP__LOCAL_XPAON__VERIFY(src) \ argument
63806 #define TOP__PAD2GND__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19) argument
63807 #define TOP__PAD2GND__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U) argument
63808 #define TOP__PAD2GND__MODIFY(dst, src) \ argument
63812 #define TOP__PAD2GND__VERIFY(src) \ argument
63826 #define TOP__INTH2PAD__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20) argument
63827 #define TOP__INTH2PAD__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U) argument
63828 #define TOP__INTH2PAD__MODIFY(dst, src) \ argument
63832 #define TOP__INTH2PAD__VERIFY(src) \ argument
63846 #define TOP__INTH2GND__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21) argument
63847 #define TOP__INTH2GND__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U) argument
63848 #define TOP__INTH2GND__MODIFY(dst, src) \ argument
63852 #define TOP__INTH2GND__VERIFY(src) \ argument
63866 #define TOP__INT2PAD__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22) argument
63867 #define TOP__INT2PAD__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U) argument
63868 #define TOP__INT2PAD__MODIFY(dst, src) \ argument
63872 #define TOP__INT2PAD__VERIFY(src) \ argument
63886 #define TOP__INT2GND__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23) argument
63887 #define TOP__INT2GND__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U) argument
63888 #define TOP__INT2GND__MODIFY(dst, src) \ argument
63892 #define TOP__INT2GND__VERIFY(src) \ argument
63906 #define TOP__ENBTCLK__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24) argument
63907 #define TOP__ENBTCLK__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U) argument
63908 #define TOP__ENBTCLK__MODIFY(dst, src) \ argument
63912 #define TOP__ENBTCLK__VERIFY(src) \ argument
63926 #define TOP__PWDPALCLK__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25) argument
63927 #define TOP__PWDPALCLK__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U) argument
63928 #define TOP__PWDPALCLK__MODIFY(dst, src) \ argument
63932 #define TOP__PWDPALCLK__VERIFY(src) \ argument
63946 #define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26) argument
63947 #define TOP__INV_CLK320_ADC__WRITE(src) \ argument
63950 #define TOP__INV_CLK320_ADC__MODIFY(dst, src) \ argument
63954 #define TOP__INV_CLK320_ADC__VERIFY(src) \ argument
63968 #define TOP__FLIP_REFCLK40__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27) argument
63969 #define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U) argument
63970 #define TOP__FLIP_REFCLK40__MODIFY(dst, src) \ argument
63974 #define TOP__FLIP_REFCLK40__VERIFY(src) \ argument
63988 #define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
63989 #define TOP__FLIP_PLLCLK320__WRITE(src) \ argument
63992 #define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \ argument
63996 #define TOP__FLIP_PLLCLK320__VERIFY(src) \ argument
64010 #define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
64011 #define TOP__FLIP_PLLCLK160__WRITE(src) \ argument
64014 #define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \ argument
64018 #define TOP__FLIP_PLLCLK160__VERIFY(src) \ argument
64032 #define TOP__CLK_SEL__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30) argument
64033 #define TOP__CLK_SEL__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U) argument
64034 #define TOP__CLK_SEL__MODIFY(dst, src) \ argument
64038 #define TOP__CLK_SEL__VERIFY(src) \ argument
64059 #define TOP2__RST_WARM_INT_L__READ(src) (u_int32_t)(src) & 0x00000001U argument
64060 #define TOP2__RST_WARM_INT_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U) argument
64061 #define TOP2__RST_WARM_INT_L__MODIFY(dst, src) \ argument
64065 #define TOP2__RST_WARM_INT_L__VERIFY(src) \ argument
64079 #define TOP2__RST_WARM_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1) argument
64080 #define TOP2__RST_WARM_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U) argument
64081 #define TOP2__RST_WARM_OVR__MODIFY(dst, src) \ argument
64085 #define TOP2__RST_WARM_OVR__VERIFY(src) \ argument
64099 #define TOP2__GLOBAL_CLK_EN__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2) argument
64100 #define TOP2__GLOBAL_CLK_EN__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U) argument
64101 #define TOP2__GLOBAL_CLK_EN__MODIFY(dst, src) \ argument
64105 #define TOP2__GLOBAL_CLK_EN__VERIFY(src) \ argument
64119 #define TOP2__LOCAL_CLKMODA__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3) argument
64120 #define TOP2__LOCAL_CLKMODA__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U) argument
64121 #define TOP2__LOCAL_CLKMODA__MODIFY(dst, src) \ argument
64125 #define TOP2__LOCAL_CLKMODA__VERIFY(src) \ argument
64139 #define TOP2__PLLBYPASS__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4) argument
64140 #define TOP2__PLLBYPASS__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U) argument
64141 #define TOP2__PLLBYPASS__MODIFY(dst, src) \ argument
64145 #define TOP2__PLLBYPASS__VERIFY(src) \ argument
64159 #define TOP2__LOCAL_PLLBYPASS__READ(src) \ argument
64162 #define TOP2__LOCAL_PLLBYPASS__WRITE(src) \ argument
64165 #define TOP2__LOCAL_PLLBYPASS__MODIFY(dst, src) \ argument
64169 #define TOP2__LOCAL_PLLBYPASS__VERIFY(src) \ argument
64183 #define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) \ argument
64186 #define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) \ argument
64189 #define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \ argument
64193 #define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \ argument
64201 #define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9) argument
64202 #define TOP2__TESTTXIQ_RCTRL__WRITE(src) \ argument
64205 #define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \ argument
64209 #define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \ argument
64217 #define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \ argument
64220 #define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \ argument
64223 #define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \ argument
64227 #define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \ argument
64235 #define TOP2__TESTTXIQ_PWD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15) argument
64236 #define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U) argument
64237 #define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \ argument
64241 #define TOP2__TESTTXIQ_PWD__VERIFY(src) \ argument
64249 #define TOP2__DACPWD__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18) argument
64250 #define TOP2__DACPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U) argument
64251 #define TOP2__DACPWD__MODIFY(dst, src) \ argument
64255 #define TOP2__DACPWD__VERIFY(src) \ argument
64263 #define TOP2__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21) argument
64264 #define TOP2__ADCPWD__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U) argument
64265 #define TOP2__ADCPWD__MODIFY(dst, src) \ argument
64269 #define TOP2__ADCPWD__VERIFY(src) \ argument
64277 #define TOP2__LOCAL_ADDACPWD__READ(src) \ argument
64280 #define TOP2__LOCAL_ADDACPWD__WRITE(src) \ argument
64283 #define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \ argument
64287 #define TOP2__LOCAL_ADDACPWD__VERIFY(src) \ argument
64301 #define TOP2__ADC_CLK_SEL__READ(src) (((u_int32_t)(src) & 0x1e000000U) >> 25) argument
64302 #define TOP2__ADC_CLK_SEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x1e000000U) argument
64303 #define TOP2__ADC_CLK_SEL__MODIFY(dst, src) \ argument
64307 #define TOP2__ADC_CLK_SEL__VERIFY(src) \ argument
64315 #define TOP2__DAC_CLK_SEL__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29) argument
64316 #define TOP2__DAC_CLK_SEL__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U) argument
64317 #define TOP2__DAC_CLK_SEL__MODIFY(dst, src) \ argument
64321 #define TOP2__DAC_CLK_SEL__VERIFY(src) \ argument
64342 #define TOP3__SPARE__READ(src) (u_int32_t)(src) & 0x0000ffffU argument
64343 #define TOP3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU) argument
64344 #define TOP3__SPARE__MODIFY(dst, src) \ argument
64348 #define TOP3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU))) argument
64354 #define TOP3__RBIAS_OUT__READ(src) (((u_int32_t)(src) & 0x003f0000U) >> 16) argument
64360 #define TOP3__RBIAS__READ(src) (((u_int32_t)(src) & 0x0fc00000U) >> 22) argument
64361 #define TOP3__RBIAS__WRITE(src) (((u_int32_t)(src) << 22) & 0x0fc00000U) argument
64362 #define TOP3__RBIAS__MODIFY(dst, src) \ argument
64366 #define TOP3__RBIAS__VERIFY(src) (!((((u_int32_t)(src) << 22) & ~0x0fc00000U))) argument
64372 #define TOP3__LOCALRBIAS__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
64373 #define TOP3__LOCALRBIAS__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
64374 #define TOP3__LOCALRBIAS__MODIFY(dst, src) \ argument
64378 #define TOP3__LOCALRBIAS__VERIFY(src) \ argument
64392 #define TOP3__BBPLL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
64393 #define TOP3__BBPLL_ATBVREG__WRITE(src) \ argument
64396 #define TOP3__BBPLL_ATBVREG__MODIFY(dst, src) \ argument
64400 #define TOP3__BBPLL_ATBVREG__VERIFY(src) \ argument
64414 #define TOP3__BBPLL_SELVREG__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30) argument
64415 #define TOP3__BBPLL_SELVREG__WRITE(src) \ argument
64418 #define TOP3__BBPLL_SELVREG__MODIFY(dst, src) \ argument
64422 #define TOP3__BBPLL_SELVREG__VERIFY(src) \ argument
64436 #define TOP3__BBPLL_PWDVREG__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
64437 #define TOP3__BBPLL_PWDVREG__WRITE(src) \ argument
64440 #define TOP3__BBPLL_PWDVREG__MODIFY(dst, src) \ argument
64444 #define TOP3__BBPLL_PWDVREG__VERIFY(src) \ argument
64471 #define THERM__SPARE__READ(src) (u_int32_t)(src) & 0x0000003fU argument
64472 #define THERM__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU) argument
64473 #define THERM__SPARE__MODIFY(dst, src) \ argument
64477 #define THERM__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000003fU))) argument
64483 #define THERM__RST_WARM_L_THERM__READ(src) \ argument
64486 #define THERM__RST_WARM_L_THERM__WRITE(src) \ argument
64489 #define THERM__RST_WARM_L_THERM__MODIFY(dst, src) \ argument
64493 #define THERM__RST_WARM_L_THERM__VERIFY(src) \ argument
64507 #define THERM__SAR_ADC_DONE__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
64519 #define THERM__SAR_ADC_OUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8) argument
64525 #define THERM__SAR_DACTEST_CODE__READ(src) \ argument
64528 #define THERM__SAR_DACTEST_CODE__WRITE(src) \ argument
64531 #define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \ argument
64535 #define THERM__SAR_DACTEST_CODE__VERIFY(src) \ argument
64543 #define THERM__SAR_DACTEST_EN__READ(src) \ argument
64546 #define THERM__SAR_DACTEST_EN__WRITE(src) \ argument
64549 #define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \ argument
64553 #define THERM__SAR_DACTEST_EN__VERIFY(src) \ argument
64567 #define THERM__SAR_ADCCAL_EN__READ(src) \ argument
64570 #define THERM__SAR_ADCCAL_EN__WRITE(src) \ argument
64573 #define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \ argument
64577 #define THERM__SAR_ADCCAL_EN__VERIFY(src) \ argument
64591 #define THERM__THERMSEL__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26) argument
64592 #define THERM__THERMSEL__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U) argument
64593 #define THERM__THERMSEL__MODIFY(dst, src) \ argument
64597 #define THERM__THERMSEL__VERIFY(src) \ argument
64605 #define THERM__SAR_SLOW_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28) argument
64606 #define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U) argument
64607 #define THERM__SAR_SLOW_EN__MODIFY(dst, src) \ argument
64611 #define THERM__SAR_SLOW_EN__VERIFY(src) \ argument
64625 #define THERM__THERMSTART__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29) argument
64626 #define THERM__THERMSTART__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U) argument
64627 #define THERM__THERMSTART__MODIFY(dst, src) \ argument
64631 #define THERM__THERMSTART__VERIFY(src) \ argument
64645 #define THERM__SAR_AUTOPWD_EN__READ(src) \ argument
64648 #define THERM__SAR_AUTOPWD_EN__WRITE(src) \ argument
64651 #define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \ argument
64655 #define THERM__SAR_AUTOPWD_EN__VERIFY(src) \ argument
64669 #define THERM__LOCAL_THERM__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
64670 #define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U) argument
64671 #define THERM__LOCAL_THERM__MODIFY(dst, src) \ argument
64675 #define THERM__LOCAL_THERM__VERIFY(src) \ argument
64702 #define XTAL__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU argument
64703 #define XTAL__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU) argument
64704 #define XTAL__SPARE__MODIFY(dst, src) \ argument
64708 #define XTAL__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU))) argument
64714 #define XTAL__SWREGCLK_EDGE_SEL__READ(src) \ argument
64717 #define XTAL__SWREGCLK_EDGE_SEL__WRITE(src) \ argument
64720 #define XTAL__SWREGCLK_EDGE_SEL__MODIFY(dst, src) \ argument
64724 #define XTAL__SWREGCLK_EDGE_SEL__VERIFY(src) \ argument
64738 #define XTAL__PWD_SWREGCLK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5) argument
64739 #define XTAL__PWD_SWREGCLK__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U) argument
64740 #define XTAL__PWD_SWREGCLK__MODIFY(dst, src) \ argument
64744 #define XTAL__PWD_SWREGCLK__VERIFY(src) \ argument
64758 #define XTAL__LOCAL_XTAL__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6) argument
64759 #define XTAL__LOCAL_XTAL__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U) argument
64760 #define XTAL__LOCAL_XTAL__MODIFY(dst, src) \ argument
64764 #define XTAL__LOCAL_XTAL__VERIFY(src) \ argument
64778 #define XTAL__XTAL_PWDCLKIN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7) argument
64779 #define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U) argument
64780 #define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \ argument
64784 #define XTAL__XTAL_PWDCLKIN__VERIFY(src) \ argument
64798 #define XTAL__XTAL_OSCON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8) argument
64799 #define XTAL__XTAL_OSCON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U) argument
64800 #define XTAL__XTAL_OSCON__MODIFY(dst, src) \ argument
64804 #define XTAL__XTAL_OSCON__VERIFY(src) \ argument
64818 #define XTAL__XTAL_ATBVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9) argument
64819 #define XTAL__XTAL_ATBVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U) argument
64820 #define XTAL__XTAL_ATBVREG__MODIFY(dst, src) \ argument
64824 #define XTAL__XTAL_ATBVREG__VERIFY(src) \ argument
64838 #define XTAL__XTAL_LBIAS2X__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10) argument
64839 #define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U) argument
64840 #define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \ argument
64844 #define XTAL__XTAL_LBIAS2X__VERIFY(src) \ argument
64858 #define XTAL__XTAL_BIAS2X__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11) argument
64859 #define XTAL__XTAL_BIAS2X__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U) argument
64860 #define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \ argument
64864 #define XTAL__XTAL_BIAS2X__VERIFY(src) \ argument
64878 #define XTAL__XTAL_PWDCLKD__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12) argument
64879 #define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U) argument
64880 #define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \ argument
64884 #define XTAL__XTAL_PWDCLKD__VERIFY(src) \ argument
64898 #define XTAL__XTAL_LOCALBIAS__READ(src) \ argument
64901 #define XTAL__XTAL_LOCALBIAS__WRITE(src) \ argument
64904 #define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \ argument
64908 #define XTAL__XTAL_LOCALBIAS__VERIFY(src) \ argument
64922 #define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14) argument
64923 #define XTAL__XTAL_SHORTXIN__WRITE(src) \ argument
64926 #define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \ argument
64930 #define XTAL__XTAL_SHORTXIN__VERIFY(src) \ argument
64944 #define XTAL__XTAL_DRVSTR__READ(src) (((u_int32_t)(src) & 0x00018000U) >> 15) argument
64945 #define XTAL__XTAL_DRVSTR__WRITE(src) (((u_int32_t)(src) << 15) & 0x00018000U) argument
64946 #define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \ argument
64950 #define XTAL__XTAL_DRVSTR__VERIFY(src) \ argument
64958 #define XTAL__XTAL_CAPOUTDAC__READ(src) \ argument
64961 #define XTAL__XTAL_CAPOUTDAC__WRITE(src) \ argument
64964 #define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \ argument
64968 #define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \ argument
64976 #define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24) argument
64977 #define XTAL__XTAL_CAPINDAC__WRITE(src) \ argument
64980 #define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \ argument
64984 #define XTAL__XTAL_CAPINDAC__VERIFY(src) \ argument
64992 #define XTAL__TCXODET__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31) argument
65017 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \ argument
65020 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \ argument
65023 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \ argument
65027 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \ argument
65041 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \ argument
65044 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \ argument
65047 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \ argument
65051 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \ argument
65065 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \ argument
65068 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \ argument
65071 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \ argument
65075 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \ argument
65089 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \ argument
65092 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \ argument
65095 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \ argument
65099 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \ argument
65113 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \ argument
65116 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \ argument
65119 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \ argument
65123 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \ argument
65137 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \ argument
65140 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \ argument
65143 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \ argument
65147 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \ argument
65161 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \ argument
65164 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \ argument
65167 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \ argument
65171 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \ argument
65185 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \ argument
65188 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \ argument
65191 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \ argument
65195 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \ argument
65209 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \ argument
65212 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \ argument
65215 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \ argument
65219 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \ argument
65233 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \ argument
65236 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \ argument
65239 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \ argument
65243 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \ argument
65257 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \ argument
65260 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \ argument
65263 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \ argument
65267 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \ argument
65281 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \ argument
65284 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \ argument
65287 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \ argument
65291 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \ argument
65305 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \ argument
65308 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \ argument
65311 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \ argument
65315 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \ argument
65329 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \ argument
65332 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \ argument
65335 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \ argument
65339 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \ argument
65353 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \ argument
65356 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \ argument
65359 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \ argument
65363 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \ argument
65377 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \ argument
65380 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \ argument
65383 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \ argument
65387 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \ argument
65401 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \ argument
65404 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \ argument
65407 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \ argument
65411 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \ argument
65438 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \ argument
65441 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \ argument
65444 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \ argument
65448 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \ argument
65456 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \ argument
65459 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \ argument
65462 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \ argument
65466 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \ argument
65487 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \ argument
65490 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \ argument
65493 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \ argument
65497 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \ argument
65505 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \ argument
65508 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \ argument
65511 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \ argument
65515 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \ argument
65523 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \ argument
65526 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \ argument
65529 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \ argument
65533 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \ argument
65541 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \ argument
65544 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \ argument
65547 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \ argument
65551 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \ argument
65578 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \ argument
65581 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \ argument
65584 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \ argument
65588 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \ argument
65596 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \ argument
65599 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \ argument
65602 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \ argument
65606 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \ argument
65614 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \ argument
65617 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \ argument
65620 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \ argument
65624 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \ argument
65648 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \ argument
65651 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \ argument
65654 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \ argument
65658 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \ argument
65666 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \ argument
65669 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \ argument
65672 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \ argument
65676 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \ argument
65697 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \ argument
65700 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \ argument
65703 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \ argument
65707 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \ argument
65731 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \ argument
65734 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \ argument
65737 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \ argument
65741 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \ argument
65749 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \ argument
65752 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \ argument
65755 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \ argument
65759 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \ argument
65780 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \ argument
65783 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \ argument
65786 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \ argument
65790 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \ argument
65811 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \ argument
65814 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \ argument
65817 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \ argument
65821 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \ argument
65829 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \ argument
65832 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \ argument
65835 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \ argument
65839 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \ argument
65860 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \ argument
65863 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \ argument
65866 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \ argument
65870 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \ argument
65891 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \ argument
65894 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \ argument
65897 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \ argument
65901 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \ argument
65922 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \ argument
65925 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \ argument
65928 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \ argument
65932 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \ argument
65953 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \ argument
65956 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \ argument
65959 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \ argument
65963 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \ argument
65971 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \ argument
65974 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \ argument
65977 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \ argument
65981 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \ argument
66002 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \ argument
66005 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \ argument
66008 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \ argument
66012 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \ argument
66020 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \ argument
66023 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \ argument
66026 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \ argument
66030 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \ argument
66044 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \ argument
66047 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \ argument
66050 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \ argument
66054 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \ argument
66062 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \ argument
66065 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \ argument
66068 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \ argument
66072 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \ argument
66093 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \ argument
66096 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \ argument
66099 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \ argument
66103 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \ argument
66111 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \ argument
66114 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \ argument
66117 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \ argument
66121 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \ argument
66129 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \ argument
66132 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \ argument
66135 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \ argument
66139 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \ argument
66147 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \ argument
66150 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \ argument
66153 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \ argument
66157 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \ argument
66178 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \ argument
66181 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \ argument
66184 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \ argument
66188 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \ argument
66196 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \ argument
66199 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \ argument
66202 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \ argument
66206 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \ argument
66227 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \ argument
66230 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \ argument
66233 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \ argument
66237 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \ argument