Lines Matching refs:dev
13 mt76x2_adjust_high_lna_gain(struct mt76x02_dev *dev, int reg, s8 offset) in mt76x2_adjust_high_lna_gain() argument
18 mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_high_lna_gain()
20 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_LNA_HIGH_GAIN, gain); in mt76x2_adjust_high_lna_gain()
24 mt76x2_adjust_agc_gain(struct mt76x02_dev *dev, int reg, s8 offset) in mt76x2_adjust_agc_gain() argument
28 gain = FIELD_GET(MT_BBP_AGC_GAIN, mt76_rr(dev, MT_BBP(AGC, reg))); in mt76x2_adjust_agc_gain()
30 mt76_rmw_field(dev, MT_BBP(AGC, reg), MT_BBP_AGC_GAIN, gain); in mt76x2_adjust_agc_gain()
33 void mt76x2_apply_gain_adj(struct mt76x02_dev *dev) in mt76x2_apply_gain_adj() argument
35 s8 *gain_adj = dev->cal.rx.high_gain; in mt76x2_apply_gain_adj()
37 mt76x2_adjust_high_lna_gain(dev, 4, gain_adj[0]); in mt76x2_apply_gain_adj()
38 mt76x2_adjust_high_lna_gain(dev, 5, gain_adj[1]); in mt76x2_apply_gain_adj()
40 mt76x2_adjust_agc_gain(dev, 8, gain_adj[0]); in mt76x2_apply_gain_adj()
41 mt76x2_adjust_agc_gain(dev, 9, gain_adj[1]); in mt76x2_apply_gain_adj()
45 void mt76x2_phy_set_txpower_regs(struct mt76x02_dev *dev, in mt76x2_phy_set_txpower_regs() argument
55 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x35160a00); in mt76x2_phy_set_txpower_regs()
56 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x35160a06); in mt76x2_phy_set_txpower_regs()
58 if (mt76x02_ext_pa_enabled(dev, band)) { in mt76x2_phy_set_txpower_regs()
59 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0x0000ec00); in mt76x2_phy_set_txpower_regs()
60 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0x0000ec00); in mt76x2_phy_set_txpower_regs()
62 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, 0xf4000200); in mt76x2_phy_set_txpower_regs()
63 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, 0xfa000200); in mt76x2_phy_set_txpower_regs()
69 if (mt76x02_ext_pa_enabled(dev, band)) { in mt76x2_phy_set_txpower_regs()
70 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x2f0f0400); in mt76x2_phy_set_txpower_regs()
71 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x2f0f0476); in mt76x2_phy_set_txpower_regs()
73 mt76_wr(dev, MT_TX_ALC_CFG_2, 0x1b0f0400); in mt76x2_phy_set_txpower_regs()
74 mt76_wr(dev, MT_TX_ALC_CFG_3, 0x1b0f0476); in mt76x2_phy_set_txpower_regs()
77 if (mt76x02_ext_pa_enabled(dev, band)) in mt76x2_phy_set_txpower_regs()
82 mt76_wr(dev, MT_RF_PA_MODE_ADJ0, pa_mode_adj); in mt76x2_phy_set_txpower_regs()
83 mt76_wr(dev, MT_RF_PA_MODE_ADJ1, pa_mode_adj); in mt76x2_phy_set_txpower_regs()
86 mt76_wr(dev, MT_BB_PA_MODE_CFG0, pa_mode[0]); in mt76x2_phy_set_txpower_regs()
87 mt76_wr(dev, MT_BB_PA_MODE_CFG1, pa_mode[1]); in mt76x2_phy_set_txpower_regs()
88 mt76_wr(dev, MT_RF_PA_MODE_CFG0, pa_mode[0]); in mt76x2_phy_set_txpower_regs()
89 mt76_wr(dev, MT_RF_PA_MODE_CFG1, pa_mode[1]); in mt76x2_phy_set_txpower_regs()
91 if (mt76x02_ext_pa_enabled(dev, band)) { in mt76x2_phy_set_txpower_regs()
99 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); in mt76x2_phy_set_txpower_regs()
100 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); in mt76x2_phy_set_txpower_regs()
101 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00001818); in mt76x2_phy_set_txpower_regs()
106 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, val); in mt76x2_phy_set_txpower_regs()
107 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, val); in mt76x2_phy_set_txpower_regs()
108 mt76_wr(dev, MT_TX_ALC_CFG_4, 0x00000606); in mt76x2_phy_set_txpower_regs()
110 mt76_wr(dev, MT_TX0_RF_GAIN_CORR, 0x383c023c); in mt76x2_phy_set_txpower_regs()
111 mt76_wr(dev, MT_TX1_RF_GAIN_CORR, 0x24282e28); in mt76x2_phy_set_txpower_regs()
112 mt76_wr(dev, MT_TX_ALC_CFG_4, 0); in mt76x2_phy_set_txpower_regs()
137 void mt76x2_phy_set_txpower(struct mt76x02_dev *dev) in mt76x2_phy_set_txpower() argument
139 enum nl80211_chan_width width = dev->mphy.chandef.width; in mt76x2_phy_set_txpower()
140 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x2_phy_set_txpower()
146 mt76x2_get_power_info(dev, &txp, chan); in mt76x2_phy_set_txpower()
153 mt76x2_get_rate_power(dev, &t, chan); in mt76x2_phy_set_txpower()
155 mt76x02_limit_rate_power(&t, dev->txpower_conf); in mt76x2_phy_set_txpower()
156 dev->mphy.txpower_cur = mt76x02_get_max_rate_power(&t); in mt76x2_phy_set_txpower()
175 dev->target_power = txp.target_power; in mt76x2_phy_set_txpower()
176 dev->target_power_delta[0] = txp_0 - txp.chain[0].target_power; in mt76x2_phy_set_txpower()
177 dev->target_power_delta[1] = txp_1 - txp.chain[0].target_power; in mt76x2_phy_set_txpower()
178 dev->rate_power = t; in mt76x2_phy_set_txpower()
180 mt76x02_phy_set_txpower(dev, txp_0, txp_1); in mt76x2_phy_set_txpower()
184 void mt76x2_configure_tx_delay(struct mt76x02_dev *dev, in mt76x2_configure_tx_delay() argument
189 if (mt76x02_ext_pa_enabled(dev, band)) { in mt76x2_configure_tx_delay()
196 mt76_wr(dev, MT_TX_SW_CFG0, cfg0); in mt76x2_configure_tx_delay()
197 mt76_wr(dev, MT_TX_SW_CFG1, cfg1); in mt76x2_configure_tx_delay()
199 mt76_rmw_field(dev, MT_XIFS_TIME_CFG, MT_XIFS_TIME_CFG_OFDM_SIFS, 15); in mt76x2_configure_tx_delay()
203 void mt76x2_phy_tssi_compensate(struct mt76x02_dev *dev) in mt76x2_phy_tssi_compensate() argument
205 struct ieee80211_channel *chan = dev->mphy.chandef.chan; in mt76x2_phy_tssi_compensate()
209 if (!dev->cal.tssi_cal_done) in mt76x2_phy_tssi_compensate()
212 if (!dev->cal.tssi_comp_pending) { in mt76x2_phy_tssi_compensate()
215 mt76x2_mcu_tssi_comp(dev, &t); in mt76x2_phy_tssi_compensate()
216 dev->cal.tssi_comp_pending = true; in mt76x2_phy_tssi_compensate()
218 if (mt76_rr(dev, MT_BBP(CORE, 34)) & BIT(4)) in mt76x2_phy_tssi_compensate()
221 dev->cal.tssi_comp_pending = false; in mt76x2_phy_tssi_compensate()
222 mt76x2_get_power_info(dev, &txp, chan); in mt76x2_phy_tssi_compensate()
224 if (mt76x02_ext_pa_enabled(dev, chan->band)) in mt76x2_phy_tssi_compensate()
232 mt76x2_mcu_tssi_comp(dev, &t); in mt76x2_phy_tssi_compensate()
234 if (t.pa_mode || dev->cal.dpd_cal_done || dev->ed_tx_blocked) in mt76x2_phy_tssi_compensate()
238 mt76x02_mcu_calibrate(dev, MCU_CAL_DPD, chan->hw_value); in mt76x2_phy_tssi_compensate()
239 dev->cal.dpd_cal_done = true; in mt76x2_phy_tssi_compensate()
245 mt76x2_phy_set_gain_val(struct mt76x02_dev *dev) in mt76x2_phy_set_gain_val() argument
250 gain_val[0] = dev->cal.agc_gain_cur[0] - dev->cal.agc_gain_adjust; in mt76x2_phy_set_gain_val()
251 gain_val[1] = dev->cal.agc_gain_cur[1] - dev->cal.agc_gain_adjust; in mt76x2_phy_set_gain_val()
254 if (!mt76x2_has_ext_lna(dev) && in mt76x2_phy_set_gain_val()
255 dev->mphy.chandef.width >= NL80211_CHAN_WIDTH_40) in mt76x2_phy_set_gain_val()
258 if (mt76x2_has_ext_lna(dev) && in mt76x2_phy_set_gain_val()
259 dev->mphy.chandef.chan->band == NL80211_BAND_2GHZ && in mt76x2_phy_set_gain_val()
260 dev->mphy.chandef.width < NL80211_CHAN_WIDTH_40) in mt76x2_phy_set_gain_val()
265 mt76_wr(dev, MT_BBP(AGC, 8), in mt76x2_phy_set_gain_val()
267 mt76_wr(dev, MT_BBP(AGC, 9), in mt76x2_phy_set_gain_val()
270 if (dev->mphy.chandef.chan->flags & IEEE80211_CHAN_RADAR) in mt76x2_phy_set_gain_val()
271 mt76x02_phy_dfs_adjust_agc(dev); in mt76x2_phy_set_gain_val()
274 void mt76x2_phy_update_channel_gain(struct mt76x02_dev *dev) in mt76x2_phy_update_channel_gain() argument
276 u8 *gain = dev->cal.agc_gain_init; in mt76x2_phy_update_channel_gain()
283 dev->cal.avg_rssi_all = mt76_get_min_avg_rssi(&dev->mt76, false); in mt76x2_phy_update_channel_gain()
284 if (!dev->cal.avg_rssi_all) in mt76x2_phy_update_channel_gain()
285 dev->cal.avg_rssi_all = -75; in mt76x2_phy_update_channel_gain()
287 low_gain = (dev->cal.avg_rssi_all > mt76x02_get_rssi_gain_thresh(dev)) + in mt76x2_phy_update_channel_gain()
288 (dev->cal.avg_rssi_all > mt76x02_get_low_rssi_gain_thresh(dev)); in mt76x2_phy_update_channel_gain()
290 gain_change = dev->cal.low_gain < 0 || in mt76x2_phy_update_channel_gain()
291 (dev->cal.low_gain & 2) ^ (low_gain & 2); in mt76x2_phy_update_channel_gain()
292 dev->cal.low_gain = low_gain; in mt76x2_phy_update_channel_gain()
295 if (mt76x02_phy_adjust_vga_gain(dev)) in mt76x2_phy_update_channel_gain()
296 mt76x2_phy_set_gain_val(dev); in mt76x2_phy_update_channel_gain()
300 if (dev->mphy.chandef.width == NL80211_CHAN_WIDTH_80) { in mt76x2_phy_update_channel_gain()
301 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560211); in mt76x2_phy_update_channel_gain()
302 val = mt76_rr(dev, MT_BBP(AGC, 26)) & ~0xf; in mt76x2_phy_update_channel_gain()
307 mt76_wr(dev, MT_BBP(AGC, 26), val); in mt76x2_phy_update_channel_gain()
309 mt76_wr(dev, MT_BBP(RXO, 14), 0x00560423); in mt76x2_phy_update_channel_gain()
312 if (mt76x2_has_ext_lna(dev)) in mt76x2_phy_update_channel_gain()
318 if (dev->mphy.chandef.chan->band == NL80211_BAND_2GHZ) in mt76x2_phy_update_channel_gain()
322 else if (dev->mphy.chandef.width == NL80211_CHAN_WIDTH_80) in mt76x2_phy_update_channel_gain()
328 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a990); in mt76x2_phy_update_channel_gain()
329 mt76_wr(dev, MT_BBP(AGC, 35), 0x08080808); in mt76x2_phy_update_channel_gain()
330 mt76_wr(dev, MT_BBP(AGC, 37), 0x08080808); in mt76x2_phy_update_channel_gain()
332 dev->cal.agc_gain_adjust = 0; in mt76x2_phy_update_channel_gain()
334 mt76_wr(dev, MT_BBP(RXO, 18), 0xf000a991); in mt76x2_phy_update_channel_gain()
336 dev->cal.agc_gain_adjust = low_gain_delta; in mt76x2_phy_update_channel_gain()
339 mt76_wr(dev, MT_BBP(AGC, 35), agc_35); in mt76x2_phy_update_channel_gain()
340 mt76_wr(dev, MT_BBP(AGC, 37), agc_37); in mt76x2_phy_update_channel_gain()
342 dev->cal.agc_gain_cur[0] = gain[0] - gain_delta; in mt76x2_phy_update_channel_gain()
343 dev->cal.agc_gain_cur[1] = gain[1] - gain_delta; in mt76x2_phy_update_channel_gain()
344 mt76x2_phy_set_gain_val(dev); in mt76x2_phy_update_channel_gain()
347 mt76_rr(dev, MT_RX_STAT_1); in mt76x2_phy_update_channel_gain()