Lines Matching defs:sc
191 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) argument
192 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ argument
195 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) argument
244 #define NUM_SGE_REQ(sc) \ argument
246 #define NUM_SGE_PG_REQ(sc) \ argument
248 #define SGE_TH_LO(sc) \ argument
250 #define SGE_TH_HI(sc) \ argument
312 #define NUM_BD_REQ(sc) \ argument
314 #define NUM_BD_PG_REQ(sc) \ argument
316 #define BD_TH_LO(sc) \ argument
320 #define BD_TH_HI(sc) \ argument
322 #define MIN_RX_AVAIL(sc) \ argument
324 #define MIN_RX_SIZE_TPA_HW(sc) \ argument
328 #define MIN_RX_SIZE_TPA(sc) \ argument
330 #define MIN_RX_SIZE_NONTPA(sc) \ argument
364 #define NUM_RCQ_REQ(sc) \ argument
366 #define NUM_RCQ_PG_REQ(sc) \ argument
368 #define RCQ_TH_LO(sc) \ argument
372 #define RCQ_TH_HI(sc) \ argument
450 #define BXE_SET_ERROR_BIT(sc, error) \ argument
471 struct bxe_softc *sc; member
541 struct bxe_softc *sc; member
692 #define IS_SRIOV(sc) 0 argument
694 #define GET_NUM_VFS_PER_PATH(sc) 0 argument
695 #define GET_NUM_VFS_PER_PF(sc) 0 argument
751 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) argument
809 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) argument
810 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) argument
811 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) argument
812 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) argument
814 #define FOR_EACH_QUEUE(sc, var) \ argument
817 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ argument
820 #define FOR_EACH_ETH_QUEUE(sc, var) \ argument
823 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ argument
826 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ argument
829 #define FOR_EACH_CNIC_QUEUE(sc, var) \ argument
840 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) argument
841 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) argument
842 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) argument
843 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) argument
844 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) argument
845 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) argument
847 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) argument
848 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) argument
849 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) argument
850 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) argument
851 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) argument
853 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) argument
854 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) argument
855 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) argument
856 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) argument
857 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) argument
1018 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) argument
1019 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) argument
1020 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) argument
1040 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) argument
1041 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) argument
1042 #define VNICS_PER_PATH(sc) \ argument
1052 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) argument
1053 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) argument
1056 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) argument
1059 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) argument
1062 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) argument
1067 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) argument
1075 #define IS_MF(sc) \ argument
1078 #define IS_MF_SD(sc) \ argument
1081 #define IS_MF_SI(sc) \ argument
1084 #define IS_MF_AFEX(sc) \ argument
1087 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) argument
1088 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) argument
1089 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) argument
1113 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) argument
1114 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) argument
1140 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) argument
1146 #define CHIP_REV_IS_SLOW(sc) \ argument
1148 #define CHIP_REV_IS_FPGA(sc) \ argument
1150 #define CHIP_REV_IS_EMUL(sc) \ argument
1152 #define CHIP_REV_IS_ASIC(sc) \ argument
1155 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) argument
1156 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) argument
1158 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) argument
1159 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) argument
1160 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) argument
1161 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) argument
1162 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ argument
1164 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ argument
1167 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) argument
1168 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) argument
1169 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) argument
1170 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ argument
1173 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) argument
1174 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) argument
1175 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) argument
1176 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) argument
1177 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) argument
1178 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) argument
1179 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) argument
1180 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) argument
1181 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) argument
1182 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ argument
1185 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ argument
1187 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) argument
1189 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ argument
1201 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ argument
1203 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ argument
1206 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) argument
1207 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ argument
1210 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ argument
1214 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ argument
1218 #define IS_PF(sc) (!IS_VF(sc)) argument
1232 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) argument
1238 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) argument
1239 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) argument
1246 #define CHIP_INT_MODE_IS_NBC(sc) \ argument
1249 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) argument
1329 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) argument
1336 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) argument
1385 #define SC_PATH(sc) (sc->path_id) argument
1386 #define SC_PORT(sc) (sc->pfunc_rel & 1) argument
1387 #define SC_FUNC(sc) (sc->pfunc_rel) argument
1388 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) argument
1389 #define SC_VN(sc) (sc->pfunc_rel >> 1) argument
1390 #define SC_L_ID(sc) (SC_VN(sc) << 2) argument
1391 #define PORT_ID(sc) SC_PORT(sc) argument
1392 #define PATH_ID(sc) SC_PATH(sc) argument
1393 #define VNIC_ID(sc) SC_VN(sc) argument
1394 #define FUNC_ID(sc) SC_FUNC(sc) argument
1395 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) argument
1396 #define SC_FW_MB_IDX_VN(sc, vn) \ argument
1399 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) argument
1431 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) argument
1432 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) argument
1433 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) argument
1434 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) argument
1436 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) argument
1437 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) argument
1438 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) argument
1439 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) argument
1442 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) argument
1443 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) argument
1444 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) argument
1446 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) argument
1447 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) argument
1448 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) argument
1450 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) argument
1451 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) argument
1452 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) argument
1454 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) argument
1455 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) argument
1456 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) argument
1458 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) argument
1459 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) argument
1460 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) argument
1462 #define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); argument
1463 #define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); argument
1464 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) argument
1467 #define DMAE_READY(sc) (sc->dmae_ready) argument
1620 #define GUNZIP_BUF(sc) (sc->gz_buf) argument
1621 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) argument
1622 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) argument
1629 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) argument
1639 #define INIT_OPS(sc) (sc->init_ops) argument
1640 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) argument
1641 #define INIT_DATA(sc) (sc->init_data) argument
1642 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) argument
1643 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) argument
1644 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) argument
1645 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) argument
1646 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) argument
1647 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) argument
1648 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) argument
1649 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) argument
1661 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) argument
1664 #define BXE_L2_MAX_CID(sc) \ argument
1667 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ argument
1671 #define BXE_L2_CID_COUNT(sc) \ argument
1674 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ argument
1677 #define L2_ILT_LINES(sc) \ argument
1745 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ argument
1746 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ argument
1747 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ argument
1829 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) argument
1830 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) argument
1831 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) argument
1833 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) argument
1834 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) argument
1835 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) argument
1839 #define REG_WR8(sc, offset, val) \ argument
1844 #define REG_WR16(sc, offset, val) \ argument
1849 #define REG_WR32(sc, offset, val) \ argument
1854 #define REG_RD8(sc, offset) \ argument
1859 #define REG_RD16(sc, offset) \ argument
1864 #define REG_RD32(sc, offset) \ argument
1871 #define REG_RD(sc, offset) REG_RD32(sc, offset) argument
1872 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) argument
1874 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) argument
1875 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) argument
1877 #define BXE_SP(sc, var) (&(sc)->sp->var) argument
1878 #define BXE_SP_MAPPING(sc, var) \ argument
1881 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) argument
1882 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) argument
1884 #define REG_RD_DMAE(sc, offset, valp, len32) \ argument
1890 #define REG_WR_DMAE(sc, offset, valp, len32) \ argument
1896 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ argument
1899 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ argument
1902 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ argument
1917 #define DOORBELL(sc, cid, val) \ argument
1924 #define SHMEM_ADDR(sc, field) \ argument
1926 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) argument
1927 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) argument
1928 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) argument
1930 #define SHMEM2_ADDR(sc, field) \ argument
1932 #define SHMEM2_HAS(sc, field) \ argument
1935 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) argument
1936 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) argument
1938 #define MFCFG_ADDR(sc, field) \ argument
1940 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) argument
1941 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) argument
1942 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) argument
1990 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) argument
1995 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) argument
1996 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) argument
2026 #define BXE_PMF_LINK_ASSERT(sc) \ argument
2048 #define PFS_PER_PORT(sc) \ argument
2050 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) argument
2052 #define FIRST_ABS_FUNC_IN_PORT(sc) \ argument
2056 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ argument
2074 #define HW_CID(sc, x) \ argument
2175 #define DBASSERT(sc, exp, msg) \ argument
2185 #define BLOGD(sc, codepath, format, args...) \ argument
2198 #define BLOGI(sc, format, args...) \ argument
2215 #define BLOGW(sc, format, args...) \ argument
2232 #define BLOGE(sc, format, args...) \ argument
2250 #define bxe_panic(sc, msg) \ argument
2257 #define bxe_panic(sc, msg) \ argument
2262 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); argument
2263 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) argument
2278 reg_poll(struct bxe_softc *sc, in reg_poll()
2306 bxe_igu_ack_sb_gen(struct bxe_softc *sc, in bxe_igu_ack_sb_gen()
2333 bxe_hc_ack_sb(struct bxe_softc *sc, in bxe_hc_ack_sb()
2360 bxe_ack_sb(struct bxe_softc *sc, in bxe_ack_sb()
2385 bxe_hc_ack_int(struct bxe_softc *sc) in bxe_hc_ack_int()
2396 bxe_igu_ack_int(struct bxe_softc *sc) in bxe_igu_ack_int()
2409 bxe_ack_int(struct bxe_softc *sc) in bxe_ack_int()
2420 func_by_vn(struct bxe_softc *sc, in func_by_vn()
2433 struct bxe_softc *sc = fp->sc; in bxe_stats_id() local