Lines Matching refs:reg
123 uint32_t reg; in rk3066_clk_pll_init() local
128 READ4(clk, sc->mode_reg, ®); in rk3066_clk_pll_init()
131 reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; in rk3066_clk_pll_init()
132 clknode_init_parent_idx(clk, reg); in rk3066_clk_pll_init()
140 uint32_t reg; in rk3066_clk_pll_set_mux() local
145 reg = (idx & RK3066_CLK_PLL_MODE_MASK) << sc->mode_shift; in rk3066_clk_pll_set_mux()
146 reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_mux()
150 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_mux()
161 uint32_t raw0, raw1, raw2, reg; in rk3066_clk_pll_recalc() local
170 READ4(clk, sc->mode_reg, ®); in rk3066_clk_pll_recalc()
174 reg = (reg >> sc->mode_shift) & RK3066_CLK_PLL_MODE_MASK; in rk3066_clk_pll_recalc()
176 if (reg != RK3066_CLK_PLL_MODE_NORMAL) in rk3066_clk_pll_recalc()
208 uint32_t reg; in rk3066_clk_pll_set_freq() local
228 reg = (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_freq()
230 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3066_clk_pll_set_freq()
231 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
238 reg = 0; in rk3066_clk_pll_set_freq()
239 reg |= RK3066_CLK_PLL_POSTDIV_MASK << 16; in rk3066_clk_pll_set_freq()
240 reg |= (rates->postdiv1 - 1) << RK3066_CLK_PLL_POSTDIV_SHIFT; in rk3066_clk_pll_set_freq()
242 reg |= RK3066_CLK_PLL_REFDIV_MASK << 16; in rk3066_clk_pll_set_freq()
243 reg |= (rates->refdiv - 1)<< RK3066_CLK_PLL_REFDIV_SHIFT; in rk3066_clk_pll_set_freq()
245 dprintf("Set PLL_CON0 to %x\n", reg); in rk3066_clk_pll_set_freq()
246 WRITE4(clk, sc->base_offset, reg); in rk3066_clk_pll_set_freq()
250 READ4(clk, sc->base_offset + 4, ®); in rk3066_clk_pll_set_freq()
251 reg &= ~RK3066_CLK_PLL_FBDIV_MASK; in rk3066_clk_pll_set_freq()
252 reg |= RK3066_CLK_PLL_FBDIV_MASK << 16; in rk3066_clk_pll_set_freq()
253 reg = (rates->fbdiv - 1) << RK3066_CLK_PLL_FBDIV_SHIFT; in rk3066_clk_pll_set_freq()
255 dprintf("Set PLL_CON1 to %x\n", reg); in rk3066_clk_pll_set_freq()
256 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3066_clk_pll_set_freq()
259 reg = rates->bwadj - 1; in rk3066_clk_pll_set_freq()
260 dprintf("Set PLL_CON2 to %x (%x)\n", reg, rates->bwadj); in rk3066_clk_pll_set_freq()
261 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3066_clk_pll_set_freq()
270 READ4(clk, sc->base_offset + 0x4, ®); in rk3066_clk_pll_set_freq()
271 if ((reg & RK3066_CLK_PLL_LOCK_MASK) != 0) in rk3066_clk_pll_set_freq()
281 dprintf("PLL_CON1: %x\n", reg); in rk3066_clk_pll_set_freq()
286 reg = (RK3066_CLK_PLL_MODE_NORMAL << sc->mode_shift); in rk3066_clk_pll_set_freq()
287 reg |= (RK3066_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3066_clk_pll_set_freq()
289 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3066_clk_pll_set_freq()
290 WRITE4(clk, sc->mode_reg, reg); in rk3066_clk_pll_set_freq()
427 uint32_t reg; in rk3328_clk_pll_set_freq() local
451 reg = (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3328_clk_pll_set_freq()
453 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3328_clk_pll_set_freq()
454 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
457 reg = (rates->postdiv1 << RK3328_CLK_PLL_POSTDIV1_SHIFT) | in rk3328_clk_pll_set_freq()
459 reg |= (RK3328_CLK_PLL_POSTDIV1_MASK | RK3328_CLK_PLL_FBDIV_MASK) << 16; in rk3328_clk_pll_set_freq()
460 dprintf("Set PLL_CON0 to %x\n", reg); in rk3328_clk_pll_set_freq()
461 WRITE4(clk, sc->base_offset, reg); in rk3328_clk_pll_set_freq()
464 reg = (rates->dsmpd << RK3328_CLK_PLL_DSMPD_SHIFT) | in rk3328_clk_pll_set_freq()
467 reg |= (RK3328_CLK_PLL_DSMPD_MASK | in rk3328_clk_pll_set_freq()
470 dprintf("Set PLL_CON1 to %x\n", reg); in rk3328_clk_pll_set_freq()
471 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3328_clk_pll_set_freq()
474 READ4(clk, sc->base_offset + 0x8, ®); in rk3328_clk_pll_set_freq()
475 reg &= ~RK3328_CLK_PLL_FRAC_MASK; in rk3328_clk_pll_set_freq()
476 reg |= rates->frac << RK3328_CLK_PLL_FRAC_SHIFT; in rk3328_clk_pll_set_freq()
477 dprintf("Set PLL_CON2 to %x\n", reg); in rk3328_clk_pll_set_freq()
478 WRITE4(clk, sc->base_offset + 0x8, reg); in rk3328_clk_pll_set_freq()
482 READ4(clk, sc->base_offset + 0x4, ®); in rk3328_clk_pll_set_freq()
483 if ((reg & RK3328_CLK_PLL_LOCK_MASK) == 0) in rk3328_clk_pll_set_freq()
489 reg = (RK3328_CLK_PLL_MODE_NORMAL << sc->mode_shift); in rk3328_clk_pll_set_freq()
490 reg |= (RK3328_CLK_PLL_MODE_MASK << sc->mode_shift) << in rk3328_clk_pll_set_freq()
492 dprintf("Set PLL_MODEREG to %x\n", reg); in rk3328_clk_pll_set_freq()
493 WRITE4(clk, sc->mode_reg, reg); in rk3328_clk_pll_set_freq()
668 uint32_t reg; in rk3399_clk_pll_set_freq() local
692 reg = RK3399_CLK_PLL_MODE_SLOW << RK3399_CLK_PLL_MODE_SHIFT; in rk3399_clk_pll_set_freq()
693 reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
694 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
697 reg = rates->fbdiv << RK3399_CLK_PLL_FBDIV_SHIFT; in rk3399_clk_pll_set_freq()
698 reg |= RK3399_CLK_PLL_FBDIV_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
699 WRITE4(clk, sc->base_offset, reg); in rk3399_clk_pll_set_freq()
702 reg = rates->postdiv1 << RK3399_CLK_PLL_POSTDIV1_SHIFT; in rk3399_clk_pll_set_freq()
703 reg |= rates->postdiv2 << RK3399_CLK_PLL_POSTDIV2_SHIFT; in rk3399_clk_pll_set_freq()
704 reg |= rates->refdiv << RK3399_CLK_PLL_REFDIV_SHIFT; in rk3399_clk_pll_set_freq()
705 reg |= (RK3399_CLK_PLL_POSTDIV1_MASK | RK3399_CLK_PLL_POSTDIV2_MASK | in rk3399_clk_pll_set_freq()
707 WRITE4(clk, sc->base_offset + 0x4, reg); in rk3399_clk_pll_set_freq()
710 READ4(clk, sc->base_offset + 0x8, ®); in rk3399_clk_pll_set_freq()
711 reg &= ~RK3399_CLK_PLL_FRAC_MASK; in rk3399_clk_pll_set_freq()
712 reg |= rates->frac << RK3399_CLK_PLL_FRAC_SHIFT; in rk3399_clk_pll_set_freq()
713 WRITE4(clk, sc->base_offset + 0x8, reg | RK3399_CLK_PLL_WRITE_MASK); in rk3399_clk_pll_set_freq()
716 reg = rates->dsmpd << RK3399_CLK_PLL_DSMPD_SHIFT; in rk3399_clk_pll_set_freq()
717 reg |= RK3399_CLK_PLL_DSMPD_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
718 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()
722 READ4(clk, sc->base_offset + RK3399_CLK_PLL_LOCK_OFFSET, ®); in rk3399_clk_pll_set_freq()
723 if ((reg & RK3399_CLK_PLL_LOCK_MASK) == 0) in rk3399_clk_pll_set_freq()
729 reg = RK3399_CLK_PLL_MODE_NORMAL << RK3399_CLK_PLL_MODE_SHIFT; in rk3399_clk_pll_set_freq()
730 reg |= RK3399_CLK_PLL_MODE_MASK << RK_CLK_PLL_MASK_SHIFT; in rk3399_clk_pll_set_freq()
731 WRITE4(clk, sc->base_offset + 0xC, reg); in rk3399_clk_pll_set_freq()