76 	uint32_t reg;  in ar40xx_hw_port_init()  local
113 	reg = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH  in ar40xx_hw_port_init()
115 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);  in ar40xx_hw_port_init()
117 	reg = AR40XX_PORT_LOOKUP_LEARN;  in ar40xx_hw_port_init()
118 	reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;  in ar40xx_hw_port_init()
119 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);  in ar40xx_hw_port_init()
151 	uint32_t reg;  in ar40xx_hw_port_link_up()  local
158 	reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port));  in ar40xx_hw_port_link_up()
159 	reg |= AR40XX_PORT_AUTO_LINK_EN;  in ar40xx_hw_port_link_up()
160 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg);  in ar40xx_hw_port_link_up()
173 	uint32_t reg;  in ar40xx_hw_port_cpuport_setup()  local
178 	reg = AR40XX_PORT_STATUS_TXFLOW  in ar40xx_hw_port_cpuport_setup()
183 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);  in ar40xx_hw_port_cpuport_setup()
186 	reg |= AR40XX_PORT_TX_EN | AR40XX_PORT_RX_EN;  in ar40xx_hw_port_cpuport_setup()
187         AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);  in ar40xx_hw_port_cpuport_setup()
203 	uint32_t reg;  in ar40xx_hw_get_port_pvid()  local
208 	reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(port));  in ar40xx_hw_get_port_pvid()
210 	reg = reg >> AR40XX_PORT_VLAN0_DEF_CVID_S;  in ar40xx_hw_get_port_pvid()
211 	reg = reg & 0x0fff; /* XXX */  in ar40xx_hw_get_port_pvid()
213 	*pvid = reg;  in ar40xx_hw_get_port_pvid()
226 	uint32_t reg;  in ar40xx_hw_set_port_pvid()  local
232 	reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;  in ar40xx_hw_set_port_pvid()
233 	reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;  in ar40xx_hw_set_port_pvid()
234 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);  in ar40xx_hw_set_port_pvid()
257 	uint32_t egress, ingress, reg;  in ar40xx_hw_port_setup()  local
269 	reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;  in ar40xx_hw_port_setup()
270 	reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;  in ar40xx_hw_port_setup()
271 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);  in ar40xx_hw_port_setup()
274 	reg = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;  in ar40xx_hw_port_setup()
275 	reg |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;  in ar40xx_hw_port_setup()
276 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);  in ar40xx_hw_port_setup()
279 	reg = members;  in ar40xx_hw_port_setup()
280 	reg |= AR40XX_PORT_LOOKUP_LEARN;  in ar40xx_hw_port_setup()
281 	reg |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;  in ar40xx_hw_port_setup()
282 	reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;  in ar40xx_hw_port_setup()
283 	AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);  in ar40xx_hw_port_setup()