Lines Matching refs:bw
3293 static void ice_set_clear_cir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_cir_bw() argument
3295 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_cir_bw()
3297 bw_t_info->cir_bw.bw = 0; in ice_set_clear_cir_bw()
3301 bw_t_info->cir_bw.bw = bw; in ice_set_clear_cir_bw()
3312 static void ice_set_clear_eir_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_eir_bw() argument
3314 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_eir_bw()
3316 bw_t_info->eir_bw.bw = 0; in ice_set_clear_eir_bw()
3320 bw_t_info->eir_bw.bw = bw; in ice_set_clear_eir_bw()
3331 static void ice_set_clear_shared_bw(struct ice_bw_type_info *bw_t_info, u32 bw) in ice_set_clear_shared_bw() argument
3333 if (bw == ICE_SCHED_DFLT_BW) { in ice_set_clear_shared_bw()
3339 bw_t_info->shared_bw = bw; in ice_set_clear_shared_bw()
3355 enum ice_rl_type rl_type, u32 bw) in ice_sched_save_vsi_bw() argument
3366 ice_set_clear_cir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); in ice_sched_save_vsi_bw()
3369 ice_set_clear_eir_bw(&vsi_ctx->sched.bw_t_info[tc], bw); in ice_sched_save_vsi_bw()
3372 ice_set_clear_shared_bw(&vsi_ctx->sched.bw_t_info[tc], bw); in ice_sched_save_vsi_bw()
3468 enum ice_rl_type rl_type, u32 bw) in ice_sched_save_agg_bw() argument
3479 ice_set_clear_cir_bw(&agg_info->bw_t_info[tc], bw); in ice_sched_save_agg_bw()
3482 ice_set_clear_eir_bw(&agg_info->bw_t_info[tc], bw); in ice_sched_save_agg_bw()
3485 ice_set_clear_shared_bw(&agg_info->bw_t_info[tc], bw); in ice_sched_save_agg_bw()
3506 enum ice_rl_type rl_type, u32 bw) in ice_cfg_vsi_bw_lmt_per_tc() argument
3512 tc, rl_type, bw); in ice_cfg_vsi_bw_lmt_per_tc()
3515 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); in ice_cfg_vsi_bw_lmt_per_tc()
3563 enum ice_rl_type rl_type, u32 bw) in ice_cfg_agg_bw_lmt_per_tc() argument
3568 tc, rl_type, bw); in ice_cfg_agg_bw_lmt_per_tc()
3571 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); in ice_cfg_agg_bw_lmt_per_tc()
3962 static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw) in ice_sched_calc_wakeup() argument
3969 bytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE); in ice_sched_calc_wakeup()
4006 ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw, in ice_sched_bw_to_rl_profile() argument
4017 if (bw < ICE_SCHED_MIN_BW || bw > ICE_SCHED_MAX_BW) in ice_sched_bw_to_rl_profile()
4021 bytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE); in ice_sched_bw_to_rl_profile()
4051 wm = ice_sched_calc_wakeup(hw, bw); in ice_sched_bw_to_rl_profile()
4078 u32 bw, u8 layer_num) in ice_sched_add_rl_profile() argument
4105 profile_type && rl_prof_elem->bw == bw) in ice_sched_add_rl_profile()
4116 status = ice_sched_bw_to_rl_profile(hw, bw, &rl_prof_elem->profile); in ice_sched_add_rl_profile()
4120 rl_prof_elem->bw = bw; in ice_sched_add_rl_profile()
4395 enum ice_rl_type rl_type, u32 bw, u8 layer_num) in ice_sched_set_node_bw() argument
4402 rl_prof_info = ice_sched_add_rl_profile(hw, rl_type, bw, layer_num); in ice_sched_set_node_bw()
4496 enum ice_rl_type rl_type, u32 bw) in ice_sched_set_node_bw_lmt() argument
4512 if (bw == ICE_SCHED_DFLT_BW) in ice_sched_set_node_bw_lmt()
4514 return ice_sched_set_node_bw(pi, node, rl_type, bw, layer_num); in ice_sched_set_node_bw_lmt()
4572 ice_sched_save_q_bw(struct ice_q_ctx *q_ctx, enum ice_rl_type rl_type, u32 bw) in ice_sched_save_q_bw() argument
4576 ice_set_clear_cir_bw(&q_ctx->bw_t_info, bw); in ice_sched_save_q_bw()
4579 ice_set_clear_eir_bw(&q_ctx->bw_t_info, bw); in ice_sched_save_q_bw()
4582 ice_set_clear_shared_bw(&q_ctx->bw_t_info, bw); in ice_sched_save_q_bw()
4603 u16 q_handle, enum ice_rl_type rl_type, u32 bw) in ice_sched_set_q_bw_lmt() argument
4640 if (bw == ICE_SCHED_DFLT_BW) in ice_sched_set_q_bw_lmt()
4643 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); in ice_sched_set_q_bw_lmt()
4646 status = ice_sched_save_q_bw(q_ctx, rl_type, bw); in ice_sched_set_q_bw_lmt()
4666 u16 q_handle, enum ice_rl_type rl_type, u32 bw) in ice_cfg_q_bw_lmt() argument
4669 bw); in ice_cfg_q_bw_lmt()
4702 enum ice_rl_type rl_type, u32 bw) in ice_sched_save_tc_node_bw() argument
4708 ice_set_clear_cir_bw(&pi->tc_node_bw_t_info[tc], bw); in ice_sched_save_tc_node_bw()
4711 ice_set_clear_eir_bw(&pi->tc_node_bw_t_info[tc], bw); in ice_sched_save_tc_node_bw()
4714 ice_set_clear_shared_bw(&pi->tc_node_bw_t_info[tc], bw); in ice_sched_save_tc_node_bw()
4733 enum ice_rl_type rl_type, u32 bw) in ice_sched_set_tc_node_bw_lmt() argument
4744 if (bw == ICE_SCHED_DFLT_BW) in ice_sched_set_tc_node_bw_lmt()
4747 status = ice_sched_set_node_bw_lmt(pi, tc_node, rl_type, bw); in ice_sched_set_tc_node_bw_lmt()
4749 status = ice_sched_save_tc_node_bw(pi, tc, rl_type, bw); in ice_sched_set_tc_node_bw_lmt()
4768 enum ice_rl_type rl_type, u32 bw) in ice_cfg_tc_node_bw_lmt() argument
4770 return ice_sched_set_tc_node_bw_lmt(pi, tc, rl_type, bw); in ice_cfg_tc_node_bw_lmt()
4998 enum ice_rl_type rl_type, u32 bw) in ice_sched_set_node_bw_lmt_per_tc() argument
5015 if (bw == ICE_SCHED_DFLT_BW) in ice_sched_set_node_bw_lmt_per_tc()
5018 status = ice_sched_set_node_bw_lmt(pi, node, rl_type, bw); in ice_sched_set_node_bw_lmt_per_tc()
5092 enum ice_rl_type rl_type, u32 bw) in ice_sched_set_save_vsi_srl_node_bw() argument
5096 if (bw == ICE_SCHED_DFLT_BW) { in ice_sched_set_save_vsi_srl_node_bw()
5099 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); in ice_sched_set_save_vsi_srl_node_bw()
5102 status = ice_sched_save_vsi_bw(pi, vsi_handle, tc, rl_type, bw); in ice_sched_set_save_vsi_srl_node_bw()
5321 enum ice_rl_type rl_type, u32 bw) in ice_sched_set_save_agg_srl_node_bw() argument
5325 if (bw == ICE_SCHED_DFLT_BW) { in ice_sched_set_save_agg_srl_node_bw()
5328 status = ice_sched_set_node_bw_lmt(pi, srl_node, rl_type, bw); in ice_sched_set_save_agg_srl_node_bw()
5331 status = ice_sched_save_agg_bw(pi, agg_id, tc, rl_type, bw); in ice_sched_set_save_agg_srl_node_bw()
5609 bw_t_info->cir_bw.bw); in ice_sched_replay_node_bw()
5622 bw_t_info->eir_bw.bw); in ice_sched_replay_node_bw()