Lines Matching refs:reg
115 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
120 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
121 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
123 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
125 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
127 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
129 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
131 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
138 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
141 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
143 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg); in ixgbe_dcb_config_rx_arbiter_82598()
146 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); in ixgbe_dcb_config_rx_arbiter_82598()
147 reg |= IXGBE_RDRXCTL_RDMTS_1_2; in ixgbe_dcb_config_rx_arbiter_82598()
148 reg |= IXGBE_RDRXCTL_MPBEN; in ixgbe_dcb_config_rx_arbiter_82598()
149 reg |= IXGBE_RDRXCTL_MCEN; in ixgbe_dcb_config_rx_arbiter_82598()
150 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
152 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL); in ixgbe_dcb_config_rx_arbiter_82598()
154 reg &= ~IXGBE_RXCTRL_DMBYPS; in ixgbe_dcb_config_rx_arbiter_82598()
155 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg); in ixgbe_dcb_config_rx_arbiter_82598()
174 u32 reg, max_credits; in ixgbe_dcb_config_tx_desc_arbiter_82598() local
177 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS); in ixgbe_dcb_config_tx_desc_arbiter_82598()
180 reg &= ~IXGBE_DPMCS_ARBDIS; in ixgbe_dcb_config_tx_desc_arbiter_82598()
181 reg |= IXGBE_DPMCS_TSOEF; in ixgbe_dcb_config_tx_desc_arbiter_82598()
184 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT); in ixgbe_dcb_config_tx_desc_arbiter_82598()
186 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
191 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
192 reg |= (u32)(refill[i]); in ixgbe_dcb_config_tx_desc_arbiter_82598()
193 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_desc_arbiter_82598()
196 reg |= IXGBE_TDTQ2TCCR_GSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
199 reg |= IXGBE_TDTQ2TCCR_LSP; in ixgbe_dcb_config_tx_desc_arbiter_82598()
201 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg); in ixgbe_dcb_config_tx_desc_arbiter_82598()
221 u32 reg; in ixgbe_dcb_config_tx_data_arbiter_82598() local
224 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS); in ixgbe_dcb_config_tx_data_arbiter_82598()
226 reg &= ~IXGBE_PDPMCS_ARBDIS; in ixgbe_dcb_config_tx_data_arbiter_82598()
228 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM); in ixgbe_dcb_config_tx_data_arbiter_82598()
230 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
234 reg = refill[i]; in ixgbe_dcb_config_tx_data_arbiter_82598()
235 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
236 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT; in ixgbe_dcb_config_tx_data_arbiter_82598()
239 reg |= IXGBE_TDPT2TCCR_GSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
242 reg |= IXGBE_TDPT2TCCR_LSP; in ixgbe_dcb_config_tx_data_arbiter_82598()
244 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
248 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL); in ixgbe_dcb_config_tx_data_arbiter_82598()
249 reg |= IXGBE_DTXCTL_ENDBUBD; in ixgbe_dcb_config_tx_data_arbiter_82598()
250 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg); in ixgbe_dcb_config_tx_data_arbiter_82598()
264 u32 fcrtl, reg; in ixgbe_dcb_config_pfc_82598() local
268 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_pfc_82598()
269 reg &= ~IXGBE_RMCS_TFCE_802_3X; in ixgbe_dcb_config_pfc_82598()
270 reg |= IXGBE_RMCS_TFCE_PRIORITY; in ixgbe_dcb_config_pfc_82598()
271 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_pfc_82598()
274 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL); in ixgbe_dcb_config_pfc_82598()
275 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE); in ixgbe_dcb_config_pfc_82598()
278 reg |= IXGBE_FCTRL_RPFCE; in ixgbe_dcb_config_pfc_82598()
280 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg); in ixgbe_dcb_config_pfc_82598()
291 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; in ixgbe_dcb_config_pfc_82598()
293 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg); in ixgbe_dcb_config_pfc_82598()
297 reg = hw->fc.pause_time | (hw->fc.pause_time << 16); in ixgbe_dcb_config_pfc_82598()
299 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); in ixgbe_dcb_config_pfc_82598()
316 u32 reg = 0; in ixgbe_dcb_config_tc_stats_82598() local
322 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
323 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
324 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()
325 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1)); in ixgbe_dcb_config_tc_stats_82598()
326 reg |= ((0x1010101) * j); in ixgbe_dcb_config_tc_stats_82598()
327 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg); in ixgbe_dcb_config_tc_stats_82598()
331 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i)); in ixgbe_dcb_config_tc_stats_82598()
332 reg |= ((0x1010101) * i); in ixgbe_dcb_config_tc_stats_82598()
333 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg); in ixgbe_dcb_config_tc_stats_82598()