Lines Matching refs:m

40 #define	MLX5_CORE_PCI_DIAGNOSTICS(m) \  argument
41 m(+1, pxd_ready_bp, 0x0401) \
42 m(+1, pci_write_bp, 0x0402) \
43 m(+1, pci_read_bp, 0x0403) \
44 m(+1, pci_read_stuck_no_completion_buffer, 0x0404) \
45 m(+1, max_pci_bw, 0x0405) \
46 m(+1, used_pci_bw, 0x0406) \
47 m(+1, rx_pci_errors, 0) \
48 m(+1, tx_pci_errors, 0) \
49 m(+1, tx_pci_correctable_errors, 0) \
50 m(+1, tx_pci_non_fatal_errors, 0) \
51 m(+1, tx_pci_fatal_errors, 0)
67 #define	MLX5_CORE_GENERAL_DIAGNOSTICS(m) \  argument
68 m(+1, l0_mtt_miss, 0x0801) \
69 m(+1, l0_mtt_hit, 0x0802) \
70 m(+1, l1_mtt_miss, 0x0803) \
71 m(+1, l1_mtt_hit, 0x0804) \
72 m(+1, l0_mpt_miss, 0x0805) \
73 m(+1, l0_mpt_hit, 0x0806) \
74 m(+1, l1_mpt_miss, 0x0807) \
75 m(+1, l1_mpt_hit, 0x0808) \
76 m(+1, rxb_no_slow_path_credits, 0x0c01) \
77 m(+1, rxb_no_fast_path_credits, 0x0c02) \
78 m(+1, rxb_rxt_no_slow_path_cred_perf_count, 0x0c03) \
79 m(+1, rxb_rxt_no_fast_path_cred_perf_count, 0x0c04) \
80 m(+1, rxt_ctrl_perf_slice_load_slow, 0x1001) \
81 m(+1, rxt_ctrl_perf_slice_load_fast, 0x1002) \
82 m(+1, rxt_steering_perf_count_steering0_rse_work_rate, 0x1003) \
83 m(+1, rxt_steering_perf_count_steering1_rse_work_rate, 0x1004) \
84 m(+1, perf_count_tpt_credit, 0x1401) \
85 m(+1, perf_wb_miss, 0x1402) \
86 m(+1, perf_wb_hit, 0x1403) \
87 m(+1, rxw_perf_rx_l1_slow_miss_ldb, 0x1404) \
88 m(+1, rxw_perf_rx_l1_slow_hit_ldb, 0x1405) \
89 m(+1, rxw_perf_rx_l1_fast_miss_ldb, 0x1406) \
90 m(+1, rxw_perf_rx_l1_fast_hit_ldb, 0x1407) \
91 m(+1, rxw_perf_l2_cache_read_miss_ldb, 0x1408) \
92 m(+1, rxw_perf_l2_cache_read_hit_ldb, 0x1409) \
93 m(+1, rxw_perf_rx_l1_slow_miss_reqsl, 0x140a) \
94 m(+1, rxw_perf_rx_l1_slow_hit_reqsl, 0x140b) \
95 m(+1, rxw_perf_rx_l1_fast_miss_reqsl, 0x140c) \
96 m(+1, rxw_perf_rx_l1_fast_hit_reqsl, 0x140d) \
97 m(+1, rxw_perf_l2_cache_read_miss_reqsl, 0x140e) \
98 m(+1, rxw_perf_l2_cache_read_hit_reqsl, 0x140f) \
99 m(+1, rxs_no_pxt_credits, 0x1801) \
100 m(+1, rxc_eq_all_slices_busy, 0x1c01) \
101 m(+1, rxc_cq_all_slices_busy, 0x1c02) \
102 m(+1, rxc_msix_all_slices_busy, 0x1c03) \
103 m(+1, sxw_qp_done_due_to_vl_limited, 0x2001) \
104 m(+1, sxw_qp_done_due_to_desched, 0x2002) \
105 m(+1, sxw_qp_done_due_to_work_done, 0x2003) \
106 m(+1, sxw_qp_done_due_to_limited, 0x2004) \
107 m(+1, sxw_qp_done_due_to_e2e_credits, 0x2005) \
108 m(+1, sxw_packet_send_sxw2sxp_go_vld, 0x2006) \
109 m(+1, sxw_perf_count_steering_hit, 0x2007) \
110 m(+1, sxw_perf_count_steering_miss, 0x2008) \
111 m(+1, sxw_perf_count_steering_rse_0, 0x2009) \
112 m(+1, sxd_no_sched_credits, 0x2401) \
113 m(+1, sxd_no_slow_path_sched_credits, 0x2402) \
114 m(+1, tpt_indirect_mem_key, 0x2801)