44 static int oce_POST(POCE_SOFTC sc);
51 oce_POST(POCE_SOFTC sc)  in oce_POST()  argument
57 	post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));  in oce_POST()
62 		OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);  in oce_POST()
72 		post_status.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_SEMAPHORE(sc));  in oce_POST()
74 			device_printf(sc->dev,  in oce_POST()
82 	device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);  in oce_POST()
92 oce_hw_init(POCE_SOFTC sc)  in oce_hw_init()  argument
96 	rc = oce_POST(sc);  in oce_hw_init()
101 	rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);  in oce_hw_init()
103 		device_printf(sc->dev, "Mailbox alloc failed\n");  in oce_hw_init()
107 	rc = oce_reset_fun(sc);  in oce_hw_init()
112 	rc = oce_mbox_init(sc);  in oce_hw_init()
116 	rc = oce_get_fw_version(sc);  in oce_hw_init()
120 	rc = oce_get_fw_config(sc);  in oce_hw_init()
124 	sc->macaddr.size_of_struct = 6;  in oce_hw_init()
125 	rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,  in oce_hw_init()
126 					&sc->macaddr);  in oce_hw_init()
130 	if ((IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) || IS_SH(sc)) {  in oce_hw_init()
131 		rc = oce_mbox_check_native_mode(sc);  in oce_hw_init()
135 		sc->be3_native = 0;  in oce_hw_init()
140 	oce_dma_free(sc, &sc->bsmbx);  in oce_hw_init()
141 	device_printf(sc->dev, "Hardware initialisation failed\n");  in oce_hw_init()
150 oce_hw_pci_free(POCE_SOFTC sc)  in oce_hw_pci_free()  argument
154 	if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))  in oce_hw_pci_free()
159 	if (sc->devcfg_res != NULL) {  in oce_hw_pci_free()
160 		bus_release_resource(sc->dev,  in oce_hw_pci_free()
162 				     PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);  in oce_hw_pci_free()
163 		sc->devcfg_res = (struct resource *)NULL;  in oce_hw_pci_free()
164 		sc->devcfg_btag = (bus_space_tag_t) 0;  in oce_hw_pci_free()
165 		sc->devcfg_bhandle = (bus_space_handle_t)0;  in oce_hw_pci_free()
166 		sc->devcfg_vhandle = (void *)NULL;  in oce_hw_pci_free()
169 	if (sc->csr_res != NULL) {  in oce_hw_pci_free()
170 		bus_release_resource(sc->dev,  in oce_hw_pci_free()
172 				     PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);  in oce_hw_pci_free()
173 		sc->csr_res = (struct resource *)NULL;  in oce_hw_pci_free()
174 		sc->csr_btag = (bus_space_tag_t)0;  in oce_hw_pci_free()
175 		sc->csr_bhandle = (bus_space_handle_t)0;  in oce_hw_pci_free()
176 		sc->csr_vhandle = (void *)NULL;  in oce_hw_pci_free()
179 	if (sc->db_res != NULL) {  in oce_hw_pci_free()
180 		bus_release_resource(sc->dev,  in oce_hw_pci_free()
182 				     PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);  in oce_hw_pci_free()
183 		sc->db_res = (struct resource *)NULL;  in oce_hw_pci_free()
184 		sc->db_btag = (bus_space_tag_t)0;  in oce_hw_pci_free()
185 		sc->db_bhandle = (bus_space_handle_t)0;  in oce_hw_pci_free()
186 		sc->db_vhandle = (void *)NULL;  in oce_hw_pci_free()
195 void oce_get_pci_capabilities(POCE_SOFTC sc)  in oce_get_pci_capabilities()  argument
199 	if (pci_find_cap(sc->dev, PCIY_PCIX, &val) == 0) {  in oce_get_pci_capabilities()
201 			sc->flags |= OCE_FLAGS_PCIX;  in oce_get_pci_capabilities()
204 	if (pci_find_cap(sc->dev, PCIY_EXPRESS, &val) == 0) {  in oce_get_pci_capabilities()
207 			    pci_read_config(sc->dev, val + 0x12, 2);  in oce_get_pci_capabilities()
209 			sc->flags |= OCE_FLAGS_PCIE;  in oce_get_pci_capabilities()
210 			sc->pcie_link_speed = link_status & 0xf;  in oce_get_pci_capabilities()
211 			sc->pcie_link_width = (link_status >> 4) & 0x3f;  in oce_get_pci_capabilities()
215 	if (pci_find_cap(sc->dev, PCIY_MSI, &val) == 0) {  in oce_get_pci_capabilities()
217 			sc->flags |= OCE_FLAGS_MSI_CAPABLE;  in oce_get_pci_capabilities()
220 	if (pci_find_cap(sc->dev, PCIY_MSIX, &val) == 0) {  in oce_get_pci_capabilities()
222 			val = pci_msix_count(sc->dev);  in oce_get_pci_capabilities()
223 			sc->flags |= OCE_FLAGS_MSIX_CAPABLE;  in oce_get_pci_capabilities()
235 oce_hw_pci_alloc(POCE_SOFTC sc)  in oce_hw_pci_alloc()  argument
240 	pci_enable_busmaster(sc->dev);  in oce_hw_pci_alloc()
242 	oce_get_pci_capabilities(sc);  in oce_hw_pci_alloc()
244 	sc->fn = pci_get_function(sc->dev);  in oce_hw_pci_alloc()
247 	if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))  in oce_hw_pci_alloc()
254 	if (IS_BE(sc) || IS_SH(sc))   in oce_hw_pci_alloc()
255 		sc->devcfg_res = bus_alloc_resource_any(sc->dev,  in oce_hw_pci_alloc()
259 		sc->devcfg_res = bus_alloc_resource_anywhere(sc->dev,  in oce_hw_pci_alloc()
263 	if (!sc->devcfg_res)  in oce_hw_pci_alloc()
266 	sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);  in oce_hw_pci_alloc()
267 	sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);  in oce_hw_pci_alloc()
268 	sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);  in oce_hw_pci_alloc()
273 	intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);  in oce_hw_pci_alloc()
279 		device_printf(sc->dev, "Adapter doesnt support SLI4\n");  in oce_hw_pci_alloc()
284 		sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;  in oce_hw_pci_alloc()
287 		sc->flags |= OCE_FLAGS_FUNCRESET_RQD;  in oce_hw_pci_alloc()
290 		sc->flags |= OCE_FLAGS_VIRTUAL_PORT;  in oce_hw_pci_alloc()
293 	if (IS_BE(sc) || IS_SH(sc)) {  in oce_hw_pci_alloc()
296 		sc->csr_res = bus_alloc_resource_any(sc->dev,  in oce_hw_pci_alloc()
298 		if (!sc->csr_res)  in oce_hw_pci_alloc()
300 		sc->csr_btag = rman_get_bustag(sc->csr_res);  in oce_hw_pci_alloc()
301 		sc->csr_bhandle = rman_get_bushandle(sc->csr_res);  in oce_hw_pci_alloc()
302 		sc->csr_vhandle = rman_get_virtual(sc->csr_res);  in oce_hw_pci_alloc()
306 		sc->db_res = bus_alloc_resource_any(sc->dev,  in oce_hw_pci_alloc()
308 		if (!sc->db_res)  in oce_hw_pci_alloc()
310 		sc->db_btag = rman_get_bustag(sc->db_res);  in oce_hw_pci_alloc()
311 		sc->db_bhandle = rman_get_bushandle(sc->db_res);  in oce_hw_pci_alloc()
312 		sc->db_vhandle = rman_get_virtual(sc->db_res);  in oce_hw_pci_alloc()
318 	oce_hw_pci_free(sc);  in oce_hw_pci_alloc()
328 oce_hw_shutdown(POCE_SOFTC sc)  in oce_hw_shutdown()  argument
331 	oce_stats_free(sc);  in oce_hw_shutdown()
333 	oce_hw_intr_disable(sc);  in oce_hw_shutdown()
336 	oce_free_lro(sc);  in oce_hw_shutdown()
339 	oce_queue_release_all(sc);  in oce_hw_shutdown()
341 	oce_delete_nw_interface(sc);  in oce_hw_shutdown()
343 	oce_fw_clean(sc);  in oce_hw_shutdown()
345 	oce_intr_free(sc);  in oce_hw_shutdown()
347 	oce_hw_pci_free(sc);  in oce_hw_shutdown()
349 	LOCK_DESTROY(&sc->bmbx_lock);  in oce_hw_shutdown()
350 	LOCK_DESTROY(&sc->dev_lock);  in oce_hw_shutdown()
352 	oce_dma_free(sc, &sc->bsmbx);  in oce_hw_shutdown()
361 oce_create_nw_interface(POCE_SOFTC sc)  in oce_create_nw_interface()  argument
373 	if (IS_XE201(sc)) {  in oce_create_nw_interface()
379 	if (IS_SH(sc) || IS_XE201(sc))  in oce_create_nw_interface()
382         if (sc->enable_hwlro) {  in oce_create_nw_interface()
388 	if (is_rss_enabled(sc))  in oce_create_nw_interface()
395 	rc = oce_if_create(sc,  in oce_create_nw_interface()
398 			   0, &sc->macaddr.mac_addr[0], &sc->if_id);  in oce_create_nw_interface()
402 	atomic_inc_32(&sc->nifs);  in oce_create_nw_interface()
404 	sc->if_cap_flags = capab_en_flags;  in oce_create_nw_interface()
407 	rc = oce_set_flow_control(sc, sc->flow_control);  in oce_create_nw_interface()
411 	rc = oce_rxf_set_promiscuous(sc, sc->promisc);  in oce_create_nw_interface()
418 	oce_delete_nw_interface(sc);  in oce_create_nw_interface()
428 oce_delete_nw_interface(POCE_SOFTC sc)  in oce_delete_nw_interface()  argument
431 	if (sc->nifs > 0) {  in oce_delete_nw_interface()
432 		oce_if_del(sc, sc->if_id);  in oce_delete_nw_interface()
433 		atomic_dec_32(&sc->nifs);  in oce_delete_nw_interface()
443 oce_pci_soft_reset(POCE_SOFTC sc)  in oce_pci_soft_reset()  argument
448 	ctrl.dw0 = OCE_READ_CSR_MPU(sc, csr, MPU_EP_CONTROL);  in oce_pci_soft_reset()
450 	OCE_WRITE_CSR_MPU(sc, csr, MPU_EP_CONTROL, ctrl.dw0);  in oce_pci_soft_reset()
452 	rc=oce_POST(sc);  in oce_pci_soft_reset()
463 oce_hw_start(POCE_SOFTC sc)  in oce_hw_start()  argument
468 	rc = oce_get_link_status(sc, &link);  in oce_hw_start()
473 		sc->link_status = NTWK_LOGICAL_LINK_UP;  in oce_hw_start()
474 		if_link_state_change(sc->ifp, LINK_STATE_UP);  in oce_hw_start()
476 		sc->link_status = NTWK_LOGICAL_LINK_DOWN;  in oce_hw_start()
477 		if_link_state_change(sc->ifp, LINK_STATE_DOWN);  in oce_hw_start()
480 	sc->link_speed = link.phys_port_speed;  in oce_hw_start()
481 	sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;  in oce_hw_start()
483 	rc = oce_start_mq(sc->mq);  in oce_hw_start()
488 	oce_hw_intr_enable(sc);  in oce_hw_start()
489 	oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);  in oce_hw_start()
494 	oce_first_mcc_cmd(sc);  in oce_hw_start()
504 oce_hw_intr_enable(POCE_SOFTC sc)  in oce_hw_intr_enable()  argument
508 	reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);  in oce_hw_intr_enable()
510 	OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);  in oce_hw_intr_enable()
519 oce_hw_intr_disable(POCE_SOFTC sc)  in oce_hw_intr_disable()  argument
523 	reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);  in oce_hw_intr_disable()
525 	OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);  in oce_hw_intr_disable()
547 oce_hw_update_multicast(POCE_SOFTC sc)  in oce_hw_update_multicast()  argument
549 	if_t ifp = sc->ifp;  in oce_hw_update_multicast()
555 	if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),  in oce_hw_update_multicast()
571 	req->params.req.if_id = sc->if_id;  in oce_hw_update_multicast()
572 	rc = oce_update_multicast(sc, &dma);  in oce_hw_update_multicast()
573 	oce_dma_free(sc, &dma);  in oce_hw_update_multicast()