Lines Matching refs:sc
65 qcom_spi_hw_read_controller_transfer_sizes(struct qcom_spi_softc *sc) in qcom_spi_hw_read_controller_transfer_sizes() argument
69 reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES); in qcom_spi_hw_read_controller_transfer_sizes()
71 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_read_controller_transfer_sizes()
78 sc->config.input_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
80 sc->config.input_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
86 sc->config.output_block_size = 4; in qcom_spi_hw_read_controller_transfer_sizes()
88 sc->config.output_block_size = val * 16; in qcom_spi_hw_read_controller_transfer_sizes()
93 sc->config.input_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
94 sc->config.input_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
99 sc->config.output_fifo_size = in qcom_spi_hw_read_controller_transfer_sizes()
100 sc->config.output_block_size * (2 << val); in qcom_spi_hw_read_controller_transfer_sizes()
106 qcom_spi_hw_qup_is_state_valid_locked(struct qcom_spi_softc *sc) in qcom_spi_hw_qup_is_state_valid_locked() argument
110 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_qup_is_state_valid_locked()
112 reg = QCOM_SPI_READ_4(sc, QUP_STATE); in qcom_spi_hw_qup_is_state_valid_locked()
113 QCOM_SPI_BARRIER_READ(sc); in qcom_spi_hw_qup_is_state_valid_locked()
119 qcom_spi_hw_qup_wait_state_valid_locked(struct qcom_spi_softc *sc) in qcom_spi_hw_qup_wait_state_valid_locked() argument
124 if (qcom_spi_hw_qup_is_state_valid_locked(sc)) in qcom_spi_hw_qup_wait_state_valid_locked()
128 device_printf(sc->sc_dev, in qcom_spi_hw_qup_wait_state_valid_locked()
136 qcom_spi_hw_is_opmode_dma_locked(struct qcom_spi_softc *sc) in qcom_spi_hw_is_opmode_dma_locked() argument
139 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_is_opmode_dma_locked()
141 if (sc->state.transfer_mode == QUP_IO_M_MODE_DMOV) in qcom_spi_hw_is_opmode_dma_locked()
143 if (sc->state.transfer_mode == QUP_IO_M_MODE_BAM) in qcom_spi_hw_is_opmode_dma_locked()
149 qcom_spi_hw_qup_set_state_locked(struct qcom_spi_softc *sc, uint32_t state) in qcom_spi_hw_qup_set_state_locked() argument
154 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_qup_set_state_locked()
157 ret = qcom_spi_hw_qup_wait_state_valid_locked(sc); in qcom_spi_hw_qup_set_state_locked()
162 cur_state = QCOM_SPI_READ_4(sc, QUP_STATE); in qcom_spi_hw_qup_set_state_locked()
164 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_STATE_CHANGE, in qcom_spi_hw_qup_set_state_locked()
174 QCOM_SPI_WRITE_4(sc, QUP_STATE, QUP_STATE_CLEAR); in qcom_spi_hw_qup_set_state_locked()
175 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_qup_set_state_locked()
176 QCOM_SPI_WRITE_4(sc, QUP_STATE, QUP_STATE_CLEAR); in qcom_spi_hw_qup_set_state_locked()
177 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_qup_set_state_locked()
181 QCOM_SPI_WRITE_4(sc, QUP_STATE, cur_state); in qcom_spi_hw_qup_set_state_locked()
182 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_qup_set_state_locked()
186 ret = qcom_spi_hw_qup_wait_state_valid_locked(sc); in qcom_spi_hw_qup_set_state_locked()
191 cur_state = QCOM_SPI_READ_4(sc, QUP_STATE); in qcom_spi_hw_qup_set_state_locked()
193 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_STATE_CHANGE, in qcom_spi_hw_qup_set_state_locked()
207 qcom_spi_hw_qup_init_locked(struct qcom_spi_softc *sc) in qcom_spi_hw_qup_init_locked() argument
211 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_qup_init_locked()
214 (void) qcom_spi_hw_do_full_reset(sc); in qcom_spi_hw_qup_init_locked()
216 ret = qcom_spi_hw_qup_set_state_locked(sc, QUP_STATE_RESET); in qcom_spi_hw_qup_init_locked()
218 device_printf(sc->sc_dev, "ERROR: %s: couldn't reset\n", in qcom_spi_hw_qup_init_locked()
223 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, 0); in qcom_spi_hw_qup_init_locked()
224 QCOM_SPI_WRITE_4(sc, QUP_IO_M_MODES, 0); in qcom_spi_hw_qup_init_locked()
226 if (! QCOM_SPI_QUP_VERSION_V1(sc)) in qcom_spi_hw_qup_init_locked()
227 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK, 0); in qcom_spi_hw_qup_init_locked()
230 if (QCOM_SPI_QUP_VERSION_V1(sc)) in qcom_spi_hw_qup_init_locked()
231 QCOM_SPI_WRITE_4(sc, QUP_ERROR_FLAGS_EN, in qcom_spi_hw_qup_init_locked()
235 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_qup_init_locked()
246 qcom_spi_hw_spi_init_locked(struct qcom_spi_softc *sc) in qcom_spi_hw_spi_init_locked() argument
249 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_spi_init_locked()
252 QCOM_SPI_WRITE_4(sc, SPI_ERROR_FLAGS_EN, in qcom_spi_hw_spi_init_locked()
255 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_spi_init_locked()
258 QCOM_SPI_WRITE_4(sc, SPI_CONFIG, 0); in qcom_spi_hw_spi_init_locked()
259 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_spi_init_locked()
262 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, in qcom_spi_hw_spi_init_locked()
264 | SPI_IO_C_CS_SELECT(sc->config.cs_select)); in qcom_spi_hw_spi_init_locked()
265 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_spi_init_locked()
282 qcom_spi_hw_spi_cs_force(struct qcom_spi_softc *sc, int cs, bool enable) in qcom_spi_hw_spi_cs_force() argument
286 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_spi_cs_force()
288 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_CHIPSELECT, in qcom_spi_hw_spi_cs_force()
292 reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL); in qcom_spi_hw_spi_cs_force()
299 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg); in qcom_spi_hw_spi_cs_force()
300 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_spi_cs_force()
309 qcom_spi_hw_interrupt_handle(struct qcom_spi_softc *sc) in qcom_spi_hw_interrupt_handle() argument
313 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_interrupt_handle()
316 qup_error = QCOM_SPI_READ_4(sc, QUP_ERROR_FLAGS); in qcom_spi_hw_interrupt_handle()
317 spi_error = QCOM_SPI_READ_4(sc, SPI_ERROR_FLAGS); in qcom_spi_hw_interrupt_handle()
318 op_flags = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL); in qcom_spi_hw_interrupt_handle()
321 QCOM_SPI_WRITE_4(sc, QUP_ERROR_FLAGS, qup_error); in qcom_spi_hw_interrupt_handle()
322 QCOM_SPI_WRITE_4(sc, SPI_ERROR_FLAGS, spi_error); in qcom_spi_hw_interrupt_handle()
324 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_INTR, in qcom_spi_hw_interrupt_handle()
333 device_printf(sc->sc_dev, "ERROR: (QUP) mask=0x%08x\n", in qcom_spi_hw_interrupt_handle()
335 sc->intr.error = true; in qcom_spi_hw_interrupt_handle()
338 device_printf(sc->sc_dev, "ERROR: (SPI) mask=0x%08x\n", in qcom_spi_hw_interrupt_handle()
340 sc->intr.error = true; in qcom_spi_hw_interrupt_handle()
344 if (qcom_spi_hw_is_opmode_dma_locked(sc)) { in qcom_spi_hw_interrupt_handle()
346 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, op_flags); in qcom_spi_hw_interrupt_handle()
349 sc->intr.rx_dma_done = true; in qcom_spi_hw_interrupt_handle()
352 sc->intr.tx_dma_done = true; in qcom_spi_hw_interrupt_handle()
356 sc->intr.do_rx = true; in qcom_spi_hw_interrupt_handle()
358 sc->intr.do_tx = true; in qcom_spi_hw_interrupt_handle()
363 sc->intr.done = true; in qcom_spi_hw_interrupt_handle()
364 if (sc->intr.error) in qcom_spi_hw_interrupt_handle()
365 sc->intr.done = true; in qcom_spi_hw_interrupt_handle()
378 qcom_spi_hw_setup_transfer_selection(struct qcom_spi_softc *sc, uint32_t len) in qcom_spi_hw_setup_transfer_selection() argument
381 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_transfer_selection()
387 sc->state.transfer_mode = QUP_IO_M_MODE_FIFO; in qcom_spi_hw_setup_transfer_selection()
388 sc->transfer.tx_offset = 0; in qcom_spi_hw_setup_transfer_selection()
389 sc->transfer.rx_offset = 0; in qcom_spi_hw_setup_transfer_selection()
390 sc->transfer.tx_len = 0; in qcom_spi_hw_setup_transfer_selection()
391 sc->transfer.rx_len = 0; in qcom_spi_hw_setup_transfer_selection()
392 sc->transfer.tx_buf = NULL; in qcom_spi_hw_setup_transfer_selection()
393 sc->transfer.rx_buf = NULL; in qcom_spi_hw_setup_transfer_selection()
403 sc->state.transfer_word_size = 4; in qcom_spi_hw_setup_transfer_selection()
405 sc->state.transfer_word_size = 1; in qcom_spi_hw_setup_transfer_selection()
414 qcom_spi_hw_complete_transfer(struct qcom_spi_softc *sc) in qcom_spi_hw_complete_transfer() argument
416 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_complete_transfer()
418 sc->state.transfer_mode = QUP_IO_M_MODE_FIFO; in qcom_spi_hw_complete_transfer()
419 sc->transfer.tx_offset = 0; in qcom_spi_hw_complete_transfer()
420 sc->transfer.rx_offset = 0; in qcom_spi_hw_complete_transfer()
421 sc->transfer.tx_len = 0; in qcom_spi_hw_complete_transfer()
422 sc->transfer.rx_len = 0; in qcom_spi_hw_complete_transfer()
423 sc->transfer.tx_buf = NULL; in qcom_spi_hw_complete_transfer()
424 sc->transfer.rx_buf = NULL; in qcom_spi_hw_complete_transfer()
425 sc->state.transfer_word_size = 0; in qcom_spi_hw_complete_transfer()
436 qcom_spi_hw_setup_current_transfer(struct qcom_spi_softc *sc) in qcom_spi_hw_setup_current_transfer() argument
440 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_current_transfer()
449 bytes_left = sc->transfer.tx_len - sc->transfer.tx_offset; in qcom_spi_hw_setup_current_transfer()
451 if (sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) { in qcom_spi_hw_setup_current_transfer()
458 sc->transfer.num_words = bytes_left / sc->state.transfer_word_size; in qcom_spi_hw_setup_current_transfer()
459 sc->transfer.num_words = MIN(sc->transfer.num_words, in qcom_spi_hw_setup_current_transfer()
460 sc->config.input_fifo_size / sizeof(uint32_t)); in qcom_spi_hw_setup_current_transfer()
461 } else if (sc->state.transfer_mode == QUP_IO_M_MODE_BLOCK) { in qcom_spi_hw_setup_current_transfer()
471 sc->transfer.num_words = bytes_left / sc->state.transfer_word_size; in qcom_spi_hw_setup_current_transfer()
472 sc->transfer.num_words = MIN(sc->transfer.num_words, in qcom_spi_hw_setup_current_transfer()
477 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_current_transfer()
483 sc->transfer.tx_len, in qcom_spi_hw_setup_current_transfer()
484 sc->transfer.tx_offset, in qcom_spi_hw_setup_current_transfer()
485 sc->state.transfer_word_size, in qcom_spi_hw_setup_current_transfer()
487 sc->transfer.num_words, in qcom_spi_hw_setup_current_transfer()
488 sc->config.input_fifo_size / sizeof(uint32_t)); in qcom_spi_hw_setup_current_transfer()
500 qcom_spi_hw_setup_pio_transfer_cnt(struct qcom_spi_softc *sc) in qcom_spi_hw_setup_pio_transfer_cnt() argument
503 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_pio_transfer_cnt()
505 QCOM_SPI_WRITE_4(sc, QUP_MX_READ_CNT, sc->transfer.num_words); in qcom_spi_hw_setup_pio_transfer_cnt()
506 QCOM_SPI_WRITE_4(sc, QUP_MX_WRITE_CNT, sc->transfer.num_words); in qcom_spi_hw_setup_pio_transfer_cnt()
507 QCOM_SPI_WRITE_4(sc, QUP_MX_INPUT_CNT, 0); in qcom_spi_hw_setup_pio_transfer_cnt()
508 QCOM_SPI_WRITE_4(sc, QUP_MX_OUTPUT_CNT, 0); in qcom_spi_hw_setup_pio_transfer_cnt()
510 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_pio_transfer_cnt()
512 sc->transfer.num_words); in qcom_spi_hw_setup_pio_transfer_cnt()
514 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_pio_transfer_cnt()
527 qcom_spi_hw_setup_block_transfer_cnt(struct qcom_spi_softc *sc) in qcom_spi_hw_setup_block_transfer_cnt() argument
530 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_block_transfer_cnt()
532 QCOM_SPI_WRITE_4(sc, QUP_MX_READ_CNT, 0); in qcom_spi_hw_setup_block_transfer_cnt()
533 QCOM_SPI_WRITE_4(sc, QUP_MX_WRITE_CNT, 0); in qcom_spi_hw_setup_block_transfer_cnt()
534 QCOM_SPI_WRITE_4(sc, QUP_MX_INPUT_CNT, sc->transfer.num_words); in qcom_spi_hw_setup_block_transfer_cnt()
535 QCOM_SPI_WRITE_4(sc, QUP_MX_OUTPUT_CNT, sc->transfer.num_words); in qcom_spi_hw_setup_block_transfer_cnt()
536 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_block_transfer_cnt()
542 qcom_spi_hw_setup_io_modes(struct qcom_spi_softc *sc) in qcom_spi_hw_setup_io_modes() argument
546 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_io_modes()
548 reg = QCOM_SPI_READ_4(sc, QUP_IO_M_MODES); in qcom_spi_hw_setup_io_modes()
561 if (qcom_spi_hw_is_opmode_dma_locked(sc)) in qcom_spi_hw_setup_io_modes()
567 reg |= ((sc->state.transfer_mode & QUP_IO_M_INPUT_MODE_MASK) in qcom_spi_hw_setup_io_modes()
569 reg |= ((sc->state.transfer_mode & QUP_IO_M_OUTPUT_MODE_MASK) in qcom_spi_hw_setup_io_modes()
572 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_io_modes()
575 QCOM_SPI_WRITE_4(sc, QUP_IO_M_MODES, reg); in qcom_spi_hw_setup_io_modes()
576 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_io_modes()
582 qcom_spi_hw_setup_spi_io_clock_polarity(struct qcom_spi_softc *sc, in qcom_spi_hw_setup_spi_io_clock_polarity() argument
587 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_spi_io_clock_polarity()
589 reg = QCOM_SPI_READ_4(sc, SPI_IO_CONTROL); in qcom_spi_hw_setup_spi_io_clock_polarity()
596 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_spi_io_clock_polarity()
599 QCOM_SPI_WRITE_4(sc, SPI_IO_CONTROL, reg); in qcom_spi_hw_setup_spi_io_clock_polarity()
600 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_spi_io_clock_polarity()
606 qcom_spi_hw_setup_spi_config(struct qcom_spi_softc *sc, uint32_t clock_val, in qcom_spi_hw_setup_spi_config() argument
617 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_spi_config()
619 reg = QCOM_SPI_READ_4(sc, SPI_CONFIG); in qcom_spi_hw_setup_spi_config()
638 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_spi_config()
641 QCOM_SPI_WRITE_4(sc, SPI_CONFIG, reg); in qcom_spi_hw_setup_spi_config()
642 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_spi_config()
648 qcom_spi_hw_setup_qup_config(struct qcom_spi_softc *sc, bool is_tx, bool is_rx) in qcom_spi_hw_setup_qup_config() argument
652 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_qup_config()
654 reg = QCOM_SPI_READ_4(sc, QUP_CONFIG); in qcom_spi_hw_setup_qup_config()
661 reg |= ((sc->state.transfer_word_size * 8) - 1) & QUP_CONFIG_N; in qcom_spi_hw_setup_qup_config()
668 if (qcom_spi_hw_is_opmode_dma_locked(sc)) { in qcom_spi_hw_setup_qup_config()
675 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_qup_config()
678 QCOM_SPI_WRITE_4(sc, QUP_CONFIG, reg); in qcom_spi_hw_setup_qup_config()
679 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_qup_config()
685 qcom_spi_hw_setup_operational_mask(struct qcom_spi_softc *sc) in qcom_spi_hw_setup_operational_mask() argument
688 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_setup_operational_mask()
690 if (QCOM_SPI_QUP_VERSION_V1(sc)) { in qcom_spi_hw_setup_operational_mask()
691 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TRANSFER_SETUP, in qcom_spi_hw_setup_operational_mask()
696 if (qcom_spi_hw_is_opmode_dma_locked(sc)) in qcom_spi_hw_setup_operational_mask()
697 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK, in qcom_spi_hw_setup_operational_mask()
700 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL_MASK, 0); in qcom_spi_hw_setup_operational_mask()
702 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_setup_operational_mask()
711 qcom_spi_hw_ack_write_pio_fifo(struct qcom_spi_softc *sc) in qcom_spi_hw_ack_write_pio_fifo() argument
714 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_ack_write_pio_fifo()
715 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG); in qcom_spi_hw_ack_write_pio_fifo()
716 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_ack_write_pio_fifo()
721 qcom_spi_hw_ack_opmode(struct qcom_spi_softc *sc) in qcom_spi_hw_ack_opmode() argument
724 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_ack_opmode()
726 QCOM_SPI_BARRIER_READ(sc); in qcom_spi_hw_ack_opmode()
727 QCOM_SPI_READ_4(sc, QUP_OPERATIONAL); in qcom_spi_hw_ack_opmode()
728 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG); in qcom_spi_hw_ack_opmode()
729 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_ack_opmode()
742 qcom_spi_hw_write_from_tx_buf(struct qcom_spi_softc *sc, int shift, in qcom_spi_hw_write_from_tx_buf() argument
746 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_write_from_tx_buf()
748 if (sc->transfer.tx_buf == NULL) in qcom_spi_hw_write_from_tx_buf()
751 if (sc->transfer.tx_offset < sc->transfer.tx_len) { in qcom_spi_hw_write_from_tx_buf()
752 *val |= (sc->transfer.tx_buf[sc->transfer.tx_offset] & 0xff) in qcom_spi_hw_write_from_tx_buf()
754 sc->transfer.tx_offset++; in qcom_spi_hw_write_from_tx_buf()
762 qcom_spi_hw_write_pio_fifo(struct qcom_spi_softc *sc) in qcom_spi_hw_write_pio_fifo() argument
767 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_write_pio_fifo()
769 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_OUT_SERVICE_FLAG); in qcom_spi_hw_write_pio_fifo()
770 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_write_pio_fifo()
775 for (i = 0; i < sc->transfer.num_words; i++) { in qcom_spi_hw_write_pio_fifo()
779 if ((QCOM_SPI_READ_4(sc, QUP_OPERATIONAL) in qcom_spi_hw_write_pio_fifo()
781 device_printf(sc->sc_dev, "%s: FIFO full\n", __func__); in qcom_spi_hw_write_pio_fifo()
798 if (sc->state.transfer_word_size == 1) { in qcom_spi_hw_write_pio_fifo()
799 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®)) in qcom_spi_hw_write_pio_fifo()
801 } else if (sc->state.transfer_word_size == 2) { in qcom_spi_hw_write_pio_fifo()
802 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®)) in qcom_spi_hw_write_pio_fifo()
804 if (qcom_spi_hw_write_from_tx_buf(sc, 16, ®)) in qcom_spi_hw_write_pio_fifo()
806 } else if (sc->state.transfer_word_size == 4) { in qcom_spi_hw_write_pio_fifo()
807 if (qcom_spi_hw_write_from_tx_buf(sc, 24, ®)) in qcom_spi_hw_write_pio_fifo()
809 if (qcom_spi_hw_write_from_tx_buf(sc, 16, ®)) in qcom_spi_hw_write_pio_fifo()
811 if (qcom_spi_hw_write_from_tx_buf(sc, 8, ®)) in qcom_spi_hw_write_pio_fifo()
813 if (qcom_spi_hw_write_from_tx_buf(sc, 0, ®)) in qcom_spi_hw_write_pio_fifo()
822 QCOM_SPI_WRITE_4(sc, QUP_OUTPUT_FIFO, reg); in qcom_spi_hw_write_pio_fifo()
823 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_write_pio_fifo()
826 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TX_FIFO, in qcom_spi_hw_write_pio_fifo()
828 __func__, num_bytes, sc->transfer.num_words); in qcom_spi_hw_write_pio_fifo()
834 qcom_spi_hw_write_pio_block(struct qcom_spi_softc *sc) in qcom_spi_hw_write_pio_block() argument
847 qcom_spi_hw_read_into_rx_buf(struct qcom_spi_softc *sc, uint8_t val) in qcom_spi_hw_read_into_rx_buf() argument
849 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_read_into_rx_buf()
851 if (sc->transfer.rx_buf == NULL) in qcom_spi_hw_read_into_rx_buf()
855 if (sc->transfer.rx_offset < sc->transfer.rx_len) { in qcom_spi_hw_read_into_rx_buf()
856 sc->transfer.rx_buf[sc->transfer.rx_offset] = val; in qcom_spi_hw_read_into_rx_buf()
857 sc->transfer.rx_offset++; in qcom_spi_hw_read_into_rx_buf()
869 qcom_spi_hw_read_pio_fifo(struct qcom_spi_softc *sc) in qcom_spi_hw_read_pio_fifo() argument
875 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_read_pio_fifo()
877 QCOM_SPI_WRITE_4(sc, QUP_OPERATIONAL, QUP_OP_IN_SERVICE_FLAG); in qcom_spi_hw_read_pio_fifo()
878 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_read_pio_fifo()
880 for (i = 0; i < sc->transfer.num_words; i++) { in qcom_spi_hw_read_pio_fifo()
882 QCOM_SPI_BARRIER_READ(sc); in qcom_spi_hw_read_pio_fifo()
883 reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL); in qcom_spi_hw_read_pio_fifo()
885 device_printf(sc->sc_dev, "%s: FIFO empty\n", __func__); in qcom_spi_hw_read_pio_fifo()
894 reg = QCOM_SPI_READ_4(sc, QUP_INPUT_FIFO); in qcom_spi_hw_read_pio_fifo()
900 if (sc->state.transfer_word_size == 1) { in qcom_spi_hw_read_pio_fifo()
901 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff)) in qcom_spi_hw_read_pio_fifo()
903 } else if (sc->state.transfer_word_size == 2) { in qcom_spi_hw_read_pio_fifo()
904 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff)) in qcom_spi_hw_read_pio_fifo()
906 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff)) in qcom_spi_hw_read_pio_fifo()
908 } else if (sc->state.transfer_word_size == 4) { in qcom_spi_hw_read_pio_fifo()
909 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 24) & 0xff)) in qcom_spi_hw_read_pio_fifo()
911 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 16) & 0xff)) in qcom_spi_hw_read_pio_fifo()
913 if (qcom_spi_hw_read_into_rx_buf(sc, (reg >> 8) & 0xff)) in qcom_spi_hw_read_pio_fifo()
915 if (qcom_spi_hw_read_into_rx_buf(sc, reg & 0xff)) in qcom_spi_hw_read_pio_fifo()
920 QCOM_SPI_DPRINTF(sc, QCOM_SPI_DEBUG_HW_TX_FIFO, in qcom_spi_hw_read_pio_fifo()
922 __func__, num_bytes, sc->transfer.num_words); in qcom_spi_hw_read_pio_fifo()
929 QCOM_SPI_BARRIER_READ(sc); in qcom_spi_hw_read_pio_fifo()
930 reg = QCOM_SPI_READ_4(sc, QUP_OPERATIONAL); in qcom_spi_hw_read_pio_fifo()
932 device_printf(sc->sc_dev, "%s: read complete (DONE)\n" , in qcom_spi_hw_read_pio_fifo()
934 sc->intr.done = true; in qcom_spi_hw_read_pio_fifo()
946 if ((sc->state.transfer_mode == QUP_IO_M_MODE_FIFO) in qcom_spi_hw_read_pio_fifo()
947 && (sc->transfer.rx_offset >= sc->transfer.rx_len)) { in qcom_spi_hw_read_pio_fifo()
948 device_printf(sc->sc_dev, "%s: read complete (rxlen)\n", in qcom_spi_hw_read_pio_fifo()
950 sc->intr.done = true; in qcom_spi_hw_read_pio_fifo()
959 sc->intr.done = true; in qcom_spi_hw_read_pio_fifo()
965 qcom_spi_hw_read_pio_block(struct qcom_spi_softc *sc) in qcom_spi_hw_read_pio_block() argument
973 qcom_spi_hw_do_full_reset(struct qcom_spi_softc *sc) in qcom_spi_hw_do_full_reset() argument
975 QCOM_SPI_ASSERT_LOCKED(sc); in qcom_spi_hw_do_full_reset()
977 QCOM_SPI_WRITE_4(sc, QUP_SW_RESET, 1); in qcom_spi_hw_do_full_reset()
978 QCOM_SPI_BARRIER_WRITE(sc); in qcom_spi_hw_do_full_reset()