Lines Matching refs:slot
81 #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) argument
82 #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) argument
83 #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) argument
84 #define RD_MULTI_4(slot, off, ptr, count) \ argument
85 SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
87 #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) argument
88 #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) argument
89 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) argument
90 #define WR_MULTI_4(slot, off, ptr, count) \ argument
91 SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count))
93 static void sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err);
96 static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask);
97 static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask);
98 static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset);
99 static void sdhci_handle_card_present_locked(struct sdhci_slot *slot,
101 static void sdhci_finish_command(struct sdhci_slot *slot);
102 static void sdhci_init(struct sdhci_slot *slot);
103 static void sdhci_read_block_pio(struct sdhci_slot *slot);
104 static void sdhci_req_done(struct sdhci_slot *slot);
107 static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock);
108 static void sdhci_set_power(struct sdhci_slot *slot, u_char power);
109 static void sdhci_set_transfer_mode(struct sdhci_slot *slot,
111 static void sdhci_start(struct sdhci_slot *slot);
113 static void sdhci_start_command(struct sdhci_slot *slot,
115 static void sdhci_start_data(struct sdhci_slot *slot,
117 static void sdhci_write_block_pio(struct sdhci_slot *slot);
118 static void sdhci_transfer_pio(struct sdhci_slot *slot);
123 static int sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot,
126 static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb);
127 static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb);
128 static int sdhci_cam_update_ios(struct sdhci_slot *slot);
132 static int sdhci_dma_alloc(struct sdhci_slot *slot);
133 static void sdhci_dma_free(struct sdhci_slot *slot);
134 static void sdhci_dumpcaps(struct sdhci_slot *slot);
135 static void sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s);
136 static void sdhci_dumpregs(struct sdhci_slot *slot);
137 static void sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s);
142 static int slot_printf(const struct sdhci_slot *slot, const char * fmt, ...)
144 static int slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s,
146 static uint32_t sdhci_tuning_intmask(const struct sdhci_slot *slot);
190 slot_printf(const struct sdhci_slot *slot, const char * fmt, ...) in slot_printf() argument
205 device_get_nameunit(slot->bus), slot->num, buf); in slot_printf()
210 slot_sprintf(const struct sdhci_slot *slot, struct sbuf *s, in slot_sprintf() argument
216 retval = sbuf_printf(s, "%s-slot%d: ", device_get_nameunit(slot->bus), slot->num); in slot_sprintf()
226 sdhci_dumpregs_buf(struct sdhci_slot *slot, struct sbuf *s) in sdhci_dumpregs_buf() argument
228 slot_sprintf(slot, s, "============== REGISTER DUMP ==============\n"); in sdhci_dumpregs_buf()
230 slot_sprintf(slot, s, "Sys addr: 0x%08x | Version: 0x%08x\n", in sdhci_dumpregs_buf()
231 RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); in sdhci_dumpregs_buf()
232 slot_sprintf(slot, s, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", in sdhci_dumpregs_buf()
233 RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); in sdhci_dumpregs_buf()
234 slot_sprintf(slot, s, "Argument: 0x%08x | Trn mode: 0x%08x\n", in sdhci_dumpregs_buf()
235 RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); in sdhci_dumpregs_buf()
236 slot_sprintf(slot, s, "Present: 0x%08x | Host ctl: 0x%08x\n", in sdhci_dumpregs_buf()
237 RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); in sdhci_dumpregs_buf()
238 slot_sprintf(slot, s, "Power: 0x%08x | Blk gap: 0x%08x\n", in sdhci_dumpregs_buf()
239 RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); in sdhci_dumpregs_buf()
240 slot_sprintf(slot, s, "Wake-up: 0x%08x | Clock: 0x%08x\n", in sdhci_dumpregs_buf()
241 RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); in sdhci_dumpregs_buf()
242 slot_sprintf(slot, s, "Timeout: 0x%08x | Int stat: 0x%08x\n", in sdhci_dumpregs_buf()
243 RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); in sdhci_dumpregs_buf()
244 slot_sprintf(slot, s, "Int enab: 0x%08x | Sig enab: 0x%08x\n", in sdhci_dumpregs_buf()
245 RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs_buf()
246 slot_sprintf(slot, s, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", in sdhci_dumpregs_buf()
247 RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs_buf()
248 slot_sprintf(slot, s, "Caps: 0x%08x | Caps2: 0x%08x\n", in sdhci_dumpregs_buf()
249 RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); in sdhci_dumpregs_buf()
250 slot_sprintf(slot, s, "Max curr: 0x%08x | ADMA err: 0x%08x\n", in sdhci_dumpregs_buf()
251 RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); in sdhci_dumpregs_buf()
252 slot_sprintf(slot, s, "ADMA addr:0x%08x | Slot int: 0x%08x\n", in sdhci_dumpregs_buf()
253 RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); in sdhci_dumpregs_buf()
255 slot_sprintf(slot, s, "===========================================\n"); in sdhci_dumpregs_buf()
259 sdhci_dumpregs(struct sdhci_slot *slot) in sdhci_dumpregs() argument
264 slot_printf(slot, "sdhci_dumpregs: Failed to allocate memory for sbuf\n"); in sdhci_dumpregs()
269 sdhci_dumpregs_buf(slot, &s); in sdhci_dumpregs()
277 struct sdhci_slot *slot = arg1; in sdhci_syctl_dumpregs() local
282 sdhci_dumpregs_buf(slot, &s); in sdhci_syctl_dumpregs()
290 sdhci_dumpcaps_buf(struct sdhci_slot *slot, struct sbuf *s) in sdhci_dumpcaps_buf() argument
292 int host_caps = slot->host.caps; in sdhci_dumpcaps_buf()
293 int caps = slot->caps; in sdhci_dumpcaps_buf()
295 slot_sprintf(slot, s, in sdhci_dumpcaps_buf()
297 slot->max_clk / 1000000, in sdhci_dumpcaps_buf()
304 (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", in sdhci_dumpcaps_buf()
310 (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", in sdhci_dumpcaps_buf()
311 (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : in sdhci_dumpcaps_buf()
312 (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : in sdhci_dumpcaps_buf()
316 slot_sprintf(slot, s, "eMMC:%s%s%s%s\n", in sdhci_dumpcaps_buf()
326 slot_sprintf(slot, s, "UHS-I:%s%s%s%s%s\n", in sdhci_dumpcaps_buf()
332 if (slot->opt & SDHCI_TUNING_SUPPORTED) in sdhci_dumpcaps_buf()
333 slot_sprintf(slot, s, in sdhci_dumpcaps_buf()
335 slot->retune_count, slot->retune_mode + 1); in sdhci_dumpcaps_buf()
339 sdhci_dumpcaps(struct sdhci_slot *slot) in sdhci_dumpcaps() argument
344 slot_printf(slot, "sdhci_dumpcaps: Failed to allocate memory for sbuf\n"); in sdhci_dumpcaps()
349 sdhci_dumpcaps_buf(slot, &s); in sdhci_dumpcaps()
357 struct sdhci_slot *slot = arg1; in sdhci_syctl_dumpcaps() local
362 sdhci_dumpcaps_buf(slot, &s); in sdhci_syctl_dumpcaps()
370 sdhci_tuning_intmask(const struct sdhci_slot *slot) in sdhci_tuning_intmask() argument
375 if (slot->opt & SDHCI_TUNING_ENABLED) { in sdhci_tuning_intmask()
377 if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || in sdhci_tuning_intmask()
378 slot->retune_mode == SDHCI_RETUNE_MODE_3) in sdhci_tuning_intmask()
385 sdhci_init(struct sdhci_slot *slot) in sdhci_init() argument
388 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL); in sdhci_init()
391 slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | in sdhci_init()
398 if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && in sdhci_init()
399 !(slot->opt & SDHCI_NON_REMOVABLE)) { in sdhci_init()
400 slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; in sdhci_init()
403 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); in sdhci_init()
404 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); in sdhci_init()
408 sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) in sdhci_set_clock() argument
417 if (clock == slot->clock) in sdhci_set_clock()
419 clock = SDHCI_SET_CLOCK(slot->bus, slot, clock); in sdhci_set_clock()
420 slot->clock = clock; in sdhci_set_clock()
423 clk = RD2(slot, SDHCI_CLOCK_CONTROL); in sdhci_set_clock()
424 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); in sdhci_set_clock()
430 clk_base = slot->max_clk; in sdhci_set_clock()
431 if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { in sdhci_set_clock()
432 clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & in sdhci_set_clock()
447 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); in sdhci_set_clock()
451 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) in sdhci_set_clock()
452 slot->timeout_clk = slot->clock / 1000; in sdhci_set_clock()
454 if (slot->version < SDHCI_SPEC_300) { in sdhci_set_clock()
478 slot_printf(slot, "Divider %d for freq %d (base %d)\n", in sdhci_set_clock()
486 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
489 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
492 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) in sdhci_set_clock()
495 slot_printf(slot, in sdhci_set_clock()
497 sdhci_dumpregs(slot); in sdhci_set_clock()
505 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
509 sdhci_set_power(struct sdhci_slot *slot, u_char power) in sdhci_set_power() argument
514 if (slot->power == power) in sdhci_set_power()
517 slot->power = power; in sdhci_set_power()
521 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
539 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
547 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
548 if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) in sdhci_set_power()
552 if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) in sdhci_set_power()
553 slot_printf(slot, "Bus power failed to enable\n"); in sdhci_set_power()
555 if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { in sdhci_set_power()
556 WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); in sdhci_set_power()
558 WR1(slot, SDHCI_POWER_CONTROL, pwr); in sdhci_set_power()
564 sdhci_read_block_pio(struct sdhci_slot *slot) in sdhci_read_block_pio() argument
570 buffer = slot->curcmd->data->data; in sdhci_read_block_pio()
571 buffer += slot->offset; in sdhci_read_block_pio()
574 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) in sdhci_read_block_pio()
575 left = min(slot->curcmd->data->block_size, in sdhci_read_block_pio()
576 slot->curcmd->data->len - slot->offset); in sdhci_read_block_pio()
579 left = min(512, slot->curcmd->data->len - slot->offset); in sdhci_read_block_pio()
580 slot->offset += left; in sdhci_read_block_pio()
583 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) in sdhci_read_block_pio()
588 data = RD4(slot, SDHCI_BUFFER); in sdhci_read_block_pio()
597 RD_MULTI_4(slot, SDHCI_BUFFER, in sdhci_read_block_pio()
603 data = RD4(slot, SDHCI_BUFFER); in sdhci_read_block_pio()
613 sdhci_write_block_pio(struct sdhci_slot *slot) in sdhci_write_block_pio() argument
619 buffer = slot->curcmd->data->data; in sdhci_write_block_pio()
620 buffer += slot->offset; in sdhci_write_block_pio()
623 if (slot->curcmd->data->flags & MMC_DATA_BLOCK_SIZE) { in sdhci_write_block_pio()
624 left = min(slot->curcmd->data->block_size, in sdhci_write_block_pio()
625 slot->curcmd->data->len - slot->offset); in sdhci_write_block_pio()
628 left = min(512, slot->curcmd->data->len - slot->offset); in sdhci_write_block_pio()
629 slot->offset += left; in sdhci_write_block_pio()
640 WR4(slot, SDHCI_BUFFER, data); in sdhci_write_block_pio()
643 WR_MULTI_4(slot, SDHCI_BUFFER, in sdhci_write_block_pio()
654 WR4(slot, SDHCI_BUFFER, data); in sdhci_write_block_pio()
659 sdhci_transfer_pio(struct sdhci_slot *slot) in sdhci_transfer_pio() argument
663 if (slot->curcmd->data->flags & MMC_DATA_READ) { in sdhci_transfer_pio()
664 while (RD4(slot, SDHCI_PRESENT_STATE) & in sdhci_transfer_pio()
666 sdhci_read_block_pio(slot); in sdhci_transfer_pio()
667 if (slot->offset >= slot->curcmd->data->len) in sdhci_transfer_pio()
671 while (RD4(slot, SDHCI_PRESENT_STATE) & in sdhci_transfer_pio()
673 sdhci_write_block_pio(slot); in sdhci_transfer_pio()
674 if (slot->offset >= slot->curcmd->data->len) in sdhci_transfer_pio()
683 struct sdhci_slot *slot = arg; local
688 SDHCI_LOCK(slot);
689 if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) {
691 if (slot->card_present == 0) {
693 if (slot->dev == NULL) {
697 slot_printf(slot, "Card inserted\n");
699 slot->card_present = 1;
700 mmccam_start_discovery(slot->sim);
701 SDHCI_UNLOCK(slot);
703 d = slot->dev = device_add_child(slot->bus, "mmc", -1);
704 SDHCI_UNLOCK(slot);
706 device_set_ivars(d, slot);
711 SDHCI_UNLOCK(slot);
714 if (slot->card_present == 1) {
716 if (slot->dev != NULL) {
717 d = slot->dev;
721 slot_printf(slot, "Card removed\n");
722 slot->dev = NULL;
724 slot->card_present = 0;
725 mmccam_start_discovery(slot->sim);
726 SDHCI_UNLOCK(slot);
728 slot->intmask &= ~sdhci_tuning_intmask(slot);
729 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
730 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
731 slot->opt &= ~SDHCI_TUNING_ENABLED;
732 SDHCI_UNLOCK(slot);
733 callout_drain(&slot->retune_callout);
734 device_delete_child(slot->bus, d);
737 SDHCI_UNLOCK(slot);
742 sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) argument
758 was_present = slot->card_present;
760 was_present = slot->dev != NULL;
764 &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS);
766 taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task);
771 sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) argument
774 SDHCI_LOCK(slot);
775 sdhci_handle_card_present_locked(slot, is_present);
776 SDHCI_UNLOCK(slot);
782 struct sdhci_slot *slot = arg; local
784 sdhci_handle_card_present(slot,
785 SDHCI_GET_CARD_PRESENT(slot->bus, slot));
786 callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS,
787 sdhci_card_poll, slot);
791 sdhci_dma_alloc(struct sdhci_slot *slot) argument
795 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_SDMA_BOUNDARY)) {
797 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_4K;
799 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_8K;
801 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_16K;
803 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_32K;
805 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_64K;
807 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_128K;
809 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_256K;
811 slot->sdma_boundary = SDHCI_BLKSZ_SDMA_BNDRY_512K;
813 slot->sdma_bbufsz = SDHCI_SDMA_BNDRY_TO_BBUFSZ(slot->sdma_boundary);
823 err = bus_dma_tag_create(bus_get_dma_tag(slot->bus), slot->sdma_bbufsz,
825 slot->sdma_bbufsz, 1, slot->sdma_bbufsz, BUS_DMA_ALLOCNOW,
826 NULL, NULL, &slot->dmatag);
828 slot_printf(slot, "Can't create DMA tag for SDMA\n");
832 err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem,
833 BUS_DMA_NOWAIT, &slot->dmamap);
835 slot_printf(slot, "Can't alloc DMA memory for SDMA\n");
836 bus_dma_tag_destroy(slot->dmatag);
840 err = bus_dmamap_load(slot->dmatag, slot->dmamap,
841 (void *)slot->dmamem, slot->sdma_bbufsz, sdhci_getaddr,
842 &slot->paddr, 0);
843 if (err != 0 || slot->paddr == 0) {
844 slot_printf(slot, "Can't load DMA memory for SDMA\n");
845 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
846 bus_dma_tag_destroy(slot->dmatag);
857 sdhci_dma_free(struct sdhci_slot *slot) argument
860 bus_dmamap_unload(slot->dmatag, slot->dmamap);
861 bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap);
862 bus_dma_tag_destroy(slot->dmatag);
866 sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) argument
875 SDHCI_LOCK_INIT(slot);
877 slot->num = num;
878 slot->bus = dev;
880 slot->version = (RD2(slot, SDHCI_HOST_VERSION)
882 if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) {
883 caps = slot->caps;
884 caps2 = slot->caps2;
886 caps = RD4(slot, SDHCI_CAPABILITIES);
887 if (slot->version >= SDHCI_SPEC_300)
888 caps2 = RD4(slot, SDHCI_CAPABILITIES2);
892 if (slot->version >= SDHCI_SPEC_300) {
895 slot_printf(slot,
897 SDHCI_LOCK_DESTROY(slot);
901 slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE;
905 if (slot->version >= SDHCI_SPEC_300)
912 slot->max_clk = freq * 1000000;
918 if (slot->max_clk == 0) {
919 slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000;
920 slot_printf(slot, "Hardware doesn't specify base clock "
925 if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) {
926 slot->timeout_clk = slot->max_clk / 1000;
927 } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) {
928 slot->timeout_clk = 1000;
930 slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >>
933 slot->timeout_clk *= 1000;
940 if (slot->timeout_clk == 0) {
941 slot_printf(slot, "Hardware doesn't specify timeout clock "
943 slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
946 slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot);
947 slot->host.f_max = slot->max_clk;
948 slot->host.host_ocr = 0;
950 slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340;
952 slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310;
958 if ((caps & SDHCI_CAN_VDD_180) && (slot->version < SDHCI_SPEC_300 ||
959 (slot->opt & SDHCI_SLOT_EMBEDDED)))
960 slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE;
961 if (slot->host.host_ocr == 0) {
962 slot_printf(slot, "Hardware doesn't report any "
966 host_caps = slot->host.caps;
972 if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC)
974 if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY)
982 if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200))
987 !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50))
989 if (slot->quirks & SDHCI_QUIRK_MMC_DDR52)
991 if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 &&
994 if (slot->quirks & SDHCI_QUIRK_MMC_HS400_IF_CAN_SDR104 &&
1034 slot->opt |= SDHCI_TUNING_SUPPORTED;
1035 slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF,
1037 slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF,
1039 slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF,
1042 slot->opt |= SDHCI_SDR50_NEEDS_TUNING;
1043 slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >>
1045 if (slot->retune_mode == SDHCI_RETUNE_MODE_1) {
1046 slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >>
1048 if (slot->retune_count > 0xb) {
1049 slot_printf(slot, "Unknown re-tuning count "
1050 "%x, using 1 sec\n", slot->retune_count);
1051 slot->retune_count = 1;
1052 } else if (slot->retune_count != 0)
1053 slot->retune_count =
1054 1 << (slot->retune_count - 1);
1088 slot->host.caps = host_caps;
1092 slot->opt |= SDHCI_HAVE_DMA;
1094 if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA)
1095 slot->opt &= ~SDHCI_HAVE_DMA;
1096 if (slot->quirks & SDHCI_QUIRK_FORCE_DMA)
1097 slot->opt |= SDHCI_HAVE_DMA;
1098 if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE)
1099 slot->opt |= SDHCI_NON_REMOVABLE;
1105 if (slot->opt & SDHCI_PLATFORM_TRANSFER)
1106 slot->opt &= ~SDHCI_HAVE_DMA;
1108 if (slot->opt & SDHCI_HAVE_DMA) {
1109 err = sdhci_dma_alloc(slot);
1111 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1112 free(slot->tune_req, M_DEVBUF);
1113 free(slot->tune_cmd, M_DEVBUF);
1114 free(slot->tune_data, M_DEVBUF);
1116 SDHCI_LOCK_DESTROY(slot);
1122 sdhci_dumpcaps(slot);
1123 sdhci_dumpregs(slot);
1126 slot->timeout = 10;
1127 SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus),
1128 SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO,
1129 "timeout", CTLFLAG_RWTUN, &slot->timeout, 0,
1131 TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot);
1132 TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0,
1133 sdhci_card_task, slot);
1134 callout_init(&slot->card_poll_callout, 1);
1135 callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0);
1136 callout_init_mtx(&slot->retune_callout, &slot->mtx, 0);
1138 if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) &&
1139 !(slot->opt & SDHCI_NON_REMOVABLE)) {
1140 callout_reset(&slot->card_poll_callout,
1141 SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot);
1144 sdhci_init(slot);
1146 snprintf(node_name, sizeof(node_name), "slot%d", slot->num);
1158 slot, 0, &sdhci_syctl_dumpregs,
1163 slot, 0, &sdhci_syctl_dumpcaps,
1171 sdhci_start_slot(struct sdhci_slot *slot) argument
1174 sdhci_card_task(slot, 0);
1179 sdhci_cleanup_slot(struct sdhci_slot *slot) argument
1183 callout_drain(&slot->timeout_callout);
1184 callout_drain(&slot->card_poll_callout);
1185 callout_drain(&slot->retune_callout);
1186 taskqueue_drain(taskqueue_swi_giant, &slot->card_task);
1187 taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task);
1189 SDHCI_LOCK(slot);
1190 d = slot->dev;
1191 slot->dev = NULL;
1192 SDHCI_UNLOCK(slot);
1194 device_delete_child(slot->bus, d);
1196 SDHCI_LOCK(slot);
1197 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1198 SDHCI_UNLOCK(slot);
1199 if (slot->opt & SDHCI_HAVE_DMA)
1200 sdhci_dma_free(slot);
1201 if (slot->opt & SDHCI_TUNING_SUPPORTED) {
1202 free(slot->tune_req, M_DEVBUF);
1203 free(slot->tune_cmd, M_DEVBUF);
1204 free(slot->tune_data, M_DEVBUF);
1207 SDHCI_LOCK_DESTROY(slot);
1213 sdhci_generic_suspend(struct sdhci_slot *slot) argument
1221 callout_drain(&slot->retune_callout);
1222 SDHCI_LOCK(slot);
1223 slot->opt &= ~SDHCI_TUNING_ENABLED;
1224 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_ALL);
1225 SDHCI_UNLOCK(slot);
1231 sdhci_generic_resume(struct sdhci_slot *slot) argument
1234 SDHCI_LOCK(slot);
1235 sdhci_init(slot);
1236 SDHCI_UNLOCK(slot);
1242 sdhci_generic_reset(device_t brdev __unused, struct sdhci_slot *slot, argument
1248 if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
1249 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot))
1255 (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) {
1257 clock = slot->clock;
1258 slot->clock = 0;
1259 sdhci_set_clock(slot, clock);
1263 slot->clock = 0;
1264 slot->power = 0;
1267 WR1(slot, SDHCI_SOFTWARE_RESET, mask);
1269 if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) {
1279 while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) {
1290 while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) {
1292 slot_printf(slot, "Reset 0x%x never completed.\n",
1294 sdhci_dumpregs(slot);
1303 sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) argument
1306 if (slot->version >= SDHCI_SPEC_300)
1307 return (slot->max_clk / SDHCI_300_MAX_DIVIDER);
1309 return (slot->max_clk / SDHCI_200_MAX_DIVIDER);
1313 sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) argument
1316 if (slot->opt & SDHCI_NON_REMOVABLE)
1319 return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1323 sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) argument
1328 if (slot->version < SDHCI_SPEC_300)
1331 SDHCI_ASSERT_LOCKED(slot);
1332 ios = &slot->host.ios;
1333 sdhci_set_clock(slot, 0);
1334 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1353 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1354 sdhci_set_clock(slot, ios->clock);
1360 struct sdhci_slot *slot = device_get_ivars(reqdev); local
1361 struct mmc_ios *ios = &slot->host.ios;
1363 SDHCI_LOCK(slot);
1366 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
1367 sdhci_init(slot);
1370 sdhci_set_clock(slot, ios->clock);
1371 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
1373 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
1374 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1376 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1377 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
1379 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
1380 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
1385 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
1386 slot->hostctrl |= SDHCI_CTRL_HISPD;
1388 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
1389 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
1390 SDHCI_SET_UHS_TIMING(brdev, slot);
1392 if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
1393 SDHCI_RESET(slot->bus, slot,
1396 SDHCI_UNLOCK(slot);
1403 struct sdhci_slot *slot = device_get_ivars(reqdev); local
1408 if (slot->version < SDHCI_SPEC_300)
1412 vccq = slot->host.ios.vccq;
1413 SDHCI_LOCK(slot);
1414 sdhci_set_clock(slot, 0);
1415 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1421 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1423 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1429 if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) {
1436 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1438 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1444 slot_printf(slot,
1450 sdhci_set_clock(slot, slot->host.ios.clock);
1451 SDHCI_UNLOCK(slot);
1458 struct sdhci_slot *slot = device_get_ivars(reqdev); local
1459 const struct mmc_ios *ios = &slot->host.ios;
1465 if (!(slot->opt & SDHCI_TUNING_SUPPORTED))
1468 slot->retune_ticks = slot->retune_count * hz;
1470 SDHCI_LOCK(slot);
1473 slot_printf(slot, "HS400 must be tuned in HS200 mode\n");
1474 SDHCI_UNLOCK(slot);
1483 slot->retune_ticks = 0;
1490 if (slot->opt & SDHCI_SDR50_NEEDS_TUNING)
1492 SDHCI_UNLOCK(slot);
1495 slot_printf(slot, "Tuning requested but not required.\n");
1496 SDHCI_UNLOCK(slot);
1500 tune_cmd = slot->tune_cmd;
1504 tune_data = tune_cmd->data = slot->tune_data;
1510 tune_data->mrq = tune_cmd->mrq = slot->tune_req;
1512 slot->opt &= ~SDHCI_TUNING_ENABLED;
1513 err = sdhci_exec_tuning(slot, true);
1515 slot->opt |= SDHCI_TUNING_ENABLED;
1516 slot->intmask |= sdhci_tuning_intmask(slot);
1517 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
1518 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1519 if (slot->retune_ticks) {
1520 callout_reset(&slot->retune_callout, slot->retune_ticks,
1521 sdhci_retune, slot);
1524 SDHCI_UNLOCK(slot);
1531 struct sdhci_slot *slot = device_get_ivars(reqdev); local
1534 if (!(slot->opt & SDHCI_TUNING_ENABLED))
1538 if (slot->host.ios.timing == bus_timing_mmc_hs400)
1541 SDHCI_LOCK(slot);
1542 err = sdhci_exec_tuning(slot, reset);
1554 if (slot->retune_ticks) {
1555 callout_reset(&slot->retune_callout, slot->retune_ticks,
1556 sdhci_retune, slot);
1558 SDHCI_UNLOCK(slot);
1563 sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) argument
1572 SDHCI_ASSERT_LOCKED(slot);
1573 if (slot->req != NULL)
1577 opt = slot->opt;
1578 slot->opt = opt & ~SDHCI_HAVE_DMA;
1584 intmask = slot->intmask;
1585 slot->intmask = SDHCI_INT_DATA_AVAIL;
1586 WR4(slot, SDHCI_INT_ENABLE, SDHCI_INT_DATA_AVAIL);
1587 WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL);
1589 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1594 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);
1596 tune_req = slot->tune_req;
1597 tune_cmd = slot->tune_cmd;
1602 tune_req->done_data = slot;
1603 slot->req = tune_req;
1604 slot->flags = 0;
1605 sdhci_start(slot);
1607 msleep(tune_req, &slot->mtx, 0, "sdhciet", 0);
1610 hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2);
1624 slot->opt = opt;
1625 slot->intmask = intmask;
1626 WR4(slot, SDHCI_INT_ENABLE, intmask | SDHCI_INT_DMA_END |
1628 WR4(slot, SDHCI_SIGNAL_ENABLE, intmask);
1632 slot->retune_req = 0;
1636 slot_printf(slot, "Tuning failed, using fixed sampling clock\n");
1637 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |
1639 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1646 struct sdhci_slot *slot = arg; local
1648 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
1653 sdhci_req_done(struct sdhci_slot *slot) argument
1658 slot_printf(slot, "%s\n", __func__);
1659 if (slot->ccb != NULL && slot->curcmd != NULL) {
1660 callout_stop(&slot->timeout_callout);
1661 ccb = slot->ccb;
1662 slot->ccb = NULL;
1663 slot->curcmd = NULL;
1676 sdhci_req_done(struct sdhci_slot *slot) argument
1680 if (slot->req != NULL && slot->curcmd != NULL) {
1681 callout_stop(&slot->timeout_callout);
1682 req = slot->req;
1683 slot->req = NULL;
1684 slot->curcmd = NULL;
1701 struct sdhci_slot *slot = arg; local
1703 if (slot->curcmd != NULL) {
1704 slot_printf(slot, "Controller timeout\n");
1705 sdhci_dumpregs(slot);
1706 SDHCI_RESET(slot->bus, slot,
1708 slot->curcmd->error = MMC_ERR_TIMEOUT;
1709 sdhci_req_done(slot);
1711 slot_printf(slot, "Spurious timeout - no active command\n");
1716 sdhci_set_transfer_mode(struct sdhci_slot *slot, const struct mmc_data *data) argument
1728 slot->ccb->mmcio.stop.opcode == MMC_STOP_TRANSMISSION &&
1730 slot->req->stop != NULL &&
1732 !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)))
1737 if (slot->flags & SDHCI_USE_DMA)
1740 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1744 sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) argument
1749 slot->curcmd = cmd;
1750 slot->cmd_done = 0;
1756 slot_printf(slot, "Unsupported response type!\n");
1758 sdhci_req_done(slot);
1766 if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) ||
1767 slot->power == 0 ||
1768 slot->clock == 0) {
1769 slot_printf(slot,
1771 slot->power, slot->clock);
1773 sdhci_req_done(slot);
1787 if (cmd == &slot->ccb->mmcio.stop ||
1789 if (cmd == slot->req->stop ||
1805 while (mask & RD4(slot, SDHCI_PRESENT_STATE)) {
1807 slot_printf(slot, "Controller never released "
1809 sdhci_dumpregs(slot);
1811 sdhci_req_done(slot);
1836 sdhci_start_data(slot, cmd->data);
1842 if (slot->data_done == 0) {
1843 WR4(slot, SDHCI_SIGNAL_ENABLE,
1844 slot->intmask &= ~SDHCI_INT_RESPONSE);
1847 WR4(slot, SDHCI_ARGUMENT, cmd->arg);
1849 sdhci_set_transfer_mode(slot, cmd->data);
1851 slot_printf(slot, "Starting command opcode %#04x flags %#04x\n",
1855 WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));
1857 callout_reset(&slot->timeout_callout, slot->timeout * hz,
1858 sdhci_timeout, slot);
1862 sdhci_finish_command(struct sdhci_slot *slot) argument
1869 slot_printf(slot, "%s: called, err %d flags %#04x\n",
1870 __func__, slot->curcmd->error, slot->curcmd->flags);
1871 slot->cmd_done = 1;
1877 if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK &&
1878 slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200))
1879 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |=
1882 if (slot->curcmd->error) {
1883 if (slot->curcmd->error == MMC_ERR_BADCRC)
1884 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
1885 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
1886 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
1887 sdhci_start(slot);
1891 if (slot->curcmd->flags & MMC_RSP_PRESENT) {
1892 if (slot->curcmd->flags & MMC_RSP_136) {
1896 val = RD4(slot, SDHCI_RESPONSE + i * 4);
1897 if (slot->quirks &
1899 slot->curcmd->resp[3 - i] = val;
1901 slot->curcmd->resp[3 - i] =
1907 slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE);
1910 slot_printf(slot, "Resp: %#04x %#04x %#04x %#04x\n",
1911 slot->curcmd->resp[0], slot->curcmd->resp[1],
1912 slot->curcmd->resp[2], slot->curcmd->resp[3]);
1915 if (slot->data_done)
1916 sdhci_start(slot);
1920 sdhci_start_data(struct sdhci_slot *slot, const struct mmc_data *data) argument
1925 if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
1926 slot->data_done = 1;
1930 slot->data_done = 0;
1934 if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) {
1939 current_timeout = (1 << 13) * 1000 / slot->timeout_clk;
1946 (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) {
1950 WR1(slot, SDHCI_TIMEOUT_CONTROL, div);
1956 if ((slot->opt & SDHCI_HAVE_DMA))
1957 slot->flags |= SDHCI_USE_DMA;
1959 if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) &&
1961 slot->flags &= ~SDHCI_USE_DMA;
1963 if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
1965 slot->flags &= ~SDHCI_USE_DMA;
1967 if (slot->flags & SDHCI_USE_DMA) {
1968 sdma_bbufsz = slot->sdma_bbufsz;
1970 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1973 memcpy(slot->dmamem, data->data, ulmin(data->len,
1975 bus_dmamap_sync(slot->dmatag, slot->dmamap,
1978 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
1984 slot->intmask &= ~SDHCI_INT_DMA_END;
1986 slot->intmask |= SDHCI_INT_DMA_END;
1987 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
1990 slot->offset = 0;
1994 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, data->block_size);
1997 slot_printf(slot, "SDIO Custom block params: blksz: "
2003 blksz = SDHCI_MAKE_BLKSZ(slot->sdma_boundary, ulmin(data->len, 512));
2007 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
2008 WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);
2010 slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n",
2015 sdhci_finish_data(struct sdhci_slot *slot) argument
2017 struct mmc_data *data = slot->curcmd->data;
2023 if (!slot->cmd_done) {
2024 WR4(slot, SDHCI_SIGNAL_ENABLE,
2025 slot->intmask |= SDHCI_INT_RESPONSE);
2028 if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) &&
2029 slot->curcmd->data != NULL) {
2031 left = data->len - slot->offset;
2032 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2034 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2035 ulmin(left, slot->sdma_bbufsz));
2037 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2040 slot->data_done = 1;
2042 if (slot->curcmd->error) {
2043 if (slot->curcmd->error == MMC_ERR_BADCRC)
2044 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2045 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2046 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2047 sdhci_start(slot);
2051 if (slot->cmd_done)
2052 sdhci_start(slot);
2057 sdhci_start(struct sdhci_slot *slot) argument
2062 ccb = slot->ccb;
2067 if (!(slot->flags & CMD_STARTED)) {
2068 slot->flags |= CMD_STARTED;
2069 sdhci_start_command(slot, &mmcio->cmd);
2085 slot_printf(slot, "result: %d\n", mmcio->cmd.error);
2087 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
2088 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2089 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2092 sdhci_req_done(slot);
2096 sdhci_start(struct sdhci_slot *slot) argument
2100 req = slot->req;
2104 if (!(slot->flags & CMD_STARTED)) {
2105 slot->flags |= CMD_STARTED;
2106 sdhci_start_command(slot, req->cmd);
2109 if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) &&
2110 !(slot->flags & STOP_STARTED) && req->stop) {
2111 slot->flags |= STOP_STARTED;
2112 sdhci_start_command(slot, req->stop);
2116 slot_printf(slot, "result: %d\n", req->cmd->error);
2118 ((slot->curcmd == req->stop &&
2119 (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) ||
2120 (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2121 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2122 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_DATA);
2125 sdhci_req_done(slot);
2133 struct sdhci_slot *slot = device_get_ivars(reqdev); local
2135 SDHCI_LOCK(slot);
2136 if (slot->req != NULL) {
2137 SDHCI_UNLOCK(slot);
2141 slot_printf(slot,
2147 slot->req = req;
2148 slot->flags = 0;
2149 sdhci_start(slot);
2150 SDHCI_UNLOCK(slot);
2152 while (slot->req != NULL) {
2153 sdhci_generic_intr(slot);
2163 struct sdhci_slot *slot = device_get_ivars(reqdev); local
2166 SDHCI_LOCK(slot);
2167 val = RD4(slot, SDHCI_PRESENT_STATE);
2168 SDHCI_UNLOCK(slot);
2175 struct sdhci_slot *slot = device_get_ivars(reqdev); local
2178 SDHCI_LOCK(slot);
2179 while (slot->bus_busy)
2180 msleep(slot, &slot->mtx, 0, "sdhciah", 0);
2181 slot->bus_busy++;
2183 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);
2184 SDHCI_UNLOCK(slot);
2191 struct sdhci_slot *slot = device_get_ivars(reqdev); local
2193 SDHCI_LOCK(slot);
2195 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);
2196 slot->bus_busy--;
2197 wakeup(slot);
2198 SDHCI_UNLOCK(slot);
2203 sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) argument
2206 if (!slot->curcmd) {
2207 slot_printf(slot, "Got command interrupt 0x%08x, but "
2209 sdhci_dumpregs(slot);
2213 slot->curcmd->error = MMC_ERR_TIMEOUT;
2215 slot->curcmd->error = MMC_ERR_BADCRC;
2217 slot->curcmd->error = MMC_ERR_FIFO;
2219 sdhci_finish_command(slot);
2223 sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) argument
2229 if (!slot->curcmd) {
2230 slot_printf(slot, "Got data interrupt 0x%08x, but "
2232 sdhci_dumpregs(slot);
2235 if (slot->curcmd->data == NULL &&
2236 (slot->curcmd->flags & MMC_RSP_BUSY) == 0) {
2237 slot_printf(slot, "Got data interrupt 0x%08x, but "
2240 sdhci_dumpregs(slot);
2244 slot->curcmd->error = MMC_ERR_TIMEOUT;
2246 slot->curcmd->error = MMC_ERR_BADCRC;
2247 if (slot->curcmd->data == NULL &&
2250 slot_printf(slot, "Got data interrupt 0x%08x, but "
2252 sdhci_dumpregs(slot);
2253 slot->curcmd->error = MMC_ERR_INVALID;
2255 if (slot->curcmd->error) {
2262 (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK ||
2263 slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) {
2264 slot->req->flags |= MMC_TUNE_DONE;
2265 sdhci_finish_command(slot);
2266 sdhci_finish_data(slot);
2271 if ((slot->opt & SDHCI_PLATFORM_TRANSFER) &&
2272 SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) {
2273 SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot,
2275 slot->flags |= PLATFORM_DATA_STARTED;
2277 sdhci_transfer_pio(slot);
2281 data = slot->curcmd->data;
2282 sdma_bbufsz = slot->sdma_bbufsz;
2285 left = data->len - slot->offset;
2287 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2289 memcpy((u_char*)data->data + slot->offset, slot->dmamem,
2292 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2296 slot->offset += sdma_bbufsz;
2297 left = data->len - slot->offset;
2299 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2302 memcpy(slot->dmamem, (u_char*)data->data + slot->offset,
2304 bus_dmamap_sync(slot->dmatag, slot->dmamap,
2312 slot->intmask &= ~SDHCI_INT_DMA_END;
2313 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2316 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr);
2320 if (slot->flags & PLATFORM_DATA_STARTED) {
2321 slot->flags &= ~PLATFORM_DATA_STARTED;
2322 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2324 sdhci_finish_data(slot);
2327 if (slot->curcmd != NULL && slot->curcmd->error != 0) {
2328 if (slot->flags & PLATFORM_DATA_STARTED) {
2329 slot->flags &= ~PLATFORM_DATA_STARTED;
2330 SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot);
2332 sdhci_finish_data(slot);
2337 sdhci_acmd_irq(struct sdhci_slot *slot, uint16_t acmd_err) argument
2340 if (!slot->curcmd) {
2341 slot_printf(slot, "Got AutoCMD12 error 0x%04x, but "
2343 sdhci_dumpregs(slot);
2346 slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", acmd_err);
2347 SDHCI_RESET(slot->bus, slot, SDHCI_RESET_CMD);
2351 sdhci_generic_intr(struct sdhci_slot *slot) argument
2356 SDHCI_LOCK(slot);
2358 intmask = RD4(slot, SDHCI_INT_STATUS);
2360 SDHCI_UNLOCK(slot);
2364 slot_printf(slot, "Interrupt %#x\n", intmask);
2368 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
2369 slot_printf(slot, "Tuning error indicated\n");
2370 slot->retune_req |= SDHCI_RETUNE_REQ_RESET;
2371 if (slot->curcmd) {
2372 slot->curcmd->error = MMC_ERR_BADCRC;
2373 sdhci_finish_command(slot);
2378 slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED;
2382 slot->intmask &=
2384 slot->intmask |= present ? SDHCI_INT_CARD_REMOVE :
2386 WR4(slot, SDHCI_INT_ENABLE, slot->intmask);
2387 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
2388 WR4(slot, SDHCI_INT_STATUS, intmask &
2390 sdhci_handle_card_present_locked(slot, present);
2394 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
2395 sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK);
2399 WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
2402 sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK);
2407 val16 = RD2(slot, SDHCI_ACMD12_ERR);
2408 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
2409 sdhci_acmd_irq(slot, val16);
2413 WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
2414 slot_printf(slot, "Card is consuming too much power!\n");
2421 WR4(slot, SDHCI_INT_STATUS, intmask);
2422 slot_printf(slot, "Unexpected interrupt 0x%08x.\n",
2424 sdhci_dumpregs(slot);
2427 SDHCI_UNLOCK(slot);
2434 const struct sdhci_slot *slot = device_get_ivars(child); local
2440 *result = slot->host.ios.bus_mode;
2443 *result = slot->host.ios.bus_width;
2446 *result = slot->host.ios.chip_select;
2449 *result = slot->host.ios.clock;
2452 *result = slot->host.f_min;
2455 *result = slot->host.f_max;
2458 *result = slot->host.host_ocr;
2461 *result = slot->host.mode;
2464 *result = slot->host.ocr;
2467 *result = slot->host.ios.power_mode;
2470 *result = slot->host.ios.vdd;
2473 if (slot->opt & SDHCI_TUNING_ENABLED) {
2474 if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) {
2478 if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) {
2486 *result = slot->host.ios.vccq;
2489 *result = slot->host.caps;
2492 *result = slot->host.ios.timing;
2499 if (slot->opt & SDHCI_TUNING_ENABLED &&
2500 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2501 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2521 struct sdhci_slot *slot = device_get_ivars(child); local
2526 slot_printf(slot, "%s: var=%d\n", __func__, which);
2531 slot->host.ios.bus_mode = value;
2534 slot->host.ios.bus_width = value;
2537 slot->host.ios.chip_select = value;
2541 max_clock = slot->max_clk;
2544 if (slot->version < SDHCI_SPEC_300) {
2560 slot->host.ios.clock = clock;
2562 slot->host.ios.clock = 0;
2565 slot->host.mode = value;
2568 slot->host.ocr = value;
2571 slot->host.ios.power_mode = value;
2574 slot->host.ios.vdd = value;
2577 slot->host.ios.vccq = value;
2580 slot->host.ios.timing = value;
2595 sdhci_start_slot(struct sdhci_slot *slot) argument
2598 if ((slot->devq = cam_simq_alloc(1)) == NULL)
2601 mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF);
2602 slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll,
2603 "sdhci_slot", slot, device_get_unit(slot->bus),
2604 &slot->sim_mtx, 1, 1, slot->devq);
2606 if (slot->sim == NULL) {
2607 cam_simq_free(slot->devq);
2608 slot_printf(slot, "cannot allocate CAM SIM\n");
2612 mtx_lock(&slot->sim_mtx);
2613 if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) {
2614 slot_printf(slot, "cannot register SCSI pass-through bus\n");
2615 cam_sim_free(slot->sim, FALSE);
2616 cam_simq_free(slot->devq);
2617 mtx_unlock(&slot->sim_mtx);
2620 mtx_unlock(&slot->sim_mtx);
2623 slot->card_present = 0;
2624 sdhci_card_task(slot, 0);
2628 if (slot->sim != NULL) {
2629 mtx_lock(&slot->sim_mtx);
2630 xpt_bus_deregister(cam_sim_path(slot->sim));
2631 cam_sim_free(slot->sim, FALSE);
2632 mtx_unlock(&slot->sim_mtx);
2635 if (slot->devq != NULL)
2636 cam_simq_free(slot->devq);
2642 struct sdhci_slot *slot; local
2644 slot = cam_sim_softc(sim);
2645 if (slot == NULL) {
2651 mtx_assert(&slot->sim_mtx, MA_OWNED);
2665 slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n");
2672 cts->proto_specific.mmc.host_ocr = slot->host.host_ocr;
2673 cts->proto_specific.mmc.host_f_min = slot->host.f_min;
2674 cts->proto_specific.mmc.host_f_max = slot->host.f_max;
2675 cts->proto_specific.mmc.host_caps = slot->host.caps;
2680 if (slot->opt & SDHCI_TUNING_ENABLED &&
2681 (slot->retune_mode == SDHCI_RETUNE_MODE_1 ||
2682 slot->retune_mode == SDHCI_RETUNE_MODE_2)) {
2689 memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios));
2696 slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n");
2697 sdhci_cam_settran_settings(slot, ccb);
2702 slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n");
2713 slot_printf(slot, "Got XPT_MMC_IO\n");
2733 sdhci_cam_get_possible_host_clock(const struct sdhci_slot *slot, argument
2740 max_clock = slot->max_clk;
2743 if (slot->version < SDHCI_SPEC_300) {
2760 sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) argument
2766 ios = &slot->host.ios;
2772 ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock);
2774 slot_printf(slot, "Clock => %d\n", ios->clock);
2779 slot_printf(slot, "VDD => %d\n", ios->vdd);
2784 slot_printf(slot, "CS => %d\n", ios->chip_select);
2789 slot_printf(slot, "Bus width => %d\n", ios->bus_width);
2794 slot_printf(slot, "Power mode => %d\n", ios->power_mode);
2799 slot_printf(slot, "Timing => %d\n", ios->timing);
2804 slot_printf(slot, "Bus mode => %d\n", ios->bus_mode);
2809 slot_printf(slot, "VCCQ => %d\n", ios->vccq);
2813 return (sdhci_cam_update_ios(slot));
2817 sdhci_cam_update_ios(struct sdhci_slot *slot) argument
2819 struct mmc_ios *ios = &slot->host.ios;
2822 slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n",
2824 SDHCI_LOCK(slot);
2827 WR4(slot, SDHCI_SIGNAL_ENABLE, 0);
2828 sdhci_init(slot);
2831 sdhci_set_clock(slot, ios->clock);
2832 sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd);
2834 slot->hostctrl |= SDHCI_CTRL_8BITBUS;
2835 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2837 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2838 slot->hostctrl |= SDHCI_CTRL_4BITBUS;
2840 slot->hostctrl &= ~SDHCI_CTRL_8BITBUS;
2841 slot->hostctrl &= ~SDHCI_CTRL_4BITBUS;
2846 !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT))
2847 slot->hostctrl |= SDHCI_CTRL_HISPD;
2849 slot->hostctrl &= ~SDHCI_CTRL_HISPD;
2850 WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);
2852 if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS)
2853 SDHCI_RESET(slot->bus, slot,
2856 SDHCI_UNLOCK(slot);
2861 sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) argument
2867 SDHCI_LOCK(slot);
2874 slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x "
2887 slot->ccb = ccb;
2888 slot->flags = 0;
2889 sdhci_start(slot);
2890 SDHCI_UNLOCK(slot);