56 #define	RD4	(sc->read)  macro
292 	if (RD4(sc, SDHCI_FSL_PRES_STATE) & SDHCI_FSL_PRES_SDSTB)  in sdhci_fsl_fdt_get_clock()
294 	if (RD4(sc, SDHCI_FSL_SYS_CTRL) & SDHCI_FSL_CLK_SDCLKEN)  in sdhci_fsl_fdt_get_clock()
322 	val32 = RD4(sc, SDHCI_CLOCK_CONTROL);  in fsl_sdhc_fdt_set_clock()
385 		wrk32 = RD4(sc, SDHCI_FSL_PROT_CTRL);  in sdhci_fsl_fdt_read_1()
399 	return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT8_MAX);  in sdhci_fsl_fdt_read_1()
414 		return (RD4(sc, SDHCI_FSL_HOST_VERSION) & UINT16_MAX);  in sdhci_fsl_fdt_read_2()
424 		val32 = RD4(sc, SDHCI_INT_STATUS);  in sdhci_fsl_fdt_read_2()
425 		val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE);  in sdhci_fsl_fdt_read_2()
428 		return ((RD4(sc, off & ~3) >> (off & 3) * 8) & UINT16_MAX);  in sdhci_fsl_fdt_read_2()
445 	val32 = RD4(sc, off);  in sdhci_fsl_fdt_read_4()
478 		val32 = RD4(sc, SDHCI_FSL_PROT_CTRL);  in sdhci_fsl_fdt_write_1()
497 		val32 = RD4(sc, off & ~3);  in sdhci_fsl_fdt_write_1()
540 		val32 = RD4(sc, off & ~3);  in sdhci_fsl_fdt_write_2()
705 	val_old = val = RD4(sc, SDHCI_FSL_PROT_CTRL);  in sdhci_fsl_fdt_switch_vccq()
852 	while ((RD4(sc, reg) & mask) != value) {  in sdhci_fsl_poll_register()
946 	sc->vendor_ver = (RD4(sc, SDHCI_FSL_HOST_VERSION) &  in sdhci_fsl_fdt_attach()
960 	val = RD4(sc, SDHCI_FSL_PROT_CTRL);  in sdhci_fsl_fdt_attach()
969 	val = RD4(sc, SDHCI_CLOCK_CONTROL);  in sdhci_fsl_fdt_attach()
971 	val = RD4(sc, SDHCI_FSL_ESDHC_CTRL);  in sdhci_fsl_fdt_attach()
1104 		val = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_fdt_reset()
1114 		val = RD4(sc, SDHCI_FSL_DLLCFG1);  in sdhci_fsl_fdt_reset()
1130 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_switch_tuning_block()
1156 	reg = RD4(sc, SDHCI_FSL_TBPTR);  in sdhci_fsl_sw_tuning()
1167 	reg = RD4(sc, SDHCI_FSL_AUTOCERR);  in sdhci_fsl_sw_tuning()
1174 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_sw_tuning()
1228 	reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);  in sdhci_fsl_fdt_tune()
1246 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_fdt_tune()
1264 	reg = RD4(sc, SDHCI_FSL_TBPTR);  in sdhci_fsl_fdt_tune()
1296 		reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);  in sdhci_fsl_fdt_tune()
1341 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_disable_hs400_mode()
1345 	reg = RD4(sc, SDHCI_FSL_SDTIMINGCTL);  in sdhci_fsl_disable_hs400_mode()
1349 	reg = RD4(sc, SDHCI_FSL_SDCLKCTL);  in sdhci_fsl_disable_hs400_mode()
1360 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_disable_hs400_mode()
1373 	reg = RD4(sc, SDHCI_FSL_DLLCFG0);  in sdhci_fsl_disable_hs400_mode()
1378 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_disable_hs400_mode()
1401 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_enable_hs400_mode()
1404 	reg = RD4(sc, SDHCI_FSL_SDCLKCTL);  in sdhci_fsl_enable_hs400_mode()
1416 	reg = RD4(sc, SDHCI_FSL_DLLCFG0);  in sdhci_fsl_enable_hs400_mode()
1435 	reg = RD4(sc, SDHCI_FSL_TBCTL);  in sdhci_fsl_enable_hs400_mode()
1447 	reg = RD4(sc, SDHCI_FSL_ESDHC_CTRL);  in sdhci_fsl_enable_hs400_mode()
1496 		reg = RD4(sc, SDHCI_FSL_AUTOCERR);  in sdhci_fsl_fdt_set_uhs_timing()