Lines Matching refs:MO
146 for (const MachineOperand &MO : MI.operands()) in MachineInstr() local
147 addOperand(MF, MO); in MachineInstr()
170 for (MachineOperand &MO : operands()) in RemoveRegOperandsFromUseLists()
171 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
172 MRI.removeRegOperandFromUseList(&MO); in RemoveRegOperandsFromUseLists()
179 for (MachineOperand &MO : operands()) in AddRegOperandsToUseLists()
180 if (MO.isReg()) in AddRegOperandsToUseLists()
181 MRI.addRegOperandToUseList(&MO); in AddRegOperandsToUseLists()
383 MachineMemOperand *MO) { in addMemOperand() argument
386 MMOs.push_back(MO); in addMemOperand()
623 const MachineOperand &MO = getOperand(i); in isIdenticalTo() local
625 if (!MO.isReg()) { in isIdenticalTo()
626 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
634 if (MO.isDef()) { in isIdenticalTo()
638 if (!Register::isVirtualRegister(MO.getReg()) || in isIdenticalTo()
640 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
643 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
645 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) in isIdenticalTo()
649 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
651 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) in isIdenticalTo()
691 for (const MachineOperand &MO : MI->operands()) { in eraseFromParentAndMarkDBGValuesForRemoval() local
692 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
694 Register Reg = MO.getReg(); in eraseFromParentAndMarkDBGValuesForRemoval()
732 const MachineOperand &MO = getOperand(I); in getNumExplicitOperands() local
738 if (MO.isReg() && MO.isImplicit()) in getNumExplicitOperands()
751 const MachineOperand &MO = getOperand(I); in getNumExplicitDefs() local
752 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in getNumExplicitDefs()
941 const MachineOperand &MO = getOperand(OpIdx); in getRegClassConstraintEffectForVRegImpl() local
942 if (!MO.isReg() || MO.getReg() != Reg) in getRegClassConstraintEffectForVRegImpl()
952 const MachineOperand &MO = getOperand(OpIdx); in getRegClassConstraintEffect() local
953 assert(MO.isReg() && in getRegClassConstraintEffect()
956 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect()
982 const MachineOperand &MO = getOperand(i); in hasRegisterImplicitUseOperand() local
983 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) in hasRegisterImplicitUseOperand()
995 const MachineOperand &MO = getOperand(i); in findRegisterUseOperandIdx() local
996 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
998 Register MOReg = MO.getReg(); in findRegisterUseOperandIdx()
1002 if (!isKill || MO.isKill()) in findRegisterUseOperandIdx()
1019 const MachineOperand &MO = getOperand(i); in readsWritesVirtualRegister() local
1020 if (!MO.isReg() || MO.getReg() != Reg) in readsWritesVirtualRegister()
1024 if (MO.isUse()) in readsWritesVirtualRegister()
1025 Use |= !MO.isUndef(); in readsWritesVirtualRegister()
1026 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister()
1045 const MachineOperand &MO = getOperand(i); in findRegisterDefOperandIdx() local
1048 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) in findRegisterDefOperandIdx()
1050 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1052 Register MOReg = MO.getReg(); in findRegisterDefOperandIdx()
1060 if (Found && (!isDead || MO.isDead())) in findRegisterDefOperandIdx()
1127 const MachineOperand &MO = getOperand(OpIdx); in findTiedOperandIdx() local
1128 assert(MO.isTied() && "Operand isn't tied"); in findTiedOperandIdx()
1131 if (MO.TiedTo < TiedMax) in findTiedOperandIdx()
1132 return MO.TiedTo - 1; in findTiedOperandIdx()
1137 if (MO.isUse()) in findTiedOperandIdx()
1203 for (MachineOperand &MO : operands()) { in clearKillInfo()
1204 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1205 MO.setIsKill(false); in clearKillInfo()
1215 for (MachineOperand &MO : operands()) { in substituteRegister()
1216 if (!MO.isReg() || MO.getReg() != FromReg) in substituteRegister()
1218 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1221 for (MachineOperand &MO : operands()) { in substituteRegister()
1222 if (!MO.isReg() || MO.getReg() != FromReg) in substituteRegister()
1224 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
1477 for (const MachineOperand &MO : operands()) { in allDefsAreDead() local
1478 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
1480 if (!MO.isDead()) in allDefsAreDead()
1492 const MachineOperand &MO = MI.getOperand(i); in copyImplicitOps() local
1493 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyImplicitOps()
1494 addOperand(MF, MO); in copyImplicitOps()
1557 for (const MachineOperand &MO : operands()) { in dumprImpl() local
1558 if (!MO.isReg() || MO.isDef()) in dumprImpl()
1560 Register Reg = MO.getReg(); in dumprImpl()
1612 const MachineOperand &MO = getOperand(OpIdx); in print() local
1613 if (MO.isReg() && MO.isTied() && !MO.isDef()) in print()
1622 const MachineOperand &MO = getOperand(StartOp); in print() local
1623 if (!MO.isReg() || !MO.isDef() || MO.isImplicit()) in print()
1631 MO.print(OS, MST, TypeToPrint, StartOp, /*PrintDef=*/false, IsStandalone, in print()
1714 const MachineOperand &MO = getOperand(i); in print() local
1719 if (isDebugValue() && MO.isMetadata()) { in print()
1721 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); in print()
1727 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, in print()
1730 } else if (isDebugLabel() && MO.isMetadata()) { in print()
1732 auto *DIL = dyn_cast<DILabel>(MO.getMetadata()); in print()
1738 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, in print()
1741 } else if (i == AsmDescOp && MO.isImm()) { in print()
1744 unsigned Flag = MO.getImm(); in print()
1773 if (MO.isImm() && isOperandSubregIdx(i)) in print()
1774 MachineOperand::printSubRegIdx(OS, MO.getImm(), TRI); in print()
1776 MO.print(OS, MST, TypeToPrint, i, /*PrintDef=*/true, IsStandalone, in print()
1887 MachineOperand &MO = getOperand(i); in addRegisterKilled() local
1888 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled()
1894 if (MO.isDebug()) in addRegisterKilled()
1897 Register Reg = MO.getReg(); in addRegisterKilled()
1903 if (MO.isKill()) in addRegisterKilled()
1909 MO.setIsKill(); in addRegisterKilled()
1912 } else if (hasAliases && MO.isKill() && Register::isPhysicalRegister(Reg)) { in addRegisterKilled()
1948 for (MachineOperand &MO : operands()) { in clearRegisterKills()
1949 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in clearRegisterKills()
1951 Register OpReg = MO.getReg(); in clearRegisterKills()
1953 MO.setIsKill(false); in clearRegisterKills()
1966 MachineOperand &MO = getOperand(i); in addRegisterDead() local
1967 if (!MO.isReg() || !MO.isDef()) in addRegisterDead()
1969 Register MOReg = MO.getReg(); in addRegisterDead()
1974 MO.setIsDead(); in addRegisterDead()
1976 } else if (hasAliases && MO.isDead() && in addRegisterDead()
2011 for (MachineOperand &MO : operands()) { in clearRegisterDeads()
2012 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads()
2014 MO.setIsDead(false); in clearRegisterDeads()
2019 for (MachineOperand &MO : operands()) { in setRegisterDefReadUndef()
2020 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) in setRegisterDefReadUndef()
2022 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
2029 MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo); in addRegisterDefined() local
2030 if (MO) in addRegisterDefined()
2033 for (const MachineOperand &MO : operands()) { in addRegisterDefined() local
2034 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && in addRegisterDefined()
2035 MO.getSubReg() == 0) in addRegisterDefined()
2047 for (MachineOperand &MO : operands()) { in setPhysRegsDeadExcept()
2048 if (MO.isRegMask()) { in setPhysRegsDeadExcept()
2052 if (!MO.isReg() || !MO.isDef()) continue; in setPhysRegsDeadExcept()
2053 Register Reg = MO.getReg(); in setPhysRegsDeadExcept()
2059 MO.setIsDead(); in setPhysRegsDeadExcept()
2075 for (const MachineOperand &MO : MI->operands()) { in getHashValue() local
2076 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg())) in getHashValue()
2079 HashComponents.push_back(hash_value(MO)); in getHashValue()
2124 const MachineOperand &MO, in BuildMI() argument
2130 if (MO.isReg()) in BuildMI()
2131 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr); in BuildMI()
2133 auto MIB = BuildMI(MF, DL, MCID).add(MO); in BuildMI()
2154 for (const MachineOperand &MO : MOs) in BuildMI() local
2155 if (MO.isReg()) in BuildMI()
2156 MIB.addReg(MO.getReg(), RegState::Debug); in BuildMI()
2158 MIB.add(MO); in BuildMI()
2176 bool IsIndirect, MachineOperand &MO, in BuildMI() argument
2179 MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr); in BuildMI()
2306 for (auto &MO : MRI->use_operands(DefReg)) { in changeDebugValuesDefReg() local
2307 auto *DI = MO.getParent(); in changeDebugValuesDefReg()