Lines Matching refs:SI
53 SI *target;
54 SI value;
57 SI *target;
70 SI value;
90 SI value[4];
91 void (*function)(SIM_CPU *, UINT, SI *);
98 SI address;
102 SI address;
106 SI address;
107 SI value;
110 SI address;
114 SI address;
118 SI address;
119 SI value[4];
122 SI address;
124 void (*function)(SIM_CPU *, IADDR, SI, QI);
127 SI address;
129 void (*function)(SIM_CPU *, IADDR, SI, HI);
132 SI address;
133 SI value;
134 void (*function)(SIM_CPU *, IADDR, SI, SI);
137 SI address;
139 void (*function)(SIM_CPU *, IADDR, SI, DI);
142 SI address;
144 void (*function)(SIM_CPU *, IADDR, SI, DF);
147 SI address;
148 SI value[4];
149 void (*function)(SIM_CPU *, IADDR, SI, SI *);
187 extern void sim_queue_si_write (SIM_CPU *, SI *, SI);
188 extern void sim_queue_sf_write (SIM_CPU *, SI *, SF);
197 extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *);
200 extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI);
201 extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI);
202 extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI);
203 extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI);
204 extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF);
205 extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *);
207 extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI);
208 extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI);
209 extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI);
210 extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI);
211 extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF);
212 extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *);