Lines Matching refs:per
22 // The processor may dispatch up to 6 macro ops per cycle
29 // The unit can receive up to 6 macro ops dispatched per cycle and track up
30 // to 256 macro ops in-flight in non-SMT mode or 128 per thread in SMT mode.
75 // The unit can receive up to 6 macro ops dispatched per cycle and track up to
76 // 256 macro ops in-flight in non-SMT mode or 128 per thread in SMT mode. <...>
77 // The retire unit handles in-order commit of up to eight macro ops per cycle.
162 6, // Max moves that can be eliminated per cycle.
167 // The schedulers can receive up to six macro ops per cycle, with a limit of
168 // two per scheduler. Each scheduler can issue one micro op per cycle into
300 // but throughput is limited to one per cycle.
340 6, // Max moves that can be eliminated per cycle.
346 // <...> the scheduler can issue 1 micro op per cycle for each pipe.
366 // enabling the execution of three 256-bit memory operations per cycle.