gas/doc/c-arm.texi

33 @table @code
35 @cindex @code{-mcpu=} command line option, ARM
41 @code{arm1},
42 @code{arm2},
43 @code{arm250},
44 @code{arm3},
45 @code{arm6},
46 @code{arm60},
47 @code{arm600},
48 @code{arm610},
49 @code{arm620},
50 @code{arm7},
51 @code{arm7m},
52 @code{arm7d},
53 @code{arm7dm},
54 @code{arm7di},
55 @code{arm7dmi},
56 @code{arm70},
57 @code{arm700},
58 @code{arm700i},
59 @code{arm710},
60 @code{arm710t},
61 @code{arm720},
62 @code{arm720t},
63 @code{arm740t},
64 @code{arm710c},
65 @code{arm7100},
66 @code{arm7500},
67 @code{arm7500fe},
68 @code{arm7t},
69 @code{arm7tdmi},
70 @code{arm7tdmi-s},
71 @code{arm8},
72 @code{arm810},
73 @code{strongarm},
74 @code{strongarm1},
75 @code{strongarm110},
76 @code{strongarm1100},
77 @code{strongarm1110},
78 @code{arm9},
79 @code{arm920},
80 @code{arm920t},
81 @code{arm922t},
82 @code{arm940t},
83 @code{arm9tdmi},
84 @code{arm9e},
85 @code{arm926e},
86 @code{arm926ej-s},
87 @code{arm946e-r0},
88 @code{arm946e},
89 @code{arm946e-s},
90 @code{arm966e-r0},
91 @code{arm966e},
92 @code{arm966e-s},
93 @code{arm968e-s},
94 @code{arm10t},
95 @code{arm10tdmi},
96 @code{arm10e},
97 @code{arm1020},
98 @code{arm1020t},
99 @code{arm1020e},
100 @code{arm1022e},
101 @code{arm1026ej-s},
102 @code{arm1136j-s},
103 @code{arm1136jf-s},
104 @code{arm1156t2-s},
105 @code{arm1156t2f-s},
106 @code{arm1176jz-s},
107 @code{arm1176jzf-s},
108 @code{mpcore},
109 @code{mpcorenovfp},
110 @code{cortex-a8},
111 @code{cortex-r4},
112 @code{cortex-m3},
113 @code{ep9312} (ARM920 with Cirrus Maverick coprocessor),
114 @code{i80200} (Intel XScale processor)
115 @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
117 @code{xscale}.
118 The special name @code{all} may be used to allow the
123 co-processor instruction space.  For example, @code{-mcpu=arm920+maverick}
124 is equivalent to specifying @code{-mcpu=ep9312}.  The following extensions
126 @code{+maverick}
127 @code{+iwmmxt}
129 @code{+xscale}.
131 @cindex @code{-march=} command line option, ARM
137 @code{armv1},
138 @code{armv2},
139 @code{armv2a},
140 @code{armv2s},
141 @code{armv3},
142 @code{armv3m},
143 @code{armv4},
144 @code{armv4xm},
145 @code{armv4t},
146 @code{armv4txm},
147 @code{armv5},
148 @code{armv5t},
149 @code{armv5txm},
150 @code{armv5te},
151 @code{armv5texp},
152 @code{armv6},
153 @code{armv6j},
154 @code{armv6k},
155 @code{armv6z},
156 @code{armv6zk},
157 @code{armv7},
158 @code{armv7a},
159 @code{armv7r},
160 @code{armv7m},
161 @code{iwmmxt}
163 @code{xscale}.
164 If both @code{-mcpu} and
165 @code{-march} are specified, the assembler will use
166 the setting for @code{-mcpu}.
169 extension options as the @code{-mcpu} option.
171 @cindex @code{-mfpu=} command line option, ARM
178 @code{softfpa},
179 @code{fpe},
180 @code{fpe2},
181 @code{fpe3},
182 @code{fpa},
183 @code{fpa10},
184 @code{fpa11},
185 @code{arm7500fe},
186 @code{softvfp},
187 @code{softvfp+vfp},
188 @code{vfp},
189 @code{vfp10},
190 @code{vfp10-r0},
191 @code{vfp9},
192 @code{vfpxd},
193 @code{arm1020t},
194 @code{arm1020e},
195 @code{arm1136jf-s}
197 @code{maverick}.
200 also affects the way in which the @code{.double} assembler directive behaves
201 when assembling little-endian code.
207 @cindex @code{-mthumb} command line option, ARM
211 @code{.code 16} directive.
213 @cindex @code{-mthumb-interwork} command line option, ARM
218 @cindex @code{-mapcs} command line option, ARM
219 @item -mapcs @code{[26|32]}
224 @cindex @code{-matpcs} command line option, ARM
232 @cindex @code{-mapcs-float} command line option, ARM
238 @cindex @code{-mapcs-reentrant} command line option, ARM
241 This variant supports position independent code.
243 @cindex @code{-mfloat-abi=} command line option, ARM
248 @code{soft},
249 @code{softfp}
251 @code{hard}.
253 @cindex @code{-eabi=} command line option, ARM
258 @code{gnu},
259 @code{4}
261 @code{5}.
263 @cindex @code{-EB} command line option, ARM
268 @cindex @code{-EL} command line option, ARM
273 @cindex @code{-k} command line option, ARM
274 @cindex PIC code generation for ARM
277 as position-independent code (PIC).
333 @table @code
335 @cindex @code{align} directive, ARM
342 @cindex @code{req} directive, ARM
351 @cindex @code{unreq} directive, ARM
354 @code{req} directive.  For example:
365 @cindex @code{code} directive, ARM
366 @item .code @code{[16|32]}
370 @cindex @code{thumb} directive, ARM
372 This performs the same action as @var{.code 16}.
374 @cindex @code{arm} directive, ARM
376 This performs the same action as @var{.code 32}.
378 @cindex @code{force_thumb} directive, ARM
383 @cindex @code{thumb_func} directive, ARM
387 the assembler and linker to generate correct code for interworking
390 directive also implies @code{.thumb}
392 @cindex @code{thumb_set} directive, ARM
394 This performs the equivalent of a @code{.set} directive in that it
398 way that the @code{.thumb_func} directive does.
400 @cindex @code{.ltorg} directive, ARM
405 @code{GAS} maintains a separate literal pool for each section and each
406 sub-section.  The @code{.ltorg} directive will only affect the literal
410 Note - older versions of @code{GAS} would dump the current literal
414 @cindex @code{.pool} directive, ARM
418 @cindex @code{.fnstart} directive, ARM
422 @cindex @code{.fnend} directive, ARM
431 @cindex @code{.cantunwind} directive, ARM
436 @cindex @code{.personality} directive, ARM
440 @cindex @code{.personalityindex} directive, ARM
445 @cindex @code{.handlerdata} directive, ARM
449 @code{.fnend} directive will be added to the exception table entry.
451 Must be preceded by a @code{.personality} or @code{.personalityindex}
454 @cindex @code{.save} directive, ARM
481 @cindex @code{.pad} directive, ARM
487 @cindex @code{.movsp} directive, ARM
491 @cindex @code{.setfp} directive, ARM
496 The syntax of this directive is the same as the @code{sub} or @code{mov}
498 @code{sp} or mentioned in a previous @code{.movsp} directive.
508 @cindex @code{.unwind_raw} directive, ARM
513 For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
514 @code{.save @{r0@}}
516 @cindex @code{.cpu} directive, ARM
521 @cindex @code{.arch} directive, ARM
526 @cindex @code{.fpu} directive, ARM
531 @cindex @code{.eabi_attribute} directive, ARM
534 is either a @code{number}, @code{"string"}, or @code{number, "string"}
544 @code{@value{AS}} implements all the standard ARM opcodes.  It also
548 @table @code
550 @cindex @code{NOP} pseudo op, ARM
559 @cindex @code{LDR reg,=<label>} pseudo op, ARM
571 @cindex @code{ADR reg,<label>} pseudo op, ARM
584 @cindex @code{ADRL reg,<label>} pseudo op, ARM
612 @table @code
614 @cindex @code{$a}
616 At the start of a region of code containing ARM instructions.
618 @cindex @code{$t}
620 At the start of a region of code containing THUMB instructions.
622 @cindex @code{$d}
629 is no need to code them yourself.  Support for tagging symbols ($b,