Lines Matching refs:dig
1211 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_audio_select_pin() local
1214 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_afmt_audio_select_pin()
1217 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_audio_select_pin()
1218 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); in dce_v10_0_afmt_audio_select_pin()
1219 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_audio_select_pin()
1228 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_latency_fields() local
1235 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_latency_fields()
1265 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_latency_fields()
1274 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_speaker_allocation() local
1282 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_speaker_allocation()
1306 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1319 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, in dce_v10_0_audio_write_speaker_allocation()
1330 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_write_sad_regs() local
1352 if (!dig || !dig->afmt || !dig->afmt->pin) in dce_v10_0_audio_write_sad_regs()
1405 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); in dce_v10_0_audio_write_sad_regs()
1485 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_ACR() local
1488 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1490 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1491 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1493 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1495 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1497 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1498 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1500 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1502 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1504 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1505 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1507 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
1520 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_update_avi_infoframe() local
1524 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1526 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1528 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1530 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, in dce_v10_0_afmt_update_avi_infoframe()
1539 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_audio_set_dto() local
1545 if (!dig || !dig->afmt) in dce_v10_0_audio_set_dto()
1570 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_setmode() local
1578 if (!dig || !dig->afmt) in dce_v10_0_afmt_setmode()
1582 if (!dig->afmt->enabled) in dce_v10_0_afmt_setmode()
1592 dig->afmt->pin = dce_v10_0_audio_get_pin(adev); in dce_v10_0_afmt_setmode()
1593 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_setmode()
1597 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1599 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ in dce_v10_0_afmt_setmode()
1601 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); in dce_v10_0_afmt_setmode()
1603 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1628 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1630 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1634 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1636 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1641 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1643 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1646 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1648 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1651 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1653 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ in dce_v10_0_afmt_setmode()
1655 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1660 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1662 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1665 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1667 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1676 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1680 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1682 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1684 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1686 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1688 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1695 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1699 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, in dce_v10_0_afmt_setmode()
1720 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1725 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1727 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1729 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1731 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); in dce_v10_0_afmt_setmode()
1734 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); in dce_v10_0_afmt_setmode()
1736 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); in dce_v10_0_afmt_setmode()
1737 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); in dce_v10_0_afmt_setmode()
1738 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1739 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
1742 dce_v10_0_audio_enable(adev, dig->afmt->pin, true); in dce_v10_0_afmt_setmode()
1750 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_afmt_enable() local
1752 if (!dig || !dig->afmt) in dce_v10_0_afmt_enable()
1756 if (enable && dig->afmt->enabled) in dce_v10_0_afmt_enable()
1758 if (!enable && !dig->afmt->enabled) in dce_v10_0_afmt_enable()
1761 if (!enable && dig->afmt->pin) { in dce_v10_0_afmt_enable()
1762 dce_v10_0_audio_enable(adev, dig->afmt->pin, false); in dce_v10_0_afmt_enable()
1763 dig->afmt->pin = NULL; in dce_v10_0_afmt_enable()
1766 dig->afmt->enabled = enable; in dce_v10_0_afmt_enable()
1769 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); in dce_v10_0_afmt_enable()
2191 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_pick_dig_encoder() local
2195 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2200 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
2205 if (dig->linkb) in dce_v10_0_pick_dig_encoder()
3366 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_prepare() local
3367 if (dig) { in dce_v10_0_encoder_prepare()
3368 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder); in dce_v10_0_encoder_prepare()
3370 dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; in dce_v10_0_encoder_prepare()
3408 struct amdgpu_encoder_atom_dig *dig; in dce_v10_0_encoder_disable() local
3415 dig = amdgpu_encoder->enc_priv; in dce_v10_0_encoder_disable()
3416 dig->dig_encoder = -1; in dce_v10_0_encoder_disable()