57 		      struct intel_crtc_state *pipe_config)  in g4x_dp_set_clock()  argument
79 			if (pipe_config->port_clock == divisor[i].dot) {  in g4x_dp_set_clock()
80 				pipe_config->dpll = divisor[i];  in g4x_dp_set_clock()
81 				pipe_config->clock_set = true;  in g4x_dp_set_clock()
89 			     const struct intel_crtc_state *pipe_config)  in intel_dp_prepare()  argument
94 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_prepare()
95 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_dp_prepare()
98 				 pipe_config->port_clock,  in intel_dp_prepare()
99 				 pipe_config->lane_count);  in intel_dp_prepare()
124 	intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);  in intel_dp_prepare()
144 			     pipe_config->enhanced_framing ?  in intel_dp_prepare()
147 		if (IS_G4X(dev_priv) && pipe_config->limited_color_range)  in intel_dp_prepare()
156 		if (pipe_config->enhanced_framing)  in intel_dp_prepare()
191 			   const struct intel_crtc_state *pipe_config)  in ilk_edp_pll_on()  argument
193 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in ilk_edp_pll_on()
196 	assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder);  in ilk_edp_pll_on()
201 		    pipe_config->port_clock);  in ilk_edp_pll_on()
205 	if (pipe_config->port_clock == 162000)  in ilk_edp_pll_on()
333 				struct intel_crtc_state *pipe_config)  in intel_dp_get_config()  argument
339 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_get_config()
342 		pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);  in intel_dp_get_config()
344 		pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);  in intel_dp_get_config()
348 	pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;  in intel_dp_get_config()
355 			pipe_config->enhanced_framing = true;  in intel_dp_get_config()
368 			pipe_config->enhanced_framing = true;  in intel_dp_get_config()
381 	pipe_config->hw.adjusted_mode.flags |= flags;  in intel_dp_get_config()
384 		pipe_config->limited_color_range = true;  in intel_dp_get_config()
386 	pipe_config->lane_count =  in intel_dp_get_config()
389 	g4x_dp_get_m_n(pipe_config);  in intel_dp_get_config()
393 			pipe_config->port_clock = 162000;  in intel_dp_get_config()
395 			pipe_config->port_clock = 270000;  in intel_dp_get_config()
398 	pipe_config->hw.adjusted_mode.crtc_clock =  in intel_dp_get_config()
399 		intel_dotclock_calculate(pipe_config->port_clock,  in intel_dp_get_config()
400 					 &pipe_config->dp_m_n);  in intel_dp_get_config()
403 		intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);  in intel_dp_get_config()
405 	intel_audio_codec_get_config(encoder, pipe_config);  in intel_dp_get_config()
643 			    const struct intel_crtc_state *pipe_config,  in intel_enable_dp()  argument
656 			vlv_pps_init(encoder, pipe_config);  in intel_enable_dp()
658 		intel_dp_enable_port(intel_dp, pipe_config);  in intel_enable_dp()
669 			lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);  in intel_enable_dp()
676 	intel_dp_configure_protocol_converter(intel_dp, pipe_config);  in intel_enable_dp()
678 	intel_dp_pcon_dsc_configure(intel_dp, pipe_config);  in intel_enable_dp()
679 	intel_dp_start_link_train(intel_dp, pipe_config);  in intel_enable_dp()
680 	intel_dp_stop_link_train(intel_dp, pipe_config);  in intel_enable_dp()
685 			  const struct intel_crtc_state *pipe_config,  in g4x_enable_dp()  argument
688 	intel_enable_dp(state, encoder, pipe_config, conn_state);  in g4x_enable_dp()
689 	intel_audio_codec_enable(encoder, pipe_config, conn_state);  in g4x_enable_dp()
690 	intel_edp_backlight_on(pipe_config, conn_state);  in g4x_enable_dp()
695 			  const struct intel_crtc_state *pipe_config,  in vlv_enable_dp()  argument
698 	intel_audio_codec_enable(encoder, pipe_config, conn_state);  in vlv_enable_dp()
699 	intel_edp_backlight_on(pipe_config, conn_state);  in vlv_enable_dp()
704 			      const struct intel_crtc_state *pipe_config,  in g4x_pre_enable_dp()  argument
710 	intel_dp_prepare(encoder, pipe_config);  in g4x_pre_enable_dp()
714 		ilk_edp_pll_on(intel_dp, pipe_config);  in g4x_pre_enable_dp()
719 			      const struct intel_crtc_state *pipe_config,  in vlv_pre_enable_dp()  argument
722 	vlv_phy_pre_encoder_enable(encoder, pipe_config);  in vlv_pre_enable_dp()
724 	intel_enable_dp(state, encoder, pipe_config, conn_state);  in vlv_pre_enable_dp()
729 				  const struct intel_crtc_state *pipe_config,  in vlv_dp_pre_pll_enable()  argument
732 	intel_dp_prepare(encoder, pipe_config);  in vlv_dp_pre_pll_enable()
734 	vlv_phy_pre_pll_enable(encoder, pipe_config);  in vlv_dp_pre_pll_enable()
739 			      const struct intel_crtc_state *pipe_config,  in chv_pre_enable_dp()  argument
742 	chv_phy_pre_encoder_enable(encoder, pipe_config);  in chv_pre_enable_dp()
744 	intel_enable_dp(state, encoder, pipe_config, conn_state);  in chv_pre_enable_dp()
752 				  const struct intel_crtc_state *pipe_config,  in chv_dp_pre_pll_enable()  argument
755 	intel_dp_prepare(encoder, pipe_config);  in chv_dp_pre_pll_enable()
757 	chv_phy_pre_pll_enable(encoder, pipe_config);  in chv_dp_pre_pll_enable()