Lines Matching refs:s
128 static void vbe_update_vgaregs(VGACommonState *s);
130 static inline bool vbe_enabled(VGACommonState *s) in vbe_enabled() argument
132 return s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED; in vbe_enabled()
135 static inline uint8_t sr(VGACommonState *s, int idx) in sr() argument
137 return vbe_enabled(s) ? s->sr_vbe[idx] : s->sr[idx]; in sr()
140 static void vga_update_memory_access(VGACommonState *s) in vga_update_memory_access() argument
144 if (s->legacy_address_space == NULL) { in vga_update_memory_access()
148 if (s->has_chain4_alias) { in vga_update_memory_access()
149 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias); in vga_update_memory_access()
150 object_unparent(OBJECT(&s->chain4_alias)); in vga_update_memory_access()
151 s->has_chain4_alias = false; in vga_update_memory_access()
152 s->plane_updated = 0xf; in vga_update_memory_access()
154 if ((sr(s, VGA_SEQ_PLANE_WRITE) & VGA_SR02_ALL_PLANES) == in vga_update_memory_access()
155 VGA_SR02_ALL_PLANES && sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { in vga_update_memory_access()
157 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) { in vga_update_memory_access()
165 offset = s->bank_offset; in vga_update_memory_access()
177 assert(offset + size <= s->vram_size); in vga_update_memory_access()
178 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram), in vga_update_memory_access()
179 "vga.chain4", &s->vram, offset, size); in vga_update_memory_access()
180 memory_region_add_subregion_overlap(s->legacy_address_space, base, in vga_update_memory_access()
181 &s->chain4_alias, 2); in vga_update_memory_access()
182 s->has_chain4_alias = true; in vga_update_memory_access()
186 static void vga_dumb_update_retrace_info(VGACommonState *s) in vga_dumb_update_retrace_info() argument
188 (void) s; in vga_dumb_update_retrace_info()
191 static void vga_precise_update_retrace_info(VGACommonState *s) in vga_precise_update_retrace_info() argument
210 struct vga_precise_retrace *r = &s->retrace_info.precise; in vga_precise_update_retrace_info()
212 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5; in vga_precise_update_retrace_info()
213 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START]; in vga_precise_update_retrace_info()
214 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3; in vga_precise_update_retrace_info()
215 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f; in vga_precise_update_retrace_info()
217 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] | in vga_precise_update_retrace_info()
218 (((s->cr[VGA_CRTC_OVERFLOW] & 1) | in vga_precise_update_retrace_info()
219 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2; in vga_precise_update_retrace_info()
220 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] | in vga_precise_update_retrace_info()
221 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) | in vga_precise_update_retrace_info()
222 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8); in vga_precise_update_retrace_info()
223 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf; in vga_precise_update_retrace_info()
225 clocking_mode = (sr(s, VGA_SEQ_CLOCK_MODE) >> 3) & 1; in vga_precise_update_retrace_info()
226 clock_sel = (s->msr >> 2) & 3; in vga_precise_update_retrace_info()
227 dots = (s->msr & 1) ? 8 : 9; in vga_precise_update_retrace_info()
248 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1; in vga_precise_update_retrace_info()
249 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1; in vga_precise_update_retrace_info()
283 static uint8_t vga_precise_retrace(VGACommonState *s) in vga_precise_retrace() argument
285 struct vga_precise_retrace *r = &s->retrace_info.precise; in vga_precise_retrace()
286 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE); in vga_precise_retrace()
308 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); in vga_precise_retrace()
312 static uint8_t vga_dumb_retrace(VGACommonState *s) in vga_dumb_retrace() argument
314 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE); in vga_dumb_retrace()
317 int vga_ioport_invalid(VGACommonState *s, uint32_t addr) in vga_ioport_invalid() argument
319 if (s->msr & VGA_MIS_COLOR) { in vga_ioport_invalid()
330 VGACommonState *s = opaque; in vga_ioport_read() local
333 if (vga_ioport_invalid(s, addr)) { in vga_ioport_read()
338 if (s->ar_flip_flop == 0) { in vga_ioport_read()
339 val = s->ar_index; in vga_ioport_read()
345 index = s->ar_index & 0x1f; in vga_ioport_read()
347 val = s->ar[index]; in vga_ioport_read()
353 val = s->st00; in vga_ioport_read()
356 val = s->sr_index; in vga_ioport_read()
359 val = s->sr[s->sr_index]; in vga_ioport_read()
361 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val); in vga_ioport_read()
365 val = s->dac_state; in vga_ioport_read()
368 val = s->dac_write_index; in vga_ioport_read()
371 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index]; in vga_ioport_read()
372 if (++s->dac_sub_index == 3) { in vga_ioport_read()
373 s->dac_sub_index = 0; in vga_ioport_read()
374 s->dac_read_index++; in vga_ioport_read()
378 val = s->fcr; in vga_ioport_read()
381 val = s->msr; in vga_ioport_read()
384 val = s->gr_index; in vga_ioport_read()
387 val = s->gr[s->gr_index]; in vga_ioport_read()
389 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val); in vga_ioport_read()
394 val = s->cr_index; in vga_ioport_read()
398 val = s->cr[s->cr_index]; in vga_ioport_read()
400 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val); in vga_ioport_read()
406 val = s->st01 = s->retrace(s); in vga_ioport_read()
407 s->ar_flip_flop = 0; in vga_ioport_read()
420 VGACommonState *s = opaque; in vga_ioport_write() local
424 if (vga_ioport_invalid(s, addr)) { in vga_ioport_write()
431 if (s->ar_flip_flop == 0) { in vga_ioport_write()
433 s->ar_index = val; in vga_ioport_write()
435 index = s->ar_index & 0x1f; in vga_ioport_write()
438 s->ar[index] = val & 0x3f; in vga_ioport_write()
441 s->ar[index] = val & ~0x10; in vga_ioport_write()
444 s->ar[index] = val; in vga_ioport_write()
447 s->ar[index] = val & ~0xc0; in vga_ioport_write()
450 s->ar[index] = val & ~0xf0; in vga_ioport_write()
453 s->ar[index] = val & ~0xf0; in vga_ioport_write()
459 s->ar_flip_flop ^= 1; in vga_ioport_write()
462 s->msr = val & ~0x10; in vga_ioport_write()
463 s->update_retrace_info(s); in vga_ioport_write()
466 s->sr_index = val & 7; in vga_ioport_write()
470 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val); in vga_ioport_write()
472 s->sr[s->sr_index] = val & sr_mask[s->sr_index]; in vga_ioport_write()
473 if (s->sr_index == VGA_SEQ_CLOCK_MODE) { in vga_ioport_write()
474 s->update_retrace_info(s); in vga_ioport_write()
476 vga_update_memory_access(s); in vga_ioport_write()
479 s->dac_read_index = val; in vga_ioport_write()
480 s->dac_sub_index = 0; in vga_ioport_write()
481 s->dac_state = 3; in vga_ioport_write()
484 s->dac_write_index = val; in vga_ioport_write()
485 s->dac_sub_index = 0; in vga_ioport_write()
486 s->dac_state = 0; in vga_ioport_write()
489 s->dac_cache[s->dac_sub_index] = val; in vga_ioport_write()
490 if (++s->dac_sub_index == 3) { in vga_ioport_write()
491 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3); in vga_ioport_write()
492 s->dac_sub_index = 0; in vga_ioport_write()
493 s->dac_write_index++; in vga_ioport_write()
497 s->gr_index = val & 0x0f; in vga_ioport_write()
501 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val); in vga_ioport_write()
503 s->gr[s->gr_index] = val & gr_mask[s->gr_index]; in vga_ioport_write()
504 vbe_update_vgaregs(s); in vga_ioport_write()
505 vga_update_memory_access(s); in vga_ioport_write()
509 s->cr_index = val; in vga_ioport_write()
514 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val); in vga_ioport_write()
517 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) && in vga_ioport_write()
518 s->cr_index <= VGA_CRTC_OVERFLOW) { in vga_ioport_write()
520 if (s->cr_index == VGA_CRTC_OVERFLOW) { in vga_ioport_write()
521 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) | in vga_ioport_write()
523 vbe_update_vgaregs(s); in vga_ioport_write()
527 s->cr[s->cr_index] = val; in vga_ioport_write()
528 vbe_update_vgaregs(s); in vga_ioport_write()
530 switch(s->cr_index) { in vga_ioport_write()
538 s->update_retrace_info(s); in vga_ioport_write()
544 s->fcr = val & 0x10; in vga_ioport_write()
556 static void vbe_fixup_regs(VGACommonState *s) in vbe_fixup_regs() argument
558 uint16_t *r = s->vbe_regs; in vbe_fixup_regs()
561 if (!vbe_enabled(s)) { in vbe_fixup_regs()
601 maxy = s->vbe_size / linelength; in vbe_fixup_regs()
621 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) { in vbe_fixup_regs()
624 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) { in vbe_fixup_regs()
632 s->vbe_line_offset = linelength; in vbe_fixup_regs()
633 s->vbe_start_addr = offset / 4; in vbe_fixup_regs()
637 static void vbe_update_vgaregs(VGACommonState *s) in vbe_update_vgaregs() argument
641 if (!vbe_enabled(s)) { in vbe_update_vgaregs()
647 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 | in vbe_update_vgaregs()
649 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */ in vbe_update_vgaregs()
650 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3; in vbe_update_vgaregs()
652 s->cr[VGA_CRTC_H_DISP] = in vbe_update_vgaregs()
653 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1; in vbe_update_vgaregs()
655 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1; in vbe_update_vgaregs()
656 s->cr[VGA_CRTC_V_DISP_END] = h; in vbe_update_vgaregs()
657 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) | in vbe_update_vgaregs()
660 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff; in vbe_update_vgaregs()
661 s->cr[VGA_CRTC_OVERFLOW] |= 0x10; in vbe_update_vgaregs()
662 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40; in vbe_update_vgaregs()
664 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) { in vbe_update_vgaregs()
666 s->sr_vbe[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */ in vbe_update_vgaregs()
670 s->sr_vbe[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M; in vbe_update_vgaregs()
672 s->sr_vbe[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES; in vbe_update_vgaregs()
674 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) | in vbe_update_vgaregs()
676 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */ in vbe_update_vgaregs()
681 VGACommonState *s = opaque; in vbe_ioport_read_index() local
682 return s->vbe_index; in vbe_ioport_read_index()
687 VGACommonState *s = opaque; in vbe_ioport_read_data() local
690 if (s->vbe_index < VBE_DISPI_INDEX_NB) { in vbe_ioport_read_data()
691 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) { in vbe_ioport_read_data()
692 switch(s->vbe_index) { in vbe_ioport_read_data()
704 val = s->vbe_regs[s->vbe_index]; in vbe_ioport_read_data()
708 val = s->vbe_regs[s->vbe_index]; in vbe_ioport_read_data()
710 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) { in vbe_ioport_read_data()
711 val = s->vbe_size / (64 * KiB); in vbe_ioport_read_data()
715 trace_vga_vbe_read(s->vbe_index, val); in vbe_ioport_read_data()
721 VGACommonState *s = opaque; in vbe_ioport_write_index() local
722 s->vbe_index = val; in vbe_ioport_write_index()
727 VGACommonState *s = opaque; in vbe_ioport_write_data() local
729 if (s->vbe_index <= VBE_DISPI_INDEX_NB) { in vbe_ioport_write_data()
730 trace_vga_vbe_write(s->vbe_index, val); in vbe_ioport_write_data()
731 switch(s->vbe_index) { in vbe_ioport_write_data()
739 s->vbe_regs[s->vbe_index] = val; in vbe_ioport_write_data()
748 s->vbe_regs[s->vbe_index] = val; in vbe_ioport_write_data()
749 vbe_fixup_regs(s); in vbe_ioport_write_data()
750 vbe_update_vgaregs(s); in vbe_ioport_write_data()
753 val &= s->vbe_bank_mask; in vbe_ioport_write_data()
754 s->vbe_regs[s->vbe_index] = val; in vbe_ioport_write_data()
755 s->bank_offset = (val << 16); in vbe_ioport_write_data()
756 vga_update_memory_access(s); in vbe_ioport_write_data()
760 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) { in vbe_ioport_write_data()
762 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0; in vbe_ioport_write_data()
763 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0; in vbe_ioport_write_data()
764 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0; in vbe_ioport_write_data()
765 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED; in vbe_ioport_write_data()
766 vbe_fixup_regs(s); in vbe_ioport_write_data()
767 vbe_update_vgaregs(s); in vbe_ioport_write_data()
771 memset(s->vram_ptr, 0, in vbe_ioport_write_data()
772 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset); in vbe_ioport_write_data()
775 s->bank_offset = 0; in vbe_ioport_write_data()
777 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0; in vbe_ioport_write_data()
778 s->vbe_regs[s->vbe_index] = val; in vbe_ioport_write_data()
779 vga_update_memory_access(s); in vbe_ioport_write_data()
788 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr) in vga_mem_readb() argument
794 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; in vga_mem_readb()
802 addr += s->bank_offset; in vga_mem_readb()
817 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { in vga_mem_readb()
821 } else if (s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) { in vga_mem_readb()
823 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1); in vga_mem_readb()
826 plane = s->gr[VGA_GFX_PLANE_READ]; in vga_mem_readb()
829 if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) { in vga_mem_readb()
834 if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) { in vga_mem_readb()
836 } else if ((s->gr[VGA_GFX_MODE] & VGA_GR05_HOST_ODD_EVEN) && in vga_mem_readb()
837 (s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) { in vga_mem_readb()
841 if (addr * sizeof(uint32_t) >= s->vram_size) { in vga_mem_readb()
845 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) { in vga_mem_readb()
849 return s->vram_ptr[(addr << 2) | plane]; in vga_mem_readb()
852 s->latch = ((uint32_t *)s->vram_ptr)[addr]; in vga_mem_readb()
853 if (!(s->gr[VGA_GFX_MODE] & 0x08)) { in vga_mem_readb()
855 ret = GET_PLANE(s->latch, plane); in vga_mem_readb()
858 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) & in vga_mem_readb()
859 mask16[s->gr[VGA_GFX_COMPARE_MASK]]; in vga_mem_readb()
869 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) in vga_mem_writeb() argument
879 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; in vga_mem_writeb()
887 addr += s->bank_offset; in vga_mem_writeb()
902 mask = sr(s, VGA_SEQ_PLANE_WRITE); in vga_mem_writeb()
903 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { in vga_mem_writeb()
909 if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0) { in vga_mem_writeb()
912 if (s->gr[VGA_GFX_MISC] & VGA_GR06_CHAIN_ODD_EVEN) { in vga_mem_writeb()
933 if (s->cr[VGA_CRTC_UNDERLINE] & VGA_CR14_DW) { in vga_mem_writeb()
935 } else if ((sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_SEQ_MODE) == 0 && in vga_mem_writeb()
936 (s->cr[VGA_CRTC_MODE] & VGA_CR17_WORD_BYTE) == 0) { in vga_mem_writeb()
940 if (addr * sizeof(uint32_t) >= s->vram_size) { in vga_mem_writeb()
944 if (sr(s, VGA_SEQ_MEMORY_MODE) & VGA_SR04_CHN_4M) { in vga_mem_writeb()
946 s->vram_ptr[(addr << 2) | plane] = val; in vga_mem_writeb()
950 s->plane_updated |= mask; /* only used to detect font change */ in vga_mem_writeb()
951 memory_region_set_dirty(&s->vram, addr, 1); in vga_mem_writeb()
957 write_mode = s->gr[VGA_GFX_MODE] & 3; in vga_mem_writeb()
962 b = s->gr[VGA_GFX_DATA_ROTATE] & 7; in vga_mem_writeb()
968 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]]; in vga_mem_writeb()
970 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask); in vga_mem_writeb()
971 bit_mask = s->gr[VGA_GFX_BIT_MASK]; in vga_mem_writeb()
974 val = s->latch; in vga_mem_writeb()
978 bit_mask = s->gr[VGA_GFX_BIT_MASK]; in vga_mem_writeb()
982 b = s->gr[VGA_GFX_DATA_ROTATE] & 7; in vga_mem_writeb()
985 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val; in vga_mem_writeb()
986 val = mask16[s->gr[VGA_GFX_SR_VALUE]]; in vga_mem_writeb()
991 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3; in vga_mem_writeb()
999 val &= s->latch; in vga_mem_writeb()
1003 val |= s->latch; in vga_mem_writeb()
1007 val ^= s->latch; in vga_mem_writeb()
1014 val = (val & bit_mask) | (s->latch & ~bit_mask); in vga_mem_writeb()
1018 s->plane_updated |= mask; /* only used to detect font change */ in vga_mem_writeb()
1020 ((uint32_t *)s->vram_ptr)[addr] = in vga_mem_writeb()
1021 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | in vga_mem_writeb()
1027 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); in vga_mem_writeb()
1037 static int update_palette16(VGACommonState *s) in update_palette16() argument
1043 palette = s->last_palette; in update_palette16()
1045 v = s->ar[i]; in update_palette16()
1046 if (s->ar[VGA_ATC_MODE] & 0x80) { in update_palette16()
1047 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf); in update_palette16()
1049 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f); in update_palette16()
1052 col = rgb_to_pixel32(c6_to_8(s->palette[v]), in update_palette16()
1053 c6_to_8(s->palette[v + 1]), in update_palette16()
1054 c6_to_8(s->palette[v + 2])); in update_palette16()
1064 static int update_palette256(VGACommonState *s) in update_palette256() argument
1070 palette = s->last_palette; in update_palette256()
1073 if (s->dac_8bit) { in update_palette256()
1074 col = rgb_to_pixel32(s->palette[v], in update_palette256()
1075 s->palette[v + 1], in update_palette256()
1076 s->palette[v + 2]); in update_palette256()
1078 col = rgb_to_pixel32(c6_to_8(s->palette[v]), in update_palette256()
1079 c6_to_8(s->palette[v + 1]), in update_palette256()
1080 c6_to_8(s->palette[v + 2])); in update_palette256()
1091 static void vga_get_params(VGACommonState *s, in vga_get_params() argument
1094 if (vbe_enabled(s)) { in vga_get_params()
1095 params->line_offset = s->vbe_line_offset; in vga_get_params()
1096 params->start_addr = s->vbe_start_addr; in vga_get_params()
1102 params->line_offset = s->cr[VGA_CRTC_OFFSET] << 3; in vga_get_params()
1105 params->start_addr = s->cr[VGA_CRTC_START_LO] | in vga_get_params()
1106 (s->cr[VGA_CRTC_START_HI] << 8); in vga_get_params()
1109 params->line_compare = s->cr[VGA_CRTC_LINE_COMPARE] | in vga_get_params()
1110 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) | in vga_get_params()
1111 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3); in vga_get_params()
1113 params->hpel = s->ar[VGA_ATC_PEL]; in vga_get_params()
1114 params->hpel_split = s->ar[VGA_ATC_MODE] & 0x20; in vga_get_params()
1119 static int update_basic_params(VGACommonState *s) in update_basic_params() argument
1126 s->get_params(s, ¤t); in update_basic_params()
1128 if (memcmp(¤t, &s->params, sizeof(current))) { in update_basic_params()
1129 s->params = current; in update_basic_params()
1155 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight, in vga_get_text_resolution() argument
1161 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; in vga_get_text_resolution()
1163 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) { in vga_get_text_resolution()
1166 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) { in vga_get_text_resolution()
1169 width = (s->cr[VGA_CRTC_H_DISP] + 1); in vga_get_text_resolution()
1170 if (s->cr[VGA_CRTC_V_TOTAL] == 100) { in vga_get_text_resolution()
1174 height = s->cr[VGA_CRTC_V_DISP_END] | in vga_get_text_resolution()
1175 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | in vga_get_text_resolution()
1176 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); in vga_get_text_resolution()
1194 static void vga_draw_text(VGACommonState *s, int full_update) in vga_draw_text() argument
1196 DisplaySurface *surface = qemu_console_surface(s->con); in vga_draw_text()
1208 v = sr(s, VGA_SEQ_CHARACTER_MAP); in vga_draw_text()
1210 if (offset != s->font_offsets[0]) { in vga_draw_text()
1211 s->font_offsets[0] = offset; in vga_draw_text()
1214 font_base[0] = s->vram_ptr + offset; in vga_draw_text()
1217 font_base[1] = s->vram_ptr + offset; in vga_draw_text()
1218 if (offset != s->font_offsets[1]) { in vga_draw_text()
1219 s->font_offsets[1] = offset; in vga_draw_text()
1222 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) { in vga_draw_text()
1225 s->plane_updated = 0; in vga_draw_text()
1228 full_update |= update_basic_params(s); in vga_draw_text()
1230 line_offset = s->params.line_offset; in vga_draw_text()
1232 vga_get_text_resolution(s, &width, &height, &cw, &cheight); in vga_draw_text()
1242 if (width != s->last_width || height != s->last_height || in vga_draw_text()
1243 cw != s->last_cw || cheight != s->last_ch || s->last_depth) { in vga_draw_text()
1244 s->last_scr_width = width * cw; in vga_draw_text()
1245 s->last_scr_height = height * cheight; in vga_draw_text()
1246 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height); in vga_draw_text()
1247 surface = qemu_console_surface(s->con); in vga_draw_text()
1248 dpy_text_resize(s->con, width, height); in vga_draw_text()
1249 s->last_depth = 0; in vga_draw_text()
1250 s->last_width = width; in vga_draw_text()
1251 s->last_height = height; in vga_draw_text()
1252 s->last_ch = cheight; in vga_draw_text()
1253 s->last_cw = cw; in vga_draw_text()
1256 full_update |= update_palette16(s); in vga_draw_text()
1257 palette = s->last_palette; in vga_draw_text()
1261 s->full_update_text = 1; in vga_draw_text()
1263 if (s->full_update_gfx) { in vga_draw_text()
1264 s->full_update_gfx = 0; in vga_draw_text()
1268 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | in vga_draw_text()
1269 s->cr[VGA_CRTC_CURSOR_LO]) - s->params.start_addr; in vga_draw_text()
1270 if (cursor_offset != s->cursor_offset || in vga_draw_text()
1271 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || in vga_draw_text()
1272 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) { in vga_draw_text()
1275 if (s->cursor_offset < CH_ATTR_SIZE) in vga_draw_text()
1276 s->last_ch_attr[s->cursor_offset] = -1; in vga_draw_text()
1278 s->last_ch_attr[cursor_offset] = -1; in vga_draw_text()
1279 s->cursor_offset = cursor_offset; in vga_draw_text()
1280 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; in vga_draw_text()
1281 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; in vga_draw_text()
1283 cursor_ptr = s->vram_ptr + (s->params.start_addr + cursor_offset) * 4; in vga_draw_text()
1284 if (now >= s->cursor_blink_time) { in vga_draw_text()
1285 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2; in vga_draw_text()
1286 s->cursor_visible_phase = !s->cursor_visible_phase; in vga_draw_text()
1291 ch_attr_ptr = s->last_ch_attr; in vga_draw_text()
1293 offset = s->params.start_addr * 4; in vga_draw_text()
1296 src = s->vram_ptr + offset; in vga_draw_text()
1300 if (src + sizeof(uint16_t) > s->vram_ptr + s->vram_size) { in vga_draw_text()
1330 (s->ar[VGA_ATC_MODE] & 0x04)) { in vga_draw_text()
1337 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) && in vga_draw_text()
1338 s->cursor_visible_phase) { in vga_draw_text()
1341 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f; in vga_draw_text()
1342 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f; in vga_draw_text()
1367 dpy_gfx_update(s->con, cx_min * cw, cy * cheight, in vga_draw_text()
1373 if (line < s->params.line_compare && line1 >= s->params.line_compare) { in vga_draw_text()
1415 static int vga_get_bpp(VGACommonState *s) in vga_get_bpp() argument
1419 if (vbe_enabled(s)) { in vga_get_bpp()
1420 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP]; in vga_get_bpp()
1427 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight) in vga_get_resolution() argument
1431 if (vbe_enabled(s)) { in vga_get_resolution()
1432 width = s->vbe_regs[VBE_DISPI_INDEX_XRES]; in vga_get_resolution()
1433 height = s->vbe_regs[VBE_DISPI_INDEX_YRES]; in vga_get_resolution()
1435 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8; in vga_get_resolution()
1436 height = s->cr[VGA_CRTC_V_DISP_END] | in vga_get_resolution()
1437 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | in vga_get_resolution()
1438 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); in vga_get_resolution()
1445 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2) in vga_invalidate_scanlines() argument
1453 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f); in vga_invalidate_scanlines()
1457 static bool vga_scanline_invalidated(VGACommonState *s, int y) in vga_scanline_invalidated() argument
1462 return s->invalidated_y_table[y >> 5] & (1 << (y & 0x1f)); in vga_scanline_invalidated()
1465 void vga_dirty_log_start(VGACommonState *s) in vga_dirty_log_start() argument
1467 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA); in vga_dirty_log_start()
1470 void vga_dirty_log_stop(VGACommonState *s) in vga_dirty_log_stop() argument
1472 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA); in vga_dirty_log_stop()
1478 static void vga_draw_graphic(VGACommonState *s, int full_update) in vga_draw_graphic() argument
1480 DisplaySurface *surface = qemu_console_surface(s->con); in vga_draw_graphic()
1493 bool byteswap = !s->big_endian_fb; in vga_draw_graphic()
1495 bool byteswap = s->big_endian_fb; in vga_draw_graphic()
1498 full_update |= update_basic_params(s); in vga_draw_graphic()
1500 s->get_resolution(s, &width, &height); in vga_draw_graphic()
1502 depth = s->get_bpp(s); in vga_draw_graphic()
1505 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3; in vga_draw_graphic()
1506 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7); in vga_draw_graphic()
1507 if (s->cr[VGA_CRTC_MODE] & 1) { in vga_draw_graphic()
1508 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan) in vga_draw_graphic()
1516 if (shift_control != s->shift_control || in vga_draw_graphic()
1517 double_scan != s->double_scan) { in vga_draw_graphic()
1519 s->shift_control = shift_control; in vga_draw_graphic()
1520 s->double_scan = double_scan; in vga_draw_graphic()
1524 full_update |= update_palette16(s); in vga_draw_graphic()
1525 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { in vga_draw_graphic()
1534 full_update |= update_palette16(s); in vga_draw_graphic()
1535 if (sr(s, VGA_SEQ_CLOCK_MODE) & 8) { in vga_draw_graphic()
1547 full_update |= update_palette256(s); in vga_draw_graphic()
1552 full_update |= update_palette256(s); in vga_draw_graphic()
1557 v = s->big_endian_fb ? VGA_DRAW_LINE15_BE : VGA_DRAW_LINE15_LE; in vga_draw_graphic()
1561 v = s->big_endian_fb ? VGA_DRAW_LINE16_BE : VGA_DRAW_LINE16_LE; in vga_draw_graphic()
1565 v = s->big_endian_fb ? VGA_DRAW_LINE24_BE : VGA_DRAW_LINE24_LE; in vga_draw_graphic()
1569 v = s->big_endian_fb ? VGA_DRAW_LINE32_BE : VGA_DRAW_LINE32_LE; in vga_draw_graphic()
1576 hpel = bits <= 8 ? s->params.hpel & 7 : 0; in vga_draw_graphic()
1582 region_start = (s->params.start_addr * 4); in vga_draw_graphic()
1583 region_end = region_start + (ram_addr_t)s->params.line_offset * (height - 1) + bwidth; in vga_draw_graphic()
1584 if (region_end > s->vbe_size) { in vga_draw_graphic()
1596 region_end = s->vbe_size; in vga_draw_graphic()
1599 if (s->params.line_compare < height) { in vga_draw_graphic()
1612 share_surface = dpy_gfx_check_format(s->con, format) in vga_draw_graphic()
1613 && !s->force_shadow && !force_shadow; in vga_draw_graphic()
1618 if (s->params.line_offset != s->last_line_offset || in vga_draw_graphic()
1619 disp_width != s->last_width || in vga_draw_graphic()
1620 height != s->last_height || in vga_draw_graphic()
1621 s->last_depth != depth || in vga_draw_graphic()
1622 s->last_byteswap != byteswap || in vga_draw_graphic()
1625 s->last_scr_width = disp_width; in vga_draw_graphic()
1626 s->last_scr_height = height; in vga_draw_graphic()
1627 s->last_width = disp_width; in vga_draw_graphic()
1628 s->last_height = height; in vga_draw_graphic()
1629 s->last_line_offset = s->params.line_offset; in vga_draw_graphic()
1630 s->last_depth = depth; in vga_draw_graphic()
1631 s->last_byteswap = byteswap; in vga_draw_graphic()
1633 s->panning_buf = g_realloc(s->panning_buf, in vga_draw_graphic()
1637 if (surface_data(surface) != s->vram_ptr + (s->params.start_addr * 4) in vga_draw_graphic()
1647 height, format, s->params.line_offset, in vga_draw_graphic()
1648 s->vram_ptr + (s->params.start_addr * 4)); in vga_draw_graphic()
1649 dpy_gfx_replace_surface(s->con, surface); in vga_draw_graphic()
1651 qemu_console_resize(s->con, disp_width, height); in vga_draw_graphic()
1652 surface = qemu_console_surface(s->con); in vga_draw_graphic()
1658 if (!is_buffer_shared(surface) && s->cursor_invalidate) { in vga_draw_graphic()
1659 s->cursor_invalidate(s); in vga_draw_graphic()
1664 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE], in vga_draw_graphic()
1665 s->params.line_compare, sr(s, VGA_SEQ_CLOCK_MODE)); in vga_draw_graphic()
1667 addr1 = (s->params.start_addr * 4); in vga_draw_graphic()
1674 snap = memory_region_snapshot_and_clear_dirty(&s->vram, region_start, in vga_draw_graphic()
1681 if (!(s->cr[VGA_CRTC_MODE] & 1)) { in vga_draw_graphic()
1684 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1); in vga_draw_graphic()
1687 if (!(s->cr[VGA_CRTC_MODE] & 2)) { in vga_draw_graphic()
1690 page0 = addr & s->vbe_size_mask; in vga_draw_graphic()
1691 page1 = (addr + bwidth - 1) & s->vbe_size_mask; in vga_draw_graphic()
1697 update = memory_region_snapshot_get_dirty(&s->vram, snap, in vga_draw_graphic()
1698 page0, s->vbe_size - page0); in vga_draw_graphic()
1699 update |= memory_region_snapshot_get_dirty(&s->vram, snap, in vga_draw_graphic()
1702 update = memory_region_snapshot_get_dirty(&s->vram, snap, in vga_draw_graphic()
1706 update |= vga_scanline_invalidated(s, y); in vga_draw_graphic()
1712 p = vga_draw_line(s, d, addr, width, hpel); in vga_draw_graphic()
1716 if (s->cursor_draw_line) in vga_draw_graphic()
1717 s->cursor_draw_line(s, d, y); in vga_draw_graphic()
1722 dpy_gfx_update(s->con, 0, y_start, in vga_draw_graphic()
1728 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3; in vga_draw_graphic()
1730 addr1 += s->params.line_offset; in vga_draw_graphic()
1737 if (y == s->params.line_compare) { in vga_draw_graphic()
1738 if (s->params.hpel_split) { in vga_draw_graphic()
1747 dpy_gfx_update(s->con, 0, y_start, in vga_draw_graphic()
1751 memset(s->invalidated_y_table, 0, sizeof(s->invalidated_y_table)); in vga_draw_graphic()
1754 static void vga_draw_blank(VGACommonState *s, int full_update) in vga_draw_blank() argument
1756 DisplaySurface *surface = qemu_console_surface(s->con); in vga_draw_blank()
1762 if (s->last_scr_width <= 0 || s->last_scr_height <= 0) in vga_draw_blank()
1765 w = s->last_scr_width * surface_bytes_per_pixel(surface); in vga_draw_blank()
1767 for(i = 0; i < s->last_scr_height; i++) { in vga_draw_blank()
1771 dpy_gfx_update_full(s->con); in vga_draw_blank()
1780 VGACommonState *s = opaque; in vga_update_display() local
1781 DisplaySurface *surface = qemu_console_surface(s->con); in vga_update_display()
1790 if (!(s->ar_index & 0x20)) { in vga_update_display()
1793 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; in vga_update_display()
1795 if (graphic_mode != s->graphic_mode) { in vga_update_display()
1796 s->graphic_mode = graphic_mode; in vga_update_display()
1797 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL); in vga_update_display()
1802 vga_draw_text(s, full_update); in vga_update_display()
1805 vga_draw_graphic(s, full_update); in vga_update_display()
1809 vga_draw_blank(s, full_update); in vga_update_display()
1818 VGACommonState *s = opaque; in vga_invalidate_display() local
1820 s->last_width = -1; in vga_invalidate_display()
1821 s->last_height = -1; in vga_invalidate_display()
1824 void vga_common_reset(VGACommonState *s) in vga_common_reset() argument
1826 s->sr_index = 0; in vga_common_reset()
1827 memset(s->sr, '\0', sizeof(s->sr)); in vga_common_reset()
1828 memset(s->sr_vbe, '\0', sizeof(s->sr_vbe)); in vga_common_reset()
1829 s->gr_index = 0; in vga_common_reset()
1830 memset(s->gr, '\0', sizeof(s->gr)); in vga_common_reset()
1831 s->ar_index = 0; in vga_common_reset()
1832 memset(s->ar, '\0', sizeof(s->ar)); in vga_common_reset()
1833 s->ar_flip_flop = 0; in vga_common_reset()
1834 s->cr_index = 0; in vga_common_reset()
1835 memset(s->cr, '\0', sizeof(s->cr)); in vga_common_reset()
1836 s->msr = 0; in vga_common_reset()
1837 s->fcr = 0; in vga_common_reset()
1838 s->st00 = 0; in vga_common_reset()
1839 s->st01 = 0; in vga_common_reset()
1840 s->dac_state = 0; in vga_common_reset()
1841 s->dac_sub_index = 0; in vga_common_reset()
1842 s->dac_read_index = 0; in vga_common_reset()
1843 s->dac_write_index = 0; in vga_common_reset()
1844 memset(s->dac_cache, '\0', sizeof(s->dac_cache)); in vga_common_reset()
1845 s->dac_8bit = 0; in vga_common_reset()
1846 memset(s->palette, '\0', sizeof(s->palette)); in vga_common_reset()
1847 s->bank_offset = 0; in vga_common_reset()
1848 s->vbe_index = 0; in vga_common_reset()
1849 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs)); in vga_common_reset()
1850 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5; in vga_common_reset()
1851 s->vbe_start_addr = 0; in vga_common_reset()
1852 s->vbe_line_offset = 0; in vga_common_reset()
1853 s->vbe_bank_mask = (s->vram_size >> 16) - 1; in vga_common_reset()
1854 memset(s->font_offsets, '\0', sizeof(s->font_offsets)); in vga_common_reset()
1855 s->graphic_mode = -1; /* force full update */ in vga_common_reset()
1856 s->shift_control = 0; in vga_common_reset()
1857 s->double_scan = 0; in vga_common_reset()
1858 memset(&s->params, '\0', sizeof(s->params)); in vga_common_reset()
1859 s->plane_updated = 0; in vga_common_reset()
1860 s->last_cw = 0; in vga_common_reset()
1861 s->last_ch = 0; in vga_common_reset()
1862 s->last_width = 0; in vga_common_reset()
1863 s->last_height = 0; in vga_common_reset()
1864 s->last_scr_width = 0; in vga_common_reset()
1865 s->last_scr_height = 0; in vga_common_reset()
1866 s->cursor_start = 0; in vga_common_reset()
1867 s->cursor_end = 0; in vga_common_reset()
1868 s->cursor_offset = 0; in vga_common_reset()
1869 s->big_endian_fb = s->default_endian_fb; in vga_common_reset()
1870 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table)); in vga_common_reset()
1871 memset(s->last_palette, '\0', sizeof(s->last_palette)); in vga_common_reset()
1872 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr)); in vga_common_reset()
1877 memset(&s->retrace_info, 0, sizeof (s->retrace_info)); in vga_common_reset()
1880 vga_update_memory_access(s); in vga_common_reset()
1885 VGACommonState *s = opaque; in vga_reset() local
1886 vga_common_reset(s); in vga_reset()
1897 VGACommonState *s = opaque; in vga_update_text() local
1907 if (!(s->ar_index & 0x20)) { in vga_update_text()
1910 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE; in vga_update_text()
1912 if (graphic_mode != s->graphic_mode) { in vga_update_text()
1913 s->graphic_mode = graphic_mode; in vga_update_text()
1916 if (s->last_width == -1) { in vga_update_text()
1917 s->last_width = 0; in vga_update_text()
1924 full_update |= update_basic_params(s); in vga_update_text()
1927 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1; in vga_update_text()
1929 if (!(sr(s, VGA_SEQ_CLOCK_MODE) & VGA_SR01_CHAR_CLK_8DOTS)) { in vga_update_text()
1932 if (sr(s, VGA_SEQ_CLOCK_MODE) & 0x08) { in vga_update_text()
1935 width = (s->cr[VGA_CRTC_H_DISP] + 1); in vga_update_text()
1936 if (s->cr[VGA_CRTC_V_TOTAL] == 100) { in vga_update_text()
1940 height = s->cr[VGA_CRTC_V_DISP_END] | in vga_update_text()
1941 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) | in vga_update_text()
1942 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3); in vga_update_text()
1956 if (width != s->last_width || height != s->last_height || in vga_update_text()
1957 cw != s->last_cw || cheight != s->last_ch) { in vga_update_text()
1958 s->last_scr_width = width * cw; in vga_update_text()
1959 s->last_scr_height = height * cheight; in vga_update_text()
1960 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height); in vga_update_text()
1961 dpy_text_resize(s->con, width, height); in vga_update_text()
1962 s->last_depth = 0; in vga_update_text()
1963 s->last_width = width; in vga_update_text()
1964 s->last_height = height; in vga_update_text()
1965 s->last_ch = cheight; in vga_update_text()
1966 s->last_cw = cw; in vga_update_text()
1971 s->full_update_gfx = 1; in vga_update_text()
1973 if (s->full_update_text) { in vga_update_text()
1974 s->full_update_text = 0; in vga_update_text()
1979 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | in vga_update_text()
1980 s->cr[VGA_CRTC_CURSOR_LO]) - s->params.start_addr; in vga_update_text()
1981 if (cursor_offset != s->cursor_offset || in vga_update_text()
1982 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start || in vga_update_text()
1983 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) { in vga_update_text()
1984 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20); in vga_update_text()
1986 dpy_text_cursor(s->con, in vga_update_text()
1990 dpy_text_cursor(s->con, -1, -1); in vga_update_text()
1991 s->cursor_offset = cursor_offset; in vga_update_text()
1992 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; in vga_update_text()
1993 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; in vga_update_text()
1996 src = (uint32_t *) s->vram_ptr + s->params.start_addr; in vga_update_text()
2003 dpy_text_update(s->con, 0, 0, width, height); in vga_update_text()
2026 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1); in vga_update_text()
2035 s->get_resolution(s, &width, &height); in vga_update_text()
2049 s->last_width = 60; in vga_update_text()
2050 s->last_height = height = 3; in vga_update_text()
2051 dpy_text_cursor(s->con, -1, -1); in vga_update_text()
2052 dpy_text_resize(s->con, s->last_width, height); in vga_update_text()
2054 for (dst = chardata, i = 0; i < s->last_width * height; i ++) in vga_update_text()
2058 width = (s->last_width - size) / 2; in vga_update_text()
2059 dst = chardata + s->last_width + width; in vga_update_text()
2064 dpy_text_update(s->con, 0, 0, s->last_width, height); in vga_update_text()
2070 VGACommonState *s = opaque; in vga_mem_read() local
2072 return vga_mem_readb(s, addr); in vga_mem_read()
2078 VGACommonState *s = opaque; in vga_mem_write() local
2080 vga_mem_writeb(s, addr, data); in vga_mem_write()
2095 VGACommonState *s = opaque; in vga_common_post_load() local
2098 s->graphic_mode = -1; in vga_common_post_load()
2099 vbe_update_vgaregs(s); in vga_common_post_load()
2100 vga_update_memory_access(s); in vga_common_post_load()
2106 VGACommonState *s = opaque; in vga_endian_state_needed() local
2113 return s->default_endian_fb != s->big_endian_fb; in vga_endian_state_needed()
2187 bool vga_common_init(VGACommonState *s, Object *obj, Error **errp) in vga_common_init() argument
2215 s->vram_size_mb = uint_clamp(s->vram_size_mb, 1, 512); in vga_common_init()
2216 s->vram_size_mb = pow2ceil(s->vram_size_mb); in vga_common_init()
2217 s->vram_size = s->vram_size_mb * MiB; in vga_common_init()
2219 if (!s->vbe_size) { in vga_common_init()
2220 s->vbe_size = s->vram_size; in vga_common_init()
2222 s->vbe_size_mask = s->vbe_size - 1; in vga_common_init()
2224 s->is_vbe_vmstate = 1; in vga_common_init()
2226 if (s->global_vmstate && qemu_ram_block_by_name("vga.vram")) { in vga_common_init()
2231 memory_region_init_ram_nomigrate(&s->vram, obj, "vga.vram", s->vram_size, in vga_common_init()
2237 vmstate_register_ram(&s->vram, s->global_vmstate ? NULL : DEVICE(obj)); in vga_common_init()
2238 xen_register_framebuffer(&s->vram); in vga_common_init()
2239 s->vram_ptr = memory_region_get_ram_ptr(&s->vram); in vga_common_init()
2240 s->get_bpp = vga_get_bpp; in vga_common_init()
2241 s->get_params = vga_get_params; in vga_common_init()
2242 s->get_resolution = vga_get_resolution; in vga_common_init()
2243 s->hw_ops = &vga_ops; in vga_common_init()
2246 s->retrace = vga_dumb_retrace; in vga_common_init()
2247 s->update_retrace_info = vga_dumb_update_retrace_info; in vga_common_init()
2251 s->retrace = vga_precise_retrace; in vga_common_init()
2252 s->update_retrace_info = vga_precise_update_retrace_info; in vga_common_init()
2261 s->default_endian_fb = target_words_bigendian(); in vga_common_init()
2263 vga_dirty_log_start(s); in vga_common_init()
2291 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj, in vga_init_io() argument
2311 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s, in vga_init_io()
2318 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space, in vga_init() argument
2324 qemu_register_reset(vga_reset, s); in vga_init()
2326 s->bank_offset = 0; in vga_init()
2328 s->legacy_address_space = address_space; in vga_init()
2330 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports); in vga_init()
2337 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga"); in vga_init()
2338 portio_list_set_flush_coalesced(&s->vga_port_list); in vga_init()
2339 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0); in vga_init()
2342 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe"); in vga_init()
2343 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce); in vga_init()