Lines Matching refs:s
61 static void omap_i2c_interrupts_update(OMAPI2CState *s) in omap_i2c_interrupts_update() argument
63 qemu_set_irq(s->irq, s->stat & s->mask); in omap_i2c_interrupts_update()
64 if ((s->dma >> 15) & 1) /* RDMA_EN */ in omap_i2c_interrupts_update()
65 qemu_set_irq(s->drq[0], (s->stat >> 3) & 1); /* RRDY */ in omap_i2c_interrupts_update()
66 if ((s->dma >> 7) & 1) /* XDMA_EN */ in omap_i2c_interrupts_update()
67 qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */ in omap_i2c_interrupts_update()
70 static void omap_i2c_fifo_run(OMAPI2CState *s) in omap_i2c_fifo_run() argument
74 if (!i2c_bus_busy(s->bus)) in omap_i2c_fifo_run()
77 if ((s->control >> 2) & 1) { /* RM */ in omap_i2c_fifo_run()
78 if ((s->control >> 1) & 1) { /* STP */ in omap_i2c_fifo_run()
79 i2c_end_transfer(s->bus); in omap_i2c_fifo_run()
80 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
81 s->count_cur = s->count; in omap_i2c_fifo_run()
82 s->txlen = 0; in omap_i2c_fifo_run()
83 } else if ((s->control >> 9) & 1) { /* TRX */ in omap_i2c_fifo_run()
84 while (ack && s->txlen) in omap_i2c_fifo_run()
85 ack = (i2c_send(s->bus, in omap_i2c_fifo_run()
86 (s->fifo >> ((-- s->txlen) << 3)) & in omap_i2c_fifo_run()
88 s->stat |= 1 << 4; /* XRDY */ in omap_i2c_fifo_run()
90 while (s->rxlen < 4) in omap_i2c_fifo_run()
91 s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3); in omap_i2c_fifo_run()
92 s->stat |= 1 << 3; /* RRDY */ in omap_i2c_fifo_run()
95 if ((s->control >> 9) & 1) { /* TRX */ in omap_i2c_fifo_run()
96 while (ack && s->count_cur && s->txlen) { in omap_i2c_fifo_run()
97 ack = (i2c_send(s->bus, in omap_i2c_fifo_run()
98 (s->fifo >> ((-- s->txlen) << 3)) & in omap_i2c_fifo_run()
100 s->count_cur --; in omap_i2c_fifo_run()
102 if (ack && s->count_cur) in omap_i2c_fifo_run()
103 s->stat |= 1 << 4; /* XRDY */ in omap_i2c_fifo_run()
105 s->stat &= ~(1 << 4); /* XRDY */ in omap_i2c_fifo_run()
106 if (!s->count_cur) { in omap_i2c_fifo_run()
107 s->stat |= 1 << 2; /* ARDY */ in omap_i2c_fifo_run()
108 s->control &= ~(1 << 10); /* MST */ in omap_i2c_fifo_run()
111 while (s->count_cur && s->rxlen < 4) { in omap_i2c_fifo_run()
112 s->fifo |= i2c_recv(s->bus) << ((s->rxlen ++) << 3); in omap_i2c_fifo_run()
113 s->count_cur --; in omap_i2c_fifo_run()
115 if (s->rxlen) in omap_i2c_fifo_run()
116 s->stat |= 1 << 3; /* RRDY */ in omap_i2c_fifo_run()
118 s->stat &= ~(1 << 3); /* RRDY */ in omap_i2c_fifo_run()
120 if (!s->count_cur) { in omap_i2c_fifo_run()
121 if ((s->control >> 1) & 1) { /* STP */ in omap_i2c_fifo_run()
122 i2c_end_transfer(s->bus); in omap_i2c_fifo_run()
123 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
124 s->count_cur = s->count; in omap_i2c_fifo_run()
125 s->txlen = 0; in omap_i2c_fifo_run()
127 s->stat |= 1 << 2; /* ARDY */ in omap_i2c_fifo_run()
128 s->control &= ~(1 << 10); /* MST */ in omap_i2c_fifo_run()
133 s->stat |= (!ack) << 1; /* NACK */ in omap_i2c_fifo_run()
135 s->control &= ~(1 << 1); /* STP */ in omap_i2c_fifo_run()
140 OMAPI2CState *s = OMAP_I2C(dev); in omap_i2c_reset() local
142 s->mask = 0; in omap_i2c_reset()
143 s->stat = 0; in omap_i2c_reset()
144 s->dma = 0; in omap_i2c_reset()
145 s->count = 0; in omap_i2c_reset()
146 s->count_cur = 0; in omap_i2c_reset()
147 s->fifo = 0; in omap_i2c_reset()
148 s->rxlen = 0; in omap_i2c_reset()
149 s->txlen = 0; in omap_i2c_reset()
150 s->control = 0; in omap_i2c_reset()
151 s->addr[0] = 0; in omap_i2c_reset()
152 s->addr[1] = 0; in omap_i2c_reset()
153 s->divider = 0; in omap_i2c_reset()
154 s->times[0] = 0; in omap_i2c_reset()
155 s->times[1] = 0; in omap_i2c_reset()
156 s->test = 0; in omap_i2c_reset()
161 OMAPI2CState *s = opaque; in omap_i2c_read() local
167 return s->revision; /* REV */ in omap_i2c_read()
170 return s->mask; in omap_i2c_read()
173 return s->stat | (i2c_bus_busy(s->bus) << 12); in omap_i2c_read()
176 if (s->revision >= OMAP2_INTR_REV) in omap_i2c_read()
178 ret = ctz32(s->stat & s->mask); in omap_i2c_read()
180 s->stat ^= 1 << ret; in omap_i2c_read()
185 omap_i2c_interrupts_update(s); in omap_i2c_read()
189 return (s->control >> 15) & 1; /* I2C_EN */ in omap_i2c_read()
192 return s->dma; in omap_i2c_read()
195 return s->count_cur; /* DCOUNT */ in omap_i2c_read()
199 if (s->control & (1 << 14)) { /* BE */ in omap_i2c_read()
200 ret |= ((s->fifo >> 0) & 0xff) << 8; in omap_i2c_read()
201 ret |= ((s->fifo >> 8) & 0xff) << 0; in omap_i2c_read()
203 ret |= ((s->fifo >> 8) & 0xff) << 8; in omap_i2c_read()
204 ret |= ((s->fifo >> 0) & 0xff) << 0; in omap_i2c_read()
206 if (s->rxlen == 1) { in omap_i2c_read()
207 s->stat |= 1 << 15; /* SBD */ in omap_i2c_read()
208 s->rxlen = 0; in omap_i2c_read()
209 } else if (s->rxlen > 1) { in omap_i2c_read()
210 if (s->rxlen > 2) in omap_i2c_read()
211 s->fifo >>= 16; in omap_i2c_read()
212 s->rxlen -= 2; in omap_i2c_read()
216 if (!s->rxlen) { in omap_i2c_read()
217 s->stat &= ~(1 << 3); /* RRDY */ in omap_i2c_read()
218 if (((s->control >> 10) & 1) && /* MST */ in omap_i2c_read()
219 ((~s->control >> 9) & 1)) { /* TRX */ in omap_i2c_read()
220 s->stat |= 1 << 2; /* ARDY */ in omap_i2c_read()
221 s->control &= ~(1 << 10); /* MST */ in omap_i2c_read()
224 s->stat &= ~(1 << 11); /* ROVR */ in omap_i2c_read()
225 omap_i2c_fifo_run(s); in omap_i2c_read()
226 omap_i2c_interrupts_update(s); in omap_i2c_read()
233 return s->control; in omap_i2c_read()
236 return s->addr[0]; in omap_i2c_read()
239 return s->addr[1]; in omap_i2c_read()
242 return s->divider; in omap_i2c_read()
245 return s->times[0]; in omap_i2c_read()
248 return s->times[1]; in omap_i2c_read()
251 if (s->test & (1 << 15)) { /* ST_EN */ in omap_i2c_read()
252 s->test ^= 0xa; in omap_i2c_read()
253 return s->test; in omap_i2c_read()
255 return s->test & ~0x300f; in omap_i2c_read()
265 OMAPI2CState *s = opaque; in omap_i2c_write() local
277 s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f); in omap_i2c_write()
281 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
287 s->stat &= ~(value & 0x27); in omap_i2c_write()
288 omap_i2c_interrupts_update(s); in omap_i2c_write()
292 s->dma = value & 0x8080; in omap_i2c_write()
294 s->mask &= ~(1 << 3); /* RRDY_IE */ in omap_i2c_write()
296 s->mask &= ~(1 << 4); /* XRDY_IE */ in omap_i2c_write()
300 s->count = value; /* DCOUNT */ in omap_i2c_write()
304 if (s->txlen > 2) { in omap_i2c_write()
308 s->fifo <<= 16; in omap_i2c_write()
309 s->txlen += 2; in omap_i2c_write()
310 if (s->control & (1 << 14)) { /* BE */ in omap_i2c_write()
311 s->fifo |= ((value >> 8) & 0xff) << 8; in omap_i2c_write()
312 s->fifo |= ((value >> 0) & 0xff) << 0; in omap_i2c_write()
314 s->fifo |= ((value >> 0) & 0xff) << 8; in omap_i2c_write()
315 s->fifo |= ((value >> 8) & 0xff) << 0; in omap_i2c_write()
317 s->stat &= ~(1 << 10); /* XUDF */ in omap_i2c_write()
318 if (s->txlen > 2) in omap_i2c_write()
319 s->stat &= ~(1 << 4); /* XRDY */ in omap_i2c_write()
320 omap_i2c_fifo_run(s); in omap_i2c_write()
321 omap_i2c_interrupts_update(s); in omap_i2c_write()
325 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
331 omap_i2c_reset(DEVICE(s)); in omap_i2c_write()
336 s->control = value & 0xcf87; in omap_i2c_write()
338 if (s->revision < OMAP2_INTR_REV) { in omap_i2c_write()
339 omap_i2c_reset(DEVICE(s)); in omap_i2c_write()
355 nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */ in omap_i2c_write()
357 s->stat |= nack << 1; /* NACK */ in omap_i2c_write()
358 s->control &= ~(1 << 0); /* STT */ in omap_i2c_write()
359 s->fifo = 0; in omap_i2c_write()
361 s->control &= ~(1 << 1); /* STP */ in omap_i2c_write()
363 s->count_cur = s->count; in omap_i2c_write()
364 omap_i2c_fifo_run(s); in omap_i2c_write()
366 omap_i2c_interrupts_update(s); in omap_i2c_write()
371 s->addr[0] = value & 0x3ff; in omap_i2c_write()
375 s->addr[1] = value & 0x3ff; in omap_i2c_write()
379 s->divider = value; in omap_i2c_write()
383 s->times[0] = value; in omap_i2c_write()
387 s->times[1] = value; in omap_i2c_write()
391 s->test = value & 0xf80f; in omap_i2c_write()
393 if (s->revision >= OMAP2_INTR_REV) { in omap_i2c_write()
394 s->stat |= 0x3f; in omap_i2c_write()
395 omap_i2c_interrupts_update(s); in omap_i2c_write()
412 OMAPI2CState *s = opaque; in omap_i2c_writeb() local
417 if (s->txlen > 2) { in omap_i2c_writeb()
421 s->fifo <<= 8; in omap_i2c_writeb()
422 s->txlen += 1; in omap_i2c_writeb()
423 s->fifo |= value & 0xff; in omap_i2c_writeb()
424 s->stat &= ~(1 << 10); /* XUDF */ in omap_i2c_writeb()
425 if (s->txlen > 2) in omap_i2c_writeb()
426 s->stat &= ~(1 << 4); /* XRDY */ in omap_i2c_writeb()
427 omap_i2c_fifo_run(s); in omap_i2c_writeb()
428 omap_i2c_interrupts_update(s); in omap_i2c_writeb()
476 OMAPI2CState *s = OMAP_I2C(obj); in omap_i2c_init() local
479 sysbus_init_irq(sbd, &s->irq); in omap_i2c_init()
480 sysbus_init_irq(sbd, &s->drq[0]); in omap_i2c_init()
481 sysbus_init_irq(sbd, &s->drq[1]); in omap_i2c_init()
482 sysbus_init_mmio(sbd, &s->iomem); in omap_i2c_init()
483 s->bus = i2c_init_bus(dev, NULL); in omap_i2c_init()
488 OMAPI2CState *s = OMAP_I2C(dev); in omap_i2c_realize() local
490 memory_region_init_io(&s->iomem, OBJECT(dev), &omap_i2c_ops, s, "omap.i2c", in omap_i2c_realize()
491 (s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000); in omap_i2c_realize()
493 if (!s->fclk) { in omap_i2c_realize()
497 if (s->revision >= OMAP2_INTR_REV && !s->iclk) { in omap_i2c_realize()
545 OMAPI2CState *s = OMAP_I2C(omap_i2c); in omap_i2c_bus() local
546 return s->bus; in omap_i2c_bus()