Lines Matching refs:d
79 Mioe3680PCIState *d = MIOe3680_PCI_DEV(dev); in mioe3680_pci_reset() local
83 can_sja_hardware_reset(&d->sja_state[i]); in mioe3680_pci_reset()
90 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja1_io_read() local
91 CanSJA1000State *s = &d->sja_state[0]; in mioe3680_pci_sja1_io_read()
103 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja1_io_write() local
104 CanSJA1000State *s = &d->sja_state[0]; in mioe3680_pci_sja1_io_write()
116 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja2_io_read() local
117 CanSJA1000State *s = &d->sja_state[1]; in mioe3680_pci_sja2_io_read()
129 Mioe3680PCIState *d = opaque; in mioe3680_pci_sja2_io_write() local
130 CanSJA1000State *s = &d->sja_state[1]; in mioe3680_pci_sja2_io_write()
159 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); in mioe3680_pci_realize() local
166 d->irq = pci_allocate_irq(&d->dev); in mioe3680_pci_realize()
169 can_sja_init(&d->sja_state[i], d->irq); in mioe3680_pci_realize()
173 if (can_sja_connect_to_bus(&d->sja_state[i], d->canbus[i]) < 0) { in mioe3680_pci_realize()
179 memory_region_init_io(&d->sja_io[0], OBJECT(d), &mioe3680_pci_sja1_io_ops, in mioe3680_pci_realize()
180 d, "mioe3680_pci-sja1", MIOe3680_PCI_SJA_RANGE); in mioe3680_pci_realize()
181 memory_region_init_io(&d->sja_io[1], OBJECT(d), &mioe3680_pci_sja2_io_ops, in mioe3680_pci_realize()
182 d, "mioe3680_pci-sja2", MIOe3680_PCI_SJA_RANGE); in mioe3680_pci_realize()
185 pci_register_bar(&d->dev, /*BAR*/ i, PCI_BASE_ADDRESS_SPACE_IO, in mioe3680_pci_realize()
186 &d->sja_io[i]); in mioe3680_pci_realize()
192 Mioe3680PCIState *d = MIOe3680_PCI_DEV(pci_dev); in mioe3680_pci_exit() local
196 can_sja_disconnect(&d->sja_state[i]); in mioe3680_pci_exit()
199 qemu_free_irq(d->irq); in mioe3680_pci_exit()
218 Mioe3680PCIState *d = MIOe3680_PCI_DEV(obj); in mioe3680_pci_instance_init() local
221 (Object **)&d->canbus[0], in mioe3680_pci_instance_init()
225 (Object **)&d->canbus[1], in mioe3680_pci_instance_init()