128 static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,  in sdram_bank_set_bcr()  argument
134     bank->bcr = bcr;  in sdram_bank_set_bcr()
137     if (enabled && (bcr & 1)) {  in sdram_bank_set_bcr()
153     uint32_t bcr;  in sdram_ddr_bcr()  local
157         bcr = 0;  in sdram_ddr_bcr()
160         bcr = 0x20000;  in sdram_ddr_bcr()
163         bcr = 0x40000;  in sdram_ddr_bcr()
166         bcr = 0x60000;  in sdram_ddr_bcr()
169         bcr = 0x80000;  in sdram_ddr_bcr()
172         bcr = 0xA0000;  in sdram_ddr_bcr()
175         bcr = 0xC0000;  in sdram_ddr_bcr()
183     bcr |= ram_base & 0xFF800000;  in sdram_ddr_bcr()
184     bcr |= 1;  in sdram_ddr_bcr()
186     return bcr;  in sdram_ddr_bcr()
189 static inline hwaddr sdram_ddr_base(uint32_t bcr)  in sdram_ddr_base()  argument
191     return bcr & 0xFF800000;  in sdram_ddr_base()
194 static hwaddr sdram_ddr_size(uint32_t bcr)  in sdram_ddr_size()  argument
196     int sh = (bcr >> 17) & 0x7;  in sdram_ddr_size()
238             ret = s->bank[0].bcr;  in sdram_ddr_dcr_read()
241             ret = s->bank[1].bcr;  in sdram_ddr_dcr_read()
244             ret = s->bank[2].bcr;  in sdram_ddr_dcr_read()
247             ret = s->bank[3].bcr;  in sdram_ddr_dcr_read()
299                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr_dcr_write()
310                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr_dcr_write()
409             s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);  in ppc4xx_sdram_ddr_realize()
410             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in ppc4xx_sdram_ddr_realize()
415         trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),  in ppc4xx_sdram_ddr_realize()
416                                 sdram_ddr_size(s->bank[i].bcr),  in ppc4xx_sdram_ddr_realize()
417                                 s->bank[i].bcr);  in ppc4xx_sdram_ddr_realize()
470     uint32_t bcr;  in sdram_ddr2_bcr()  local
474         bcr = 0xffc0;  in sdram_ddr2_bcr()
477         bcr = 0xff80;  in sdram_ddr2_bcr()
480         bcr = 0xff00;  in sdram_ddr2_bcr()
483         bcr = 0xfe00;  in sdram_ddr2_bcr()
486         bcr = 0xfc00;  in sdram_ddr2_bcr()
489         bcr = 0xf800;  in sdram_ddr2_bcr()
492         bcr = 0xf000;  in sdram_ddr2_bcr()
495         bcr = 0xe000;  in sdram_ddr2_bcr()
498         bcr = 0xc000;  in sdram_ddr2_bcr()
501         bcr = 0x8000;  in sdram_ddr2_bcr()
507     bcr |= ram_base >> 2 & 0xffe00000;  in sdram_ddr2_bcr()
508     bcr |= 1;  in sdram_ddr2_bcr()
510     return bcr;  in sdram_ddr2_bcr()
513 static inline hwaddr sdram_ddr2_base(uint32_t bcr)  in sdram_ddr2_base()  argument
515     return (bcr & 0xffe00000) << 2;  in sdram_ddr2_base()
518 static hwaddr sdram_ddr2_size(uint32_t bcr)  in sdram_ddr2_size()  argument
522     sh = 1024 - ((bcr >> 6) & 0x3ff);  in sdram_ddr2_size()
611                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr2_dcr_write()
623                         sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in sdram_ddr2_dcr_write()
676             s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);  in ppc4xx_sdram_ddr2_realize()
677             s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;  in ppc4xx_sdram_ddr2_realize()
678             sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,  in ppc4xx_sdram_ddr2_realize()
683         trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),  in ppc4xx_sdram_ddr2_realize()
684                                 sdram_ddr2_size(s->bank[i].bcr),  in ppc4xx_sdram_ddr2_realize()
685                                 s->bank[i].bcr);  in ppc4xx_sdram_ddr2_realize()