arm/tcg/cpu32.c

310       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
312       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
370       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
373       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
375       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
377       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
379       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
381       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
448       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
550       .access = PL1_RW, .type = ARM_CP_CONST },
552       .access = PL1_RW, .type = ARM_CP_CONST },
554       .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
589       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
592       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
595       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
598       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
601       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
604       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
607       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
610       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
613       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
616       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
619       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
622       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
625       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
628       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
631       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
634       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
637       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
640       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
643       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
646       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
649       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
652       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
655       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
658       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
661       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
664       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
667       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
670       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
673       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
676       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
679       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
682       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
685       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },
688       .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 },