Lines Matching refs:cpu
60 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a35_initfn() local
62 cpu->dtb_compatible = "arm,cortex-a35"; in aarch64_a35_initfn()
63 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a35_initfn()
64 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a35_initfn()
65 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a35_initfn()
66 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a35_initfn()
67 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a35_initfn()
68 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a35_initfn()
69 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a35_initfn()
70 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a35_initfn()
71 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a35_initfn()
74 cpu->midr = 0x411fd040; in aarch64_a35_initfn()
75 cpu->revidr = 0; in aarch64_a35_initfn()
76 cpu->ctr = 0x84448004; in aarch64_a35_initfn()
77 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a35_initfn()
78 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a35_initfn()
79 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a35_initfn()
80 cpu->id_afr0 = 0; in aarch64_a35_initfn()
81 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a35_initfn()
82 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a35_initfn()
83 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a35_initfn()
84 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a35_initfn()
85 cpu->isar.id_isar0 = 0x02101110; in aarch64_a35_initfn()
86 cpu->isar.id_isar1 = 0x13112111; in aarch64_a35_initfn()
87 cpu->isar.id_isar2 = 0x21232042; in aarch64_a35_initfn()
88 cpu->isar.id_isar3 = 0x01112131; in aarch64_a35_initfn()
89 cpu->isar.id_isar4 = 0x00011142; in aarch64_a35_initfn()
90 cpu->isar.id_isar5 = 0x00011121; in aarch64_a35_initfn()
91 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a35_initfn()
92 cpu->isar.id_aa64pfr1 = 0; in aarch64_a35_initfn()
93 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a35_initfn()
94 cpu->isar.id_aa64dfr1 = 0; in aarch64_a35_initfn()
95 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a35_initfn()
96 cpu->isar.id_aa64isar1 = 0; in aarch64_a35_initfn()
97 cpu->isar.id_aa64mmfr0 = 0x00101122; in aarch64_a35_initfn()
98 cpu->isar.id_aa64mmfr1 = 0; in aarch64_a35_initfn()
99 cpu->clidr = 0x0a200023; in aarch64_a35_initfn()
100 cpu->dcz_blocksize = 4; in aarch64_a35_initfn()
103 cpu->reset_sctlr = 0x00c50838; in aarch64_a35_initfn()
106 cpu->isar.reset_pmcr_el0 = 0x410a3000; in aarch64_a35_initfn()
109 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ in aarch64_a35_initfn()
110 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ in aarch64_a35_initfn()
111 cpu->ccsidr[2] = 0x703fe03a; /* 512KB L2 cache */ in aarch64_a35_initfn()
114 cpu->gic_num_lrs = 4; in aarch64_a35_initfn()
115 cpu->gic_vpribits = 5; in aarch64_a35_initfn()
116 cpu->gic_vprebits = 5; in aarch64_a35_initfn()
117 cpu->gic_pribits = 5; in aarch64_a35_initfn()
120 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a35_initfn()
122 cpu->isar.dbgdevid = 0x00110f13; in aarch64_a35_initfn()
124 cpu->isar.dbgdevid1 = 0x2; in aarch64_a35_initfn()
128 cpu->reset_fpsid = 0x41034043; in aarch64_a35_initfn()
131 cpu->isar.mvfr0 = 0x10110222; in aarch64_a35_initfn()
132 cpu->isar.mvfr1 = 0x12111111; in aarch64_a35_initfn()
133 cpu->isar.mvfr2 = 0x00000043; in aarch64_a35_initfn()
136 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a35_initfn()
142 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_get_sve_max_vq() local
146 if (!cpu_isar_feature(aa64_sve, cpu)) { in cpu_max_get_sve_max_vq()
149 value = cpu->sve_max_vq; in cpu_max_get_sve_max_vq()
157 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_set_sve_max_vq() local
171 cpu->sve_max_vq = max_vq; in cpu_max_set_sve_max_vq()
176 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_get_rme() local
177 return cpu_isar_feature(aa64_rme, cpu); in cpu_arm_get_rme()
182 ARMCPU *cpu = ARM_CPU(obj); in cpu_arm_set_rme() local
185 t = cpu->isar.id_aa64pfr0; in cpu_arm_set_rme()
187 cpu->isar.id_aa64pfr0 = t; in cpu_arm_set_rme()
193 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_set_l0gptsz() local
206 cpu->reset_l0gptsz = value - 30; in cpu_max_set_l0gptsz()
218 ARMCPU *cpu = ARM_CPU(obj); in cpu_max_get_l0gptsz() local
219 uint32_t value = cpu->reset_l0gptsz + 30; in cpu_max_get_l0gptsz()
229 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a55_initfn() local
231 cpu->dtb_compatible = "arm,cortex-a55"; in aarch64_a55_initfn()
232 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a55_initfn()
233 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a55_initfn()
234 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a55_initfn()
235 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a55_initfn()
236 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a55_initfn()
237 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a55_initfn()
238 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a55_initfn()
239 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a55_initfn()
240 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a55_initfn()
243 cpu->clidr = 0x82000023; in aarch64_a55_initfn()
244 cpu->ctr = 0x84448004; /* L1Ip = VIPT */ in aarch64_a55_initfn()
245 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a55_initfn()
246 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a55_initfn()
247 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a55_initfn()
248 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a55_initfn()
249 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a55_initfn()
250 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a55_initfn()
251 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a55_initfn()
252 cpu->isar.id_aa64pfr0 = 0x0000000010112222ull; in aarch64_a55_initfn()
253 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a55_initfn()
254 cpu->id_afr0 = 0x00000000; in aarch64_a55_initfn()
255 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a55_initfn()
256 cpu->isar.id_isar0 = 0x02101110; in aarch64_a55_initfn()
257 cpu->isar.id_isar1 = 0x13112111; in aarch64_a55_initfn()
258 cpu->isar.id_isar2 = 0x21232042; in aarch64_a55_initfn()
259 cpu->isar.id_isar3 = 0x01112131; in aarch64_a55_initfn()
260 cpu->isar.id_isar4 = 0x00011142; in aarch64_a55_initfn()
261 cpu->isar.id_isar5 = 0x01011121; in aarch64_a55_initfn()
262 cpu->isar.id_isar6 = 0x00000010; in aarch64_a55_initfn()
263 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a55_initfn()
264 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a55_initfn()
265 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a55_initfn()
266 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a55_initfn()
267 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a55_initfn()
268 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a55_initfn()
269 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a55_initfn()
270 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a55_initfn()
271 cpu->midr = 0x412FD050; /* r2p0 */ in aarch64_a55_initfn()
272 cpu->revidr = 0; in aarch64_a55_initfn()
275 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */ in aarch64_a55_initfn()
276 cpu->ccsidr[1] = 0x200fe01a; /* 32KB L1 icache */ in aarch64_a55_initfn()
277 cpu->ccsidr[2] = 0x703fe07a; /* 512KB L2 cache */ in aarch64_a55_initfn()
280 cpu->reset_sctlr = 0x30c50838; in aarch64_a55_initfn()
283 cpu->gic_num_lrs = 4; in aarch64_a55_initfn()
284 cpu->gic_vpribits = 5; in aarch64_a55_initfn()
285 cpu->gic_vprebits = 5; in aarch64_a55_initfn()
286 cpu->gic_pribits = 5; in aarch64_a55_initfn()
288 cpu->isar.mvfr0 = 0x10110222; in aarch64_a55_initfn()
289 cpu->isar.mvfr1 = 0x13211111; in aarch64_a55_initfn()
290 cpu->isar.mvfr2 = 0x00000043; in aarch64_a55_initfn()
293 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a55_initfn()
298 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a72_initfn() local
300 cpu->dtb_compatible = "arm,cortex-a72"; in aarch64_a72_initfn()
301 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a72_initfn()
302 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a72_initfn()
303 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a72_initfn()
304 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a72_initfn()
305 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a72_initfn()
306 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a72_initfn()
307 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a72_initfn()
308 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a72_initfn()
309 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a72_initfn()
310 cpu->midr = 0x410fd083; in aarch64_a72_initfn()
311 cpu->revidr = 0x00000000; in aarch64_a72_initfn()
312 cpu->reset_fpsid = 0x41034080; in aarch64_a72_initfn()
313 cpu->isar.mvfr0 = 0x10110222; in aarch64_a72_initfn()
314 cpu->isar.mvfr1 = 0x12111111; in aarch64_a72_initfn()
315 cpu->isar.mvfr2 = 0x00000043; in aarch64_a72_initfn()
316 cpu->ctr = 0x8444c004; in aarch64_a72_initfn()
317 cpu->reset_sctlr = 0x00c50838; in aarch64_a72_initfn()
318 cpu->isar.id_pfr0 = 0x00000131; in aarch64_a72_initfn()
319 cpu->isar.id_pfr1 = 0x00011011; in aarch64_a72_initfn()
320 cpu->isar.id_dfr0 = 0x03010066; in aarch64_a72_initfn()
321 cpu->id_afr0 = 0x00000000; in aarch64_a72_initfn()
322 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a72_initfn()
323 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a72_initfn()
324 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a72_initfn()
325 cpu->isar.id_mmfr3 = 0x02102211; in aarch64_a72_initfn()
326 cpu->isar.id_isar0 = 0x02101110; in aarch64_a72_initfn()
327 cpu->isar.id_isar1 = 0x13112111; in aarch64_a72_initfn()
328 cpu->isar.id_isar2 = 0x21232042; in aarch64_a72_initfn()
329 cpu->isar.id_isar3 = 0x01112131; in aarch64_a72_initfn()
330 cpu->isar.id_isar4 = 0x00011142; in aarch64_a72_initfn()
331 cpu->isar.id_isar5 = 0x00011121; in aarch64_a72_initfn()
332 cpu->isar.id_aa64pfr0 = 0x00002222; in aarch64_a72_initfn()
333 cpu->isar.id_aa64dfr0 = 0x10305106; in aarch64_a72_initfn()
334 cpu->isar.id_aa64isar0 = 0x00011120; in aarch64_a72_initfn()
335 cpu->isar.id_aa64mmfr0 = 0x00001124; in aarch64_a72_initfn()
336 cpu->isar.dbgdidr = 0x3516d000; in aarch64_a72_initfn()
337 cpu->isar.dbgdevid = 0x01110f13; in aarch64_a72_initfn()
338 cpu->isar.dbgdevid1 = 0x2; in aarch64_a72_initfn()
339 cpu->isar.reset_pmcr_el0 = 0x41023000; in aarch64_a72_initfn()
340 cpu->clidr = 0x0a200023; in aarch64_a72_initfn()
341 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */ in aarch64_a72_initfn()
342 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ in aarch64_a72_initfn()
343 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */ in aarch64_a72_initfn()
344 cpu->dcz_blocksize = 4; /* 64 bytes */ in aarch64_a72_initfn()
345 cpu->gic_num_lrs = 4; in aarch64_a72_initfn()
346 cpu->gic_vpribits = 5; in aarch64_a72_initfn()
347 cpu->gic_vprebits = 5; in aarch64_a72_initfn()
348 cpu->gic_pribits = 5; in aarch64_a72_initfn()
349 define_cortex_a72_a57_a53_cp_reginfo(cpu); in aarch64_a72_initfn()
354 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a76_initfn() local
356 cpu->dtb_compatible = "arm,cortex-a76"; in aarch64_a76_initfn()
357 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a76_initfn()
358 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a76_initfn()
359 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a76_initfn()
360 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a76_initfn()
361 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a76_initfn()
362 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a76_initfn()
363 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a76_initfn()
364 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a76_initfn()
365 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a76_initfn()
368 cpu->clidr = 0x82000023; in aarch64_a76_initfn()
369 cpu->ctr = 0x8444C004; in aarch64_a76_initfn()
370 cpu->dcz_blocksize = 4; in aarch64_a76_initfn()
371 cpu->isar.id_aa64dfr0 = 0x0000000010305408ull; in aarch64_a76_initfn()
372 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_a76_initfn()
373 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_a76_initfn()
374 cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull; in aarch64_a76_initfn()
375 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a76_initfn()
376 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_a76_initfn()
377 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_a76_initfn()
378 cpu->isar.id_aa64pfr1 = 0x0000000000000010ull; in aarch64_a76_initfn()
379 cpu->id_afr0 = 0x00000000; in aarch64_a76_initfn()
380 cpu->isar.id_dfr0 = 0x04010088; in aarch64_a76_initfn()
381 cpu->isar.id_isar0 = 0x02101110; in aarch64_a76_initfn()
382 cpu->isar.id_isar1 = 0x13112111; in aarch64_a76_initfn()
383 cpu->isar.id_isar2 = 0x21232042; in aarch64_a76_initfn()
384 cpu->isar.id_isar3 = 0x01112131; in aarch64_a76_initfn()
385 cpu->isar.id_isar4 = 0x00010142; in aarch64_a76_initfn()
386 cpu->isar.id_isar5 = 0x01011121; in aarch64_a76_initfn()
387 cpu->isar.id_isar6 = 0x00000010; in aarch64_a76_initfn()
388 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a76_initfn()
389 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a76_initfn()
390 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a76_initfn()
391 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a76_initfn()
392 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_a76_initfn()
393 cpu->isar.id_pfr0 = 0x10010131; in aarch64_a76_initfn()
394 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a76_initfn()
395 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a76_initfn()
396 cpu->midr = 0x414fd0b1; /* r4p1 */ in aarch64_a76_initfn()
397 cpu->revidr = 0; in aarch64_a76_initfn()
400 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ in aarch64_a76_initfn()
401 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ in aarch64_a76_initfn()
402 cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */ in aarch64_a76_initfn()
405 cpu->reset_sctlr = 0x30c50838; in aarch64_a76_initfn()
408 cpu->gic_num_lrs = 4; in aarch64_a76_initfn()
409 cpu->gic_vpribits = 5; in aarch64_a76_initfn()
410 cpu->gic_vprebits = 5; in aarch64_a76_initfn()
411 cpu->gic_pribits = 5; in aarch64_a76_initfn()
414 cpu->isar.mvfr0 = 0x10110222; in aarch64_a76_initfn()
415 cpu->isar.mvfr1 = 0x13211111; in aarch64_a76_initfn()
416 cpu->isar.mvfr2 = 0x00000043; in aarch64_a76_initfn()
419 cpu->isar.reset_pmcr_el0 = 0x410b3000; in aarch64_a76_initfn()
424 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a64fx_initfn() local
426 cpu->dtb_compatible = "arm,a64fx"; in aarch64_a64fx_initfn()
427 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a64fx_initfn()
428 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a64fx_initfn()
429 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a64fx_initfn()
430 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a64fx_initfn()
431 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a64fx_initfn()
432 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a64fx_initfn()
433 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a64fx_initfn()
434 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a64fx_initfn()
435 cpu->midr = 0x461f0010; in aarch64_a64fx_initfn()
436 cpu->revidr = 0x00000000; in aarch64_a64fx_initfn()
437 cpu->ctr = 0x86668006; in aarch64_a64fx_initfn()
438 cpu->reset_sctlr = 0x30000180; in aarch64_a64fx_initfn()
439 cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */ in aarch64_a64fx_initfn()
440 cpu->isar.id_aa64pfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
441 cpu->isar.id_aa64dfr0 = 0x0000000010305408; in aarch64_a64fx_initfn()
442 cpu->isar.id_aa64dfr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
443 cpu->id_aa64afr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
444 cpu->id_aa64afr1 = 0x0000000000000000; in aarch64_a64fx_initfn()
445 cpu->isar.id_aa64mmfr0 = 0x0000000000001122; in aarch64_a64fx_initfn()
446 cpu->isar.id_aa64mmfr1 = 0x0000000011212100; in aarch64_a64fx_initfn()
447 cpu->isar.id_aa64mmfr2 = 0x0000000000001011; in aarch64_a64fx_initfn()
448 cpu->isar.id_aa64isar0 = 0x0000000010211120; in aarch64_a64fx_initfn()
449 cpu->isar.id_aa64isar1 = 0x0000000000010001; in aarch64_a64fx_initfn()
450 cpu->isar.id_aa64zfr0 = 0x0000000000000000; in aarch64_a64fx_initfn()
451 cpu->clidr = 0x0000000080000023; in aarch64_a64fx_initfn()
452 cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */ in aarch64_a64fx_initfn()
453 cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */ in aarch64_a64fx_initfn()
454 cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */ in aarch64_a64fx_initfn()
455 cpu->dcz_blocksize = 6; /* 256 bytes */ in aarch64_a64fx_initfn()
456 cpu->gic_num_lrs = 4; in aarch64_a64fx_initfn()
457 cpu->gic_vpribits = 5; in aarch64_a64fx_initfn()
458 cpu->gic_vprebits = 5; in aarch64_a64fx_initfn()
459 cpu->gic_pribits = 5; in aarch64_a64fx_initfn()
463 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_a64fx_initfn()
467 cpu->isar.reset_pmcr_el0 = 0x46014040; in aarch64_a64fx_initfn()
561 static void define_neoverse_n1_cp_reginfo(ARMCPU *cpu) in define_neoverse_n1_cp_reginfo() argument
563 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); in define_neoverse_n1_cp_reginfo()
582 static void define_neoverse_v1_cp_reginfo(ARMCPU *cpu) in define_neoverse_v1_cp_reginfo() argument
588 define_arm_cp_regs(cpu, neoverse_n1_cp_reginfo); in define_neoverse_v1_cp_reginfo()
589 define_arm_cp_regs(cpu, neoverse_v1_cp_reginfo); in define_neoverse_v1_cp_reginfo()
594 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_n1_initfn() local
596 cpu->dtb_compatible = "arm,neoverse-n1"; in aarch64_neoverse_n1_initfn()
597 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_n1_initfn()
598 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_n1_initfn()
599 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_n1_initfn()
600 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_n1_initfn()
601 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_n1_initfn()
602 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_n1_initfn()
603 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_n1_initfn()
604 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n1_initfn()
605 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_n1_initfn()
608 cpu->clidr = 0x82000023; in aarch64_neoverse_n1_initfn()
609 cpu->ctr = 0x8444c004; in aarch64_neoverse_n1_initfn()
610 cpu->dcz_blocksize = 4; in aarch64_neoverse_n1_initfn()
611 cpu->isar.id_aa64dfr0 = 0x0000000110305408ull; in aarch64_neoverse_n1_initfn()
612 cpu->isar.id_aa64isar0 = 0x0000100010211120ull; in aarch64_neoverse_n1_initfn()
613 cpu->isar.id_aa64isar1 = 0x0000000000100001ull; in aarch64_neoverse_n1_initfn()
614 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_n1_initfn()
615 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n1_initfn()
616 cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull; in aarch64_neoverse_n1_initfn()
617 cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
618 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_n1_initfn()
619 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_n1_initfn()
620 cpu->isar.id_dfr0 = 0x04010088; in aarch64_neoverse_n1_initfn()
621 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n1_initfn()
622 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n1_initfn()
623 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n1_initfn()
624 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n1_initfn()
625 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n1_initfn()
626 cpu->isar.id_isar5 = 0x01011121; in aarch64_neoverse_n1_initfn()
627 cpu->isar.id_isar6 = 0x00000010; in aarch64_neoverse_n1_initfn()
628 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n1_initfn()
629 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n1_initfn()
630 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n1_initfn()
631 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n1_initfn()
632 cpu->isar.id_mmfr4 = 0x00021110; in aarch64_neoverse_n1_initfn()
633 cpu->isar.id_pfr0 = 0x10010131; in aarch64_neoverse_n1_initfn()
634 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n1_initfn()
635 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n1_initfn()
636 cpu->midr = 0x414fd0c1; /* r4p1 */ in aarch64_neoverse_n1_initfn()
637 cpu->revidr = 0; in aarch64_neoverse_n1_initfn()
640 cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */ in aarch64_neoverse_n1_initfn()
641 cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */ in aarch64_neoverse_n1_initfn()
642 cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */ in aarch64_neoverse_n1_initfn()
645 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n1_initfn()
648 cpu->gic_num_lrs = 4; in aarch64_neoverse_n1_initfn()
649 cpu->gic_vpribits = 5; in aarch64_neoverse_n1_initfn()
650 cpu->gic_vprebits = 5; in aarch64_neoverse_n1_initfn()
651 cpu->gic_pribits = 5; in aarch64_neoverse_n1_initfn()
654 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n1_initfn()
655 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n1_initfn()
656 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n1_initfn()
659 cpu->isar.reset_pmcr_el0 = 0x410c3000; in aarch64_neoverse_n1_initfn()
661 define_neoverse_n1_cp_reginfo(cpu); in aarch64_neoverse_n1_initfn()
666 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_v1_initfn() local
668 cpu->dtb_compatible = "arm,neoverse-v1"; in aarch64_neoverse_v1_initfn()
669 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_v1_initfn()
670 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_v1_initfn()
671 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_v1_initfn()
672 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_v1_initfn()
673 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_v1_initfn()
674 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_v1_initfn()
675 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_v1_initfn()
676 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_v1_initfn()
677 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_v1_initfn()
680 cpu->clidr = 0x82000023; in aarch64_neoverse_v1_initfn()
681 cpu->ctr = 0xb444c004; /* With DIC and IDC set */ in aarch64_neoverse_v1_initfn()
682 cpu->dcz_blocksize = 4; in aarch64_neoverse_v1_initfn()
683 cpu->id_aa64afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
684 cpu->id_aa64afr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
685 cpu->isar.id_aa64dfr0 = 0x000001f210305519ull; in aarch64_neoverse_v1_initfn()
686 cpu->isar.id_aa64dfr1 = 0x00000000; in aarch64_neoverse_v1_initfn()
687 cpu->isar.id_aa64isar0 = 0x1011111110212120ull; /* with FEAT_RNG */ in aarch64_neoverse_v1_initfn()
688 cpu->isar.id_aa64isar1 = 0x0111000001211032ull; in aarch64_neoverse_v1_initfn()
689 cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull; in aarch64_neoverse_v1_initfn()
690 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_v1_initfn()
691 cpu->isar.id_aa64mmfr2 = 0x0220011102101011ull; in aarch64_neoverse_v1_initfn()
692 cpu->isar.id_aa64pfr0 = 0x1101110120111112ull; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
693 cpu->isar.id_aa64pfr1 = 0x0000000000000020ull; in aarch64_neoverse_v1_initfn()
694 cpu->id_afr0 = 0x00000000; in aarch64_neoverse_v1_initfn()
695 cpu->isar.id_dfr0 = 0x15011099; in aarch64_neoverse_v1_initfn()
696 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_v1_initfn()
697 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_v1_initfn()
698 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_v1_initfn()
699 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_v1_initfn()
700 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_v1_initfn()
701 cpu->isar.id_isar5 = 0x11011121; in aarch64_neoverse_v1_initfn()
702 cpu->isar.id_isar6 = 0x01100111; in aarch64_neoverse_v1_initfn()
703 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_v1_initfn()
704 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_v1_initfn()
705 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_v1_initfn()
706 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_v1_initfn()
707 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_v1_initfn()
708 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_v1_initfn()
709 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_v1_initfn()
710 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_v1_initfn()
711 cpu->midr = 0x411FD402; /* r1p2 */ in aarch64_neoverse_v1_initfn()
712 cpu->revidr = 0; in aarch64_neoverse_v1_initfn()
724 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ in aarch64_neoverse_v1_initfn()
725 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ in aarch64_neoverse_v1_initfn()
726 cpu->ccsidr[2] = make_ccsidr64(8, 64, 1 * MiB); /* L2 cache */ in aarch64_neoverse_v1_initfn()
729 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_v1_initfn()
732 cpu->gic_num_lrs = 4; in aarch64_neoverse_v1_initfn()
733 cpu->gic_vpribits = 5; in aarch64_neoverse_v1_initfn()
734 cpu->gic_vprebits = 5; in aarch64_neoverse_v1_initfn()
735 cpu->gic_pribits = 5; in aarch64_neoverse_v1_initfn()
738 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_v1_initfn()
739 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_v1_initfn()
740 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_v1_initfn()
743 cpu->isar.id_aa64zfr0 = 0x0000100000100000; in aarch64_neoverse_v1_initfn()
744 cpu->sve_vq.supported = (1 << 0) /* 128bit */ in aarch64_neoverse_v1_initfn()
748 cpu->isar.reset_pmcr_el0 = 0x41213000; in aarch64_neoverse_v1_initfn()
750 define_neoverse_v1_cp_reginfo(cpu); in aarch64_neoverse_v1_initfn()
889 ARMCPU *cpu = ARM_CPU(obj); in aarch64_a710_initfn() local
891 cpu->dtb_compatible = "arm,cortex-a710"; in aarch64_a710_initfn()
892 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_a710_initfn()
893 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_a710_initfn()
894 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_a710_initfn()
895 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_a710_initfn()
896 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_a710_initfn()
897 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_a710_initfn()
898 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_a710_initfn()
899 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_a710_initfn()
900 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_a710_initfn()
903 cpu->midr = 0x412FD471; /* r2p1 */ in aarch64_a710_initfn()
904 cpu->revidr = 0; in aarch64_a710_initfn()
905 cpu->isar.id_pfr0 = 0x21110131; in aarch64_a710_initfn()
906 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_a710_initfn()
907 cpu->isar.id_dfr0 = 0x16011099; in aarch64_a710_initfn()
908 cpu->id_afr0 = 0; in aarch64_a710_initfn()
909 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_a710_initfn()
910 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_a710_initfn()
911 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_a710_initfn()
912 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_a710_initfn()
913 cpu->isar.id_isar0 = 0x02101110; in aarch64_a710_initfn()
914 cpu->isar.id_isar1 = 0x13112111; in aarch64_a710_initfn()
915 cpu->isar.id_isar2 = 0x21232042; in aarch64_a710_initfn()
916 cpu->isar.id_isar3 = 0x01112131; in aarch64_a710_initfn()
917 cpu->isar.id_isar4 = 0x00010142; in aarch64_a710_initfn()
918 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_a710_initfn()
919 cpu->isar.id_mmfr4 = 0x21021110; in aarch64_a710_initfn()
920 cpu->isar.id_isar6 = 0x01111111; in aarch64_a710_initfn()
921 cpu->isar.mvfr0 = 0x10110222; in aarch64_a710_initfn()
922 cpu->isar.mvfr1 = 0x13211111; in aarch64_a710_initfn()
923 cpu->isar.mvfr2 = 0x00000043; in aarch64_a710_initfn()
924 cpu->isar.id_pfr2 = 0x00000011; in aarch64_a710_initfn()
925 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_a710_initfn()
926 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_a710_initfn()
927 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_a710_initfn()
928 cpu->isar.id_aa64dfr0 = 0x000011f010305619ull; in aarch64_a710_initfn()
929 cpu->isar.id_aa64dfr1 = 0; in aarch64_a710_initfn()
930 cpu->id_aa64afr0 = 0; in aarch64_a710_initfn()
931 cpu->id_aa64afr1 = 0; in aarch64_a710_initfn()
932 cpu->isar.id_aa64isar0 = 0x0221111110212120ull; /* with Crypto */ in aarch64_a710_initfn()
933 cpu->isar.id_aa64isar1 = 0x0010111101211052ull; in aarch64_a710_initfn()
934 cpu->isar.id_aa64mmfr0 = 0x0000022200101122ull; in aarch64_a710_initfn()
935 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_a710_initfn()
936 cpu->isar.id_aa64mmfr2 = 0x1221011110101011ull; in aarch64_a710_initfn()
937 cpu->clidr = 0x0000001482000023ull; in aarch64_a710_initfn()
938 cpu->gm_blocksize = 4; in aarch64_a710_initfn()
939 cpu->ctr = 0x000000049444c004ull; in aarch64_a710_initfn()
940 cpu->dcz_blocksize = 4; in aarch64_a710_initfn()
944 cpu->isar.reset_pmcr_el0 = 0xa000; /* with 20 counters */ in aarch64_a710_initfn()
947 cpu->gic_num_lrs = 4; in aarch64_a710_initfn()
948 cpu->gic_vpribits = 5; in aarch64_a710_initfn()
949 cpu->gic_vprebits = 5; in aarch64_a710_initfn()
950 cpu->gic_pribits = 5; in aarch64_a710_initfn()
953 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_a710_initfn()
962 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ in aarch64_a710_initfn()
963 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ in aarch64_a710_initfn()
964 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ in aarch64_a710_initfn()
967 cpu->reset_sctlr = 0x30c50838; in aarch64_a710_initfn()
969 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); in aarch64_a710_initfn()
987 ARMCPU *cpu = ARM_CPU(obj); in aarch64_neoverse_n2_initfn() local
989 cpu->dtb_compatible = "arm,neoverse-n2"; in aarch64_neoverse_n2_initfn()
990 set_feature(&cpu->env, ARM_FEATURE_V8); in aarch64_neoverse_n2_initfn()
991 set_feature(&cpu->env, ARM_FEATURE_NEON); in aarch64_neoverse_n2_initfn()
992 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); in aarch64_neoverse_n2_initfn()
993 set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_neoverse_n2_initfn()
994 set_feature(&cpu->env, ARM_FEATURE_AARCH64); in aarch64_neoverse_n2_initfn()
995 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); in aarch64_neoverse_n2_initfn()
996 set_feature(&cpu->env, ARM_FEATURE_EL2); in aarch64_neoverse_n2_initfn()
997 set_feature(&cpu->env, ARM_FEATURE_EL3); in aarch64_neoverse_n2_initfn()
998 set_feature(&cpu->env, ARM_FEATURE_PMU); in aarch64_neoverse_n2_initfn()
1001 cpu->midr = 0x410FD493; /* r0p3 */ in aarch64_neoverse_n2_initfn()
1002 cpu->revidr = 0; in aarch64_neoverse_n2_initfn()
1003 cpu->isar.id_pfr0 = 0x21110131; in aarch64_neoverse_n2_initfn()
1004 cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1005 cpu->isar.id_dfr0 = 0x16011099; in aarch64_neoverse_n2_initfn()
1006 cpu->id_afr0 = 0; in aarch64_neoverse_n2_initfn()
1007 cpu->isar.id_mmfr0 = 0x10201105; in aarch64_neoverse_n2_initfn()
1008 cpu->isar.id_mmfr1 = 0x40000000; in aarch64_neoverse_n2_initfn()
1009 cpu->isar.id_mmfr2 = 0x01260000; in aarch64_neoverse_n2_initfn()
1010 cpu->isar.id_mmfr3 = 0x02122211; in aarch64_neoverse_n2_initfn()
1011 cpu->isar.id_isar0 = 0x02101110; in aarch64_neoverse_n2_initfn()
1012 cpu->isar.id_isar1 = 0x13112111; in aarch64_neoverse_n2_initfn()
1013 cpu->isar.id_isar2 = 0x21232042; in aarch64_neoverse_n2_initfn()
1014 cpu->isar.id_isar3 = 0x01112131; in aarch64_neoverse_n2_initfn()
1015 cpu->isar.id_isar4 = 0x00010142; in aarch64_neoverse_n2_initfn()
1016 cpu->isar.id_isar5 = 0x11011121; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1017 cpu->isar.id_mmfr4 = 0x01021110; in aarch64_neoverse_n2_initfn()
1018 cpu->isar.id_isar6 = 0x01111111; in aarch64_neoverse_n2_initfn()
1019 cpu->isar.mvfr0 = 0x10110222; in aarch64_neoverse_n2_initfn()
1020 cpu->isar.mvfr1 = 0x13211111; in aarch64_neoverse_n2_initfn()
1021 cpu->isar.mvfr2 = 0x00000043; in aarch64_neoverse_n2_initfn()
1022 cpu->isar.id_pfr2 = 0x00000011; in aarch64_neoverse_n2_initfn()
1023 cpu->isar.id_aa64pfr0 = 0x1201111120111112ull; /* GIC filled in later */ in aarch64_neoverse_n2_initfn()
1024 cpu->isar.id_aa64pfr1 = 0x0000000000000221ull; in aarch64_neoverse_n2_initfn()
1025 cpu->isar.id_aa64zfr0 = 0x0000110100110021ull; /* with Crypto */ in aarch64_neoverse_n2_initfn()
1026 cpu->isar.id_aa64dfr0 = 0x000011f210305619ull; in aarch64_neoverse_n2_initfn()
1027 cpu->isar.id_aa64dfr1 = 0; in aarch64_neoverse_n2_initfn()
1028 cpu->id_aa64afr0 = 0; in aarch64_neoverse_n2_initfn()
1029 cpu->id_aa64afr1 = 0; in aarch64_neoverse_n2_initfn()
1030 cpu->isar.id_aa64isar0 = 0x1221111110212120ull; /* with Crypto and FEAT_RNG */ in aarch64_neoverse_n2_initfn()
1031 cpu->isar.id_aa64isar1 = 0x0011111101211052ull; in aarch64_neoverse_n2_initfn()
1032 cpu->isar.id_aa64mmfr0 = 0x0000022200101125ull; in aarch64_neoverse_n2_initfn()
1033 cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull; in aarch64_neoverse_n2_initfn()
1034 cpu->isar.id_aa64mmfr2 = 0x1221011112101011ull; in aarch64_neoverse_n2_initfn()
1035 cpu->clidr = 0x0000001482000023ull; in aarch64_neoverse_n2_initfn()
1036 cpu->gm_blocksize = 4; in aarch64_neoverse_n2_initfn()
1037 cpu->ctr = 0x00000004b444c004ull; in aarch64_neoverse_n2_initfn()
1038 cpu->dcz_blocksize = 4; in aarch64_neoverse_n2_initfn()
1042 cpu->isar.reset_pmcr_el0 = 0x3000; /* with 6 counters */ in aarch64_neoverse_n2_initfn()
1045 cpu->gic_num_lrs = 4; in aarch64_neoverse_n2_initfn()
1046 cpu->gic_vpribits = 5; in aarch64_neoverse_n2_initfn()
1047 cpu->gic_vprebits = 5; in aarch64_neoverse_n2_initfn()
1048 cpu->gic_pribits = 5; in aarch64_neoverse_n2_initfn()
1051 cpu->sve_vq.supported = 1 << 0; /* 128bit */ in aarch64_neoverse_n2_initfn()
1060 cpu->ccsidr[0] = make_ccsidr64(4, 64, 64 * KiB); /* L1 dcache */ in aarch64_neoverse_n2_initfn()
1061 cpu->ccsidr[1] = cpu->ccsidr[0]; /* L1 icache */ in aarch64_neoverse_n2_initfn()
1062 cpu->ccsidr[2] = make_ccsidr64(8, 64, 512 * KiB); /* L2 cache */ in aarch64_neoverse_n2_initfn()
1065 cpu->reset_sctlr = 0x30c50838; in aarch64_neoverse_n2_initfn()
1071 define_arm_cp_regs(cpu, cortex_a710_cp_reginfo); in aarch64_neoverse_n2_initfn()
1072 define_arm_cp_regs(cpu, neoverse_n2_cp_reginfo); in aarch64_neoverse_n2_initfn()
1085 ARMCPU *cpu = ARM_CPU(obj); in aarch64_max_tcg_initfn() local
1096 unset_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); in aarch64_max_tcg_initfn()
1115 cpu->midr = t; in aarch64_max_tcg_initfn()
1121 u = cpu->clidr; in aarch64_max_tcg_initfn()
1124 cpu->clidr = u; in aarch64_max_tcg_initfn()
1131 t = cpu->ctr; in aarch64_max_tcg_initfn()
1134 cpu->ctr = t; in aarch64_max_tcg_initfn()
1136 t = cpu->isar.id_aa64isar0; in aarch64_max_tcg_initfn()
1151 cpu->isar.id_aa64isar0 = t; in aarch64_max_tcg_initfn()
1153 t = cpu->isar.id_aa64isar1; in aarch64_max_tcg_initfn()
1166 cpu->isar.id_aa64isar1 = t; in aarch64_max_tcg_initfn()
1168 t = cpu->isar.id_aa64isar2; in aarch64_max_tcg_initfn()
1171 cpu->isar.id_aa64isar2 = t; in aarch64_max_tcg_initfn()
1173 t = cpu->isar.id_aa64pfr0; in aarch64_max_tcg_initfn()
1182 cpu->isar.id_aa64pfr0 = t; in aarch64_max_tcg_initfn()
1184 t = cpu->isar.id_aa64pfr1; in aarch64_max_tcg_initfn()
1197 cpu->isar.id_aa64pfr1 = t; in aarch64_max_tcg_initfn()
1199 t = cpu->isar.id_aa64mmfr0; in aarch64_max_tcg_initfn()
1207 cpu->isar.id_aa64mmfr0 = t; in aarch64_max_tcg_initfn()
1209 t = cpu->isar.id_aa64mmfr1; in aarch64_max_tcg_initfn()
1220 cpu->isar.id_aa64mmfr1 = t; in aarch64_max_tcg_initfn()
1222 t = cpu->isar.id_aa64mmfr2; in aarch64_max_tcg_initfn()
1236 cpu->isar.id_aa64mmfr2 = t; in aarch64_max_tcg_initfn()
1238 t = cpu->isar.id_aa64mmfr3; in aarch64_max_tcg_initfn()
1240 cpu->isar.id_aa64mmfr3 = t; in aarch64_max_tcg_initfn()
1242 t = cpu->isar.id_aa64zfr0; in aarch64_max_tcg_initfn()
1252 cpu->isar.id_aa64zfr0 = t; in aarch64_max_tcg_initfn()
1254 t = cpu->isar.id_aa64dfr0; in aarch64_max_tcg_initfn()
1258 cpu->isar.id_aa64dfr0 = t; in aarch64_max_tcg_initfn()
1260 t = cpu->isar.id_aa64smfr0; in aarch64_max_tcg_initfn()
1268 cpu->isar.id_aa64smfr0 = t; in aarch64_max_tcg_initfn()
1271 aa32_max_features(cpu); in aarch64_max_tcg_initfn()
1278 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ in aarch64_max_tcg_initfn()
1279 cpu->dcz_blocksize = 7; /* 512 bytes */ in aarch64_max_tcg_initfn()
1281 cpu->gm_blocksize = 6; /* 256 bytes */ in aarch64_max_tcg_initfn()
1283 cpu->sve_vq.supported = MAKE_64BIT_MASK(0, ARM_MAX_VQ); in aarch64_max_tcg_initfn()
1284 cpu->sme_vq.supported = SVE_VQ_POW2_MAP; in aarch64_max_tcg_initfn()