Lines Matching refs:i
79 for (int i = 0; i < ctx->future_vregs_idx; i++) { in ctx_future_vreg_off() local
80 if (ctx->future_vregs_num[i] == regnum) { in ctx_future_vreg_off()
81 return offsetof(CPUHexagonState, future_VRegs[i]); in ctx_future_vreg_off()
87 for (int i = 0; i < num; i++) { in ctx_future_vreg_off() local
88 ctx->future_vregs_num[ctx->future_vregs_idx + i] = regnum++; in ctx_future_vreg_off()
101 for (int i = 0; i < ctx->tmp_vregs_idx; i++) { in ctx_tmp_vreg_off() local
102 if (ctx->tmp_vregs_num[i] == regnum) { in ctx_tmp_vreg_off()
103 return offsetof(CPUHexagonState, tmp_VRegs[i]); in ctx_tmp_vreg_off()
109 for (int i = 0; i < num; i++) { in ctx_tmp_vreg_off() local
110 ctx->tmp_vregs_num[ctx->tmp_vregs_idx + i] = regnum++; in ctx_tmp_vreg_off()
241 for (int i = 0; i < nwords; i++) { in read_packet_words() local
242 HEX_DEBUG_LOG("0x%x, ", words[i]); in read_packet_words()
251 for (int i = 0; i < pkt->num_insns; i++) { in check_for_attrib() local
252 if (GET_ATTRIB(pkt->insn[i].opcode, attrib)) { in check_for_attrib()
262 for (int i = 0; i < pkt->num_insns; i++) { in need_slot_cancelled() local
263 uint16_t opcode = pkt->insn[i].opcode; in need_slot_cancelled()
277 for (int i = 0; i < pkt->num_insns; i++) { in need_next_PC() local
278 uint16_t opcode = pkt->insn[i].opcode; in need_next_PC()
371 for (int i = 0; i < ctx->reg_log_idx; i++) { in need_commit() local
372 int rnum = ctx->reg_log[i]; in need_commit()
410 for (int i = 0; i < pkt->num_insns; i++) { in analyze_packet() local
411 Insn *insn = &pkt->insn[i]; in analyze_packet()
428 int i; in gen_start_packet() local
448 for (i = 0; i < STORES_MAX; i++) { in gen_start_packet()
449 ctx->store_width[i] = 0; in gen_start_packet()
453 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { in gen_start_packet()
454 ctx->new_value[i] = NULL; in gen_start_packet()
456 for (i = 0; i < NUM_PREGS; i++) { in gen_start_packet()
457 ctx->new_pred_value[i] = NULL; in gen_start_packet()
495 i = find_first_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS); in gen_start_packet()
496 while (i < TOTAL_PER_THREAD_REGS) { in gen_start_packet()
497 tcg_gen_mov_tl(get_result_gpr(ctx, i), hex_gpr[i]); in gen_start_packet()
498 i = find_next_bit(ctx->predicated_regs, TOTAL_PER_THREAD_REGS, in gen_start_packet()
499 i + 1); in gen_start_packet()
508 for (i = 0; i < ctx->preg_log_idx; i++) { in gen_start_packet()
509 int pred_num = ctx->preg_log[i]; in gen_start_packet()
517 i = find_first_bit(ctx->predicated_future_vregs, NUM_VREGS); in gen_start_packet()
518 while (i < NUM_VREGS) { in gen_start_packet()
520 ctx_future_vreg_off(ctx, i, 1, true); in gen_start_packet()
521 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); in gen_start_packet()
526 i = find_next_bit(ctx->predicated_future_vregs, NUM_VREGS, i + 1); in gen_start_packet()
530 i = find_first_bit(ctx->predicated_tmp_vregs, NUM_VREGS); in gen_start_packet()
531 while (i < NUM_VREGS) { in gen_start_packet()
533 ctx_tmp_vreg_off(ctx, i, 1, true); in gen_start_packet()
534 intptr_t src_off = offsetof(CPUHexagonState, VRegs[i]); in gen_start_packet()
539 i = find_next_bit(ctx->predicated_tmp_vregs, NUM_VREGS, i + 1); in gen_start_packet()
551 for (int i = 0; i < pkt->num_insns; i++) { in is_gather_store_insn() local
552 Insn *in = &pkt->insn[i]; in is_gather_store_insn()
603 int i; in gen_reg_writes() local
610 for (i = 0; i < ctx->reg_log_idx; i++) { in gen_reg_writes()
611 int reg_num = ctx->reg_log[i]; in gen_reg_writes()
632 for (int i = 0; i < ctx->preg_log_idx; i++) { in gen_pred_writes() local
633 int pred_num = ctx->preg_log[i]; in gen_pred_writes()
649 for (int i = 0; i < pkt->num_insns; i++) { in slot_is_predicated() local
650 if (pkt->insn[i].slot == slot_num) { in slot_is_predicated()
651 return GET_ATTRIB(pkt->insn[i].opcode, A_CONDEXEC); in slot_is_predicated()
773 int i; in pkt_has_hvx_store() local
774 for (i = 0; i < pkt->num_insns; i++) { in pkt_has_hvx_store()
775 int opcode = pkt->insn[i].opcode; in pkt_has_hvx_store()
785 int i; in gen_commit_hvx() local
799 for (i = 0; i < ctx->vreg_log_idx; i++) { in gen_commit_hvx()
800 int rnum = ctx->vreg_log[i]; in gen_commit_hvx()
814 for (i = 0; i < ctx->qreg_log_idx; i++) { in gen_commit_hvx()
815 int rnum = ctx->qreg_log[i]; in gen_commit_hvx()
835 for (int i = 0; i < num_insns; i++) { in update_exec_counters() local
836 if (!pkt->insn[i].is_endloop && in update_exec_counters()
837 !pkt->insn[i].part1 && in update_exec_counters()
838 !GET_ATTRIB(pkt->insn[i].opcode, A_IT_NOP)) { in update_exec_counters()
841 if (GET_ATTRIB(pkt->insn[i].opcode, A_CVI)) { in update_exec_counters()
967 int i; in decode_and_translate_packet() local
980 for (i = 0; i < pkt.num_insns; i++) { in decode_and_translate_packet()
981 ctx->insn = &pkt.insn[i]; in decode_and_translate_packet()
1107 int i; in hexagon_translate_init() local
1111 for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { in hexagon_translate_init()
1112 hex_gpr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1113 offsetof(CPUHexagonState, gpr[i]), in hexagon_translate_init()
1114 hexagon_regnames[i]); in hexagon_translate_init()
1117 snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", in hexagon_translate_init()
1118 hexagon_regnames[i]); in hexagon_translate_init()
1119 hex_reg_written[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1120 offsetof(CPUHexagonState, reg_written[i]), in hexagon_translate_init()
1121 reg_written_names[i]); in hexagon_translate_init()
1127 for (i = 0; i < NUM_PREGS; i++) { in hexagon_translate_init()
1128 hex_pred[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1129 offsetof(CPUHexagonState, pred[i]), in hexagon_translate_init()
1130 hexagon_prednames[i]); in hexagon_translate_init()
1140 for (i = 0; i < STORES_MAX; i++) { in hexagon_translate_init()
1141 snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i); in hexagon_translate_init()
1142 hex_store_addr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1143 offsetof(CPUHexagonState, mem_log_stores[i].va), in hexagon_translate_init()
1144 store_addr_names[i]); in hexagon_translate_init()
1146 snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i); in hexagon_translate_init()
1147 hex_store_width[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1148 offsetof(CPUHexagonState, mem_log_stores[i].width), in hexagon_translate_init()
1149 store_width_names[i]); in hexagon_translate_init()
1151 snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i); in hexagon_translate_init()
1152 hex_store_val32[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1153 offsetof(CPUHexagonState, mem_log_stores[i].data32), in hexagon_translate_init()
1154 store_val32_names[i]); in hexagon_translate_init()
1156 snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i); in hexagon_translate_init()
1157 hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env, in hexagon_translate_init()
1158 offsetof(CPUHexagonState, mem_log_stores[i].data64), in hexagon_translate_init()
1159 store_val64_names[i]); in hexagon_translate_init()
1161 for (i = 0; i < VSTORES_MAX; i++) { in hexagon_translate_init()
1162 snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i); in hexagon_translate_init()
1163 hex_vstore_addr[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1164 offsetof(CPUHexagonState, vstore[i].va), in hexagon_translate_init()
1165 vstore_addr_names[i]); in hexagon_translate_init()
1167 snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i); in hexagon_translate_init()
1168 hex_vstore_size[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1169 offsetof(CPUHexagonState, vstore[i].size), in hexagon_translate_init()
1170 vstore_size_names[i]); in hexagon_translate_init()
1172 snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i); in hexagon_translate_init()
1173 hex_vstore_pending[i] = tcg_global_mem_new(tcg_env, in hexagon_translate_init()
1174 offsetof(CPUHexagonState, vstore_pending[i]), in hexagon_translate_init()
1175 vstore_pending_names[i]); in hexagon_translate_init()